Method and apparatus for decoding asynchronous biphase coded data frames with variable length

<u>1. Field of the invention</u>

0001The field of the invention is that of decoding digital data organized in frames.

0002More specifically, the invention relates to decoders of two-phase asynchronous data frames, in particular coded according to the Manchester code.

0003The invention can find applications in all fields using Manchester type transmissions, such as that of industrial control or telecommunications, in particular when it is desirable to have simple decoders and at low cost.

0004For example, the invention can be applied to communication in the field of lighting, and in particular to the decoding of asynchronous two-phase frames conforming to the DALI protocol (“Digital Addressable Lighting Interface” or “Digital Addressable Lighting Interface”) . The latter is a standard protocol (IEC 60929) for bus communication intended to communicate light devices with a controller, with simplicity (two-wire connection), reliability (digital signals, Manchester coding) and interoperability (devices from different manufacturers) .

<u>2. Prior art</u>

0005There are methods for decoding two-phase asynchronous frames (typically "Manchester frames"). With these decoding methods, the length L in useful bits of the frames is imperatively fixed and known in advance of the decoding circuit. Indeed, conventionally, a two-phase asynchronous frame comprises L useful bits, preceded by at least one start bit and followed by at least one stop bit. Thus, for example, the DALI protocol provides that each frame is composed of 1 start bit, 16 useful bits (data bits) and 2 stop bits.

0006To the knowledge of the inventors, there is to date no technical solution for performing decoding in a new context where the length L in useful bits would be variable from one frame to another and not known in advance of the circuit decoding.

0007To the knowledge of the inventors, there is also no technical solution allowing the decoder to automatically change operating mode, and in particular to pass from a normal mode to a test mode.

0008Furthermore, Manchester coding is a technique which has been known for a long time and which is applied in many fields. There are several methods to retrieve the corresponding clock in a receiver, and in particular the use of a phase-locked loop (also called PLL, from the English "Phase-Locked Loop") or a precise clock . However, none of these synchronization solutions is satisfactory.

0009With a phase locked loop, the phase of the output signal is locked to that of the input signal, which forces the frequency of the output signal to lock onto the frequency of the input signal, allowing frequency control , therefore a synchronization. A major drawback of this technique is that during the phase locking step which will allow synchronization, the first data transmitted is lost. Another drawback of this technique is that it is expensive and relatively complex to implement, due in particular to the presence of a phase locked loop.

0010For other remote transmission systems, it is necessary to use a precise clock in order to reliably decode the data received. A major drawback of this technique is that it requires knowing at the receiver the speed of the transmission (or "baud rate"). Furthermore, it requires having a precise local clock, both at the transmitter and at the receiver, which makes this technique more expensive and complex to implement.

<u>3. Objectives of the invention</u>

0011The invention particularly aims to overcome these various drawbacks of the state of the art.

0012More specifically, one of the objectives of the present invention is to provide a technique for decoding a two-phase asynchronous data signal in the aforementioned new context where the length L in useful bits can vary from one frame to another and is not known in advance of the decoding circuit.

0013The invention also aims to provide such a technique which is simple and inexpensive.

0014Another objective of the invention is to provide such a technique requiring neither phase-locked loop nor precise clock.

<u>4. Essential features of the invention</u>

0015These various objectives, as well as others which will appear subsequently, are achieved according to the invention using a method of decoding, by an electronic circuit, of a two-phase asynchronous frame carried by an encoded data signal. and comprising L useful bits followed by at least one stop bit. According to the invention, the method comprises a step of automatic detection of the length L in useful bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such as: L_min≤ L ≤ L_max, With l_max= (L_min + k), where k is a predetermined integer greater than or equal to 1.

0016The general principle of the invention therefore consists in placing itself in a new context where the frames transmitted successively do not all have the same length in useful bits and where the decoder does not receive information informing it in advance of the exact number of useful bits included in each transmitted frame, and allowing the decoder to automatically detect the length L of each frame. This avoids the prior sending to the decoder of information on the length L of each frame. Thus, the invention proves to be particularly simple and effective.

0017Different applications can be envisaged in this new context.

0018In a particular embodiment of the invention, said method further comprises a step of selecting an operating mode of the electronic circuit from at least two possible operating modes, depending on the length L detected.

0019Advantageously, said at least two possible operating modes are a normal mode and a test mode.

0020Advantageously, said selection step is such that: if the length L detected is equal to L_min, normal mode is selected; if the length L detected is equal to L_max, the test mode is selected.

0021Advantageously, when the test mode is selected, the electronic circuit treats as a test frame at least one frame received after the frame whose length L has been detected.

0022Preferably, the step of automatically detecting the length L of the frame itself comprises the following successive steps:<ul id="ul0001" list-style="none" compact="compact"><li>a) detection of a possible transition in a portion of the signal carrying the rank bit (L_min + p), with p an integer variable which is initialized to 1;</li><li>b) if no transition is detected, the rank bit (L_min + p) is estimated as a stop bit and the frame is treated as a frame of (L_min + (p- 1)) useful bits;</li><li>c) if a transition is detected, the rank bit (L_min + p) is estimated as a useful bit and:<ul id="ul0002" list-style="none" compact="compact"><li>c-1) if (L_min + p) = L_max, the frame is treated as a frame of (L_min + p) useful bits;</li><li>c-2) if (L_min + p) &lt;L_max, we return to step a) having previously incremented p by one to process a portion of the signal carrying the next bit.</li></ul></li></ul>

0023Preferably, step a) itself includes a windowing step, limiting to a determined time window the detection of a possible transition in the portion of the signal carrying the rank bit (L_min + p).

0024In a preferred embodiment of the invention, the windowing step implements a counter powered by a clock internal to said circuit, and which is incremented from zero to a determined maximum value, then decremented from the determined maximum value down to zero. Furthermore, said determined time window is defined as a time interval during which the current value of the counter is greater than or equal to a predetermined threshold.

0025According to an advantageous characteristic, said determined maximum value of the counter is a predetermined value depending on a transmission frequency and a transfer rate of the data signal.

0026According to an advantageous variant, said determined maximum value of the counter is read from a register having previously memorized the content of the counter upon detection of a transition in the portion of the data signal carrying the bit of rank L_min.

0027Advantageously, said predetermined threshold is equal to half of said determined maximum value of the counter, so that said time window covers approximately 50% of a binary time.

0028Advantageously, in the case where said frame comprises L useful bits followed by a first and a second stop bit, then the step of automatic detection of the length of said frame further comprises a first step of verifying the decision, taken in step b), to treat the frame as a frame of (L_min + (p-1)) useful bits, said first verification step consisting in verifying that the rank bit (L_min + (p + 1)) is a second stop bit.

0029Advantageously, the step of automatically detecting the length of the frame further comprises a second step of verifying the decision, taken during step c-1), to treat the frame as a frame of (L_min + p) useful bits, said second verification step consisting in verifying that the rank bit (L_min + (p + 1)) is a stop bit.

0030In a particular embodiment of the invention, L_max = (L_min + 1), and in that the step for processing the bit of rank L_max itself comprises the following successive stages:<ul id="ul0003" list-style="none" compact="compact"><li>a ') detection of a possible transition in a portion of the signal carrying the bit of rank L_max ;</li><li>b ') if no transition is detected, the bit of rank L_max is estimated as a stop bit and the frame is treated as an L frame_min useful bits;</li><li>c ') if a transition is detected, the bit of rank L_max is estimated as a useful bit and the frame is treated as an L frame_max useful bits.</li></ul>

0031In an advantageous embodiment of the invention, said data signal is encoded according to a Manchester encoding.

0032The invention also relates to a computer program product, comprising program code instructions for executing the steps of the decoding method according to the invention, when said program is executed on a computer.

0033The invention also relates to a storage means, possibly totally or partially removable, readable by a computer, storing a set of instructions executable by said computer to implement the decoding method according to the invention.

0034The invention also relates to an electronic circuit for decoding a two-phase asynchronous frame carried by an encoded data signal and comprising L useful bits followed by at least one stop bit, said circuit comprising means for automatic detection of the length L in useful bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that: L_min ≤ L ≤ L_max, With l_max = (L_min + k), where k is a predetermined integer greater than or equal to 1.

0035Advantageously, said circuit further comprises means for selecting an operating mode of the electronic circuit from at least two possible operating modes, as a function of the length L detected.

0036The invention also relates to a device for controlling at least one item of equipment, this device comprising an electronic decoding circuit according to the invention.

0037Advantageously, the controlled equipment is lighting equipment.

<u>5. List of Figures</u>

0038Other characteristics and advantages of the invention will appear on reading the following description of a preferred embodiment of the invention, given by way of non-limiting example, and the attached drawings, in which:<ul id="ul0004" list-style="dash" compact="compact"><li>FIG. 1 presents a general diagram of a decoder of a frame encoded according to the Manchester principle;</li><li>FIG. 2 presents a flow diagram of a particular embodiment of the method according to the invention;</li><li>FIG. 3 describes the operation of the decoder of FIG. 1, according to the invention, in the form of a block diagram;</li><li>FIG. 4 shows a state machine detailing a particular embodiment of the step of automatic detection of the length of a frame, appearing on the flow diagram of FIG. 2;</li><li>FIG. 5 presents a timing diagram of the various input / output signals and of the intermediate signals of the diagram of FIG. 3, in the case of a frame comprising 17 useful bits and two stop bits;</li><li>FIG. 6 presents a timing diagram of the various input / output signals and of the intermediate signals of the diagram of FIG. 3, in the case of a frame comprising 16 useful bits and a stop bit;</li><li>FIG. 7 presents in detail an example of detection of a 17^th useful bit;</li><li>FIG. 8 presents in detail the detection of a first and a second stop bit.</li></ul>

<u>6. Description of an embodiment of the invention</u>

0039The general principle of the invention is based on an electronic two-phase asynchronous frame decoding circuit making it possible to recover the output of the transmitted data and their transmission clock, whatever the length in useful bits of each frame.

0040The invention uses a simple counter and does not require a precise internal clock or phase-locked loop. This electronic circuit can in particular automatically adapt to any variable transmission speed, even if it does not know the internal clock precisely. It suffices for this to implement a counter deep enough to adapt to a relatively low transmission speed, and a local clock fast enough with respect to a higher transmission speed.

0041It is considered according to the invention that the data frame received at the level of the decoder is of the asynchronous type because it consists of a series of asynchronous binary elements of the receiver. It is also of the two-phase type because the data bits are not encoded by states but by transition bits. This coding is known as Manchester coding.

0042We present, in relation to the <b><u>figure 1</u>,</b> the inputs and outputs of the decoder 14.

0043This decoder 14 has two inputs, the first 11 on which the two-phase asynchronous frames are sent (denoted RxD in the figure) and the second 12 corresponding to the input of the local clock (L_CLK in the figure), also called the internal clock . In the embodiment described, the local clock can be of imprecise frequency, but greater than 16 times the bit rate of the data to be decoded.

0044This decoder 14 also has an output 13 which makes it possible to find the decoded data DATA, placed in parallel over a width of <i>not</i> bits, the number <i>not</i> varying according to the application.

0045The transmitted signal is organized in frames. The two-phase asynchronous frames received on the RxD input 11 of the decoder 14 consist of a start bit (also called “start” bit), are followed by useful bits (also called data bits) and end with a or several stop bits (also called stop bits). The start bit and the useful bits are not encoded by states but by transitions, as illustrated in FIGS. 5 and 6. On the other hand, the stop bits are encoded by states (that is to say by levels).

0046Thus, according to Manchester coding, the useful bits equal to '1' are coded by rising edges and the useful bits equal to '0' are coded by falling edges. The start bit is also encoded according to the Manchester principle.

0047It is understood that the invention presented also applies to any other type of coding where the useful bits are encoded by transitions and not by states. It will thus be possible, in another embodiment, to code the useful bits equal to '1' by falling edges and the useful bits equal to '0' by rising edges.

0048In the absence of transmission or between the data, one remains in an inactive state, during which there is no transition.

0049We now present, in relation to the organization chart of the <b><u>figure 2</u></b>, a particular embodiment of the method according to the invention.

0050The decoder is firstly initialized in a normal operating mode (step 21). Then, the decoder automatically detects the length L in useful bits of the current frame and performs the decoding of all of this current frame (step 22). If the detected length L takes a first value (for example 16, corresponding to a “conventional DALI frame”, that is to say in accordance with the DALI protocol) (first output case of step 23), the decoder maintains its normal operating mode for processing one or more subsequent frames (step 24). If the detected length L takes a second value (for example 17, corresponding to a “modified DALI frame”, not provided for in the DALI protocol as specified today) (second output case from step 23), the decoder switches from normal operating mode to test mode for processing one or more subsequent frames (step 25).

0051Thus, through this example, the invention makes it possible to extend the current DALI protocol by introducing the use of a second type of frame, comprising 17 useful bits instead of 16. This allows the DALI bus to transmit specific information different from a standard DALI transmission, such as specific test data. If a transmitted frame comprises 16 useful bits, then the decoder will detect a standard DALI frame, and treat it as it is. On the other hand, if a transmitted frame comprises 17 useful bits, the first 16 useful bits will be treated as standard information and the 17^th bit will make it possible to indicate to the decoder that the following frames will not be standard DALI frames but test frames. These test frames can thus be processed accordingly.

0052We present more precisely, in relation to the <b><u>figure 3</u></b>, the block diagram of the decoder 14 already discussed above in relation to FIG. 1.

0053In a preferred embodiment, this decoder 14 is composed of:<ul id="ul0005" list-style="dash" compact="compact"><li>a counter 31, which can be incremented or decremented;</li><li>a register 32 used to store the value of the counter 31 at a given instant (thereafter, the value of the register is denoted “N” and the value of the counter is denoted “K” or “cnt”);</li><li>a comparator 33 comparing the value of the counter 31 to zero, called comparator to zero;</li><li>two other comparators called first comparator 34 and second comparator 35;</li><li>a “Logic and State Machine” block 36;</li><li>a digital filter 37; and</li><li>a parallelizer 38.</li></ul>

0054In general, the width of the counter 31 and that of the register 32 are given by the ratio between the "baud rate" of the data signal and the value of the local clock. For example, with a data at 1200 baud and a local clock at 1MHz, the counting capacity must be greater than<maths id="math0001" num=""><math display="inline"><mrow><mfrac><mrow><msup><mrow><mtext>10</mtext></mrow><mrow><mtext>6</mtext></mrow></msup><mtext></mtext></mrow><mrow><mtext>2400</mtext></mrow></mfrac></mrow></math><img file="EP1533907A1_D0001.tif" /></maths> , or 416, which defines a 9-bit counter. To make it possible to absorb the tolerances on the data and on the local clock (± 10% for example) and to set up the detection of frame errors, the use of a counter of at least 10 bits is recommended .

0055The digital filter 37 at the input of the assembly aims to improve the decoding by allowing the rejection of the parasites, thus avoiding the decoder 14 from confusing a parasite with a transition. For this, one can take into account several successive signal samples, for example three. Depending on the level of these three successive samples, we can decide whether they correspond to a transition (rising edge or falling edge) or to a parasite.

0056The parallelizer 38 makes it possible to reconstruct the decoded data signal 13 DATA, consisting of the data decoded in parallel over a width <i>not</i> bits where the number <i>not</i> depends on the application.

0057For the sake of simplification only, the description follows in the case where the decoder receives frames each comprising a start bit, 16 or 17 useful bits and one or two stop bits. In other words, in this example, the decoder receives two types of frames: "classic DALI frames" (16 useful bits) and "modified DALI frames" (17 useful bits).

0058The choice of the number of stop bits included in a given frame is made for example as a function of the transfer rate, that is to say the speed of processing of the frame with respect to the time of the stop bit (s).

0059It is clear, however, that the invention can be implemented with other frame structures. In general, the decoder according to the invention is capable of processing frames having a length L in useful bits which is variable from one frame to another and such that: L_min≤ L ≤ L_max, With l_max = (L_min + k), where k is a predetermined integer greater than or equal to 1.

0060The two phases of processing a frame by the decoder are presented successively in the normal operating mode (see discussion above). In the first phase, the decoder processes the start bit and the first 16 useful bits. In the second phase, the decoder processes the following bits (possibly 17^th useful bit, and stop bit (s)).

Processing the start bit and the first 16 useful bits

0061During the inactive state which precedes the start bit, the counter 31 is kept at the value zero. The zero comparator 33 comparing the output of the counter 31 to the zero value is therefore in the 'true' position, and this information is transmitted to the "Logic and State Machine" block 36. Nothing happens: the transmission line is in an inactive state. In this position, the counter 31 is at zero, under the action of a reset command 313 (called “clear”).

0062During the first falling edge (start of the start bit), the counter 31 receives a command 311 (called “up”) from the “Logic and State Machine” block 36, launching an incrementation of the counter until the detection of a new transition in the data signal (coding the start bit). The current value K of the counter 31 is then stored in the register 32 (the value N of the register is equal to K). When it detects this transition, the “Logic and State Machine” block 36 sends a decrement command 312 (called “down”), so that the counter 31 starts again in the other direction.

0063When the zero comparator 33 detects that the counter 31 has reached the value zero, the latter starts again in the upward direction, under the action for example of the logic defined in the block "Logic and State Machine" 36. At the next transition (coding the first useful bit), the new value of the counter 31 is stored in the register 32 and the counter 31 is again decremented to zero.

0064This is repeated for each of the following useful bits, up to the sixteenth. We can then assimilate the count value at the output of the counter to a sawtooth signal, the peaks of each of the teeth corresponding to the transitions in the data signal. It is from these transitions that we will recover the decoding clock and the decoded data.

0065In this preferred embodiment described, the circuit also includes two other comparators 34 and 35 making it possible to improve the decoding performance.

0066The first comparator 34 makes it possible to compare the value K of the counter 31 with the value N of the register 32 divided by two (K> N / 2?). When the value K of the counter 31 is greater than N / 2, a detection window is created, authorizing the transition detection in this window. Such a window covers about 50% of a binary time and is centered on the transition. This first comparator 34 therefore improves the robustness of the system since it reduces the probability of false detection and prohibits detection on the inter-bit edges when the consecutive bits are of the same value.

0067The second comparator 35 makes it possible to compare the value K of the counter 31 with the value N of the register 32 multiplied by two (K> 2 * N?). This comparison makes it possible to detect if transitions are still received, and therefore if the transmission is not interrupted. The robustness of the decoder is therefore further improved.

0068Finally, in this described embodiment, the “Logic and State Machine” block 36 will make it possible to recover two signals, a decoding clock signal 361 and an intermediate decoded data signal 362, called S_Clock and S_Data on the block diagram.

0069This “Logic and State Machine” block 36 intervenes at different stages during decoding: its role is to detect changes in edges on the two-phase asynchronous data signal to be decoded, to count the number of bits received according to the application and manage the counter 31 and the register 32 taking into account the output of the three comparators 33, 34 and 35.

Processing of the following bits (possible 17

<u>th</u>

useful bit, and stop bit (s))

0070The processing of the following bits corresponds to the step of automatic detection of the length of a frame (referenced 22 on the flow diagram of FIG. 2).

0071We now present a particular embodiment, in relation to the state machine of the <b><u>figure 4</u></b>.

0072In the "X" state, the decoder detects the 16^th useful bit (end of the first processing phase described above) then goes into state "A".

0073In state "A", the decoder increments the counter 31 (cnt = cnt + 1). When the value cnt of the counter 31 becomes greater than N / 2, we pass into the state "B" where a detection window is open and the incrementation of the counter continues.

0074It will be recalled that N is equal to the maximum value of the counter, at the instant when the transition coding the 16th useful bit has been detected. In an alternative embodiment of the invention, N is replaced by a predetermined maximum value as a function of a transmission frequency and a transfer rate of the data signal.

0075From state "B", if a transition is detected in the received signal (on input RxD) before the counter has reached the maximum value N, we pass to state "D", in which the bit following 16^th useful bit is treated and sampled as a 17^th useful bit. Furthermore, we start decrementing the counter.

0076From state "D", when the value cnt of counter 31 becomes less than N / 2, we pass into state "F" where the detection window is closed and the decrementation of the counter continues.

0077From state "B", if no transition is detected in the received signal before the counter reaches the maximum value N, we pass to state "C", in which we start the decrementation of the counter and we continue to wait for a possible transition.

0078From state "C", if a transition is detected in the signal received before the counter has reached the value N / 2, we pass to state "D" already discussed above.

0079From state "C", if the value cnt of counter 31 becomes lower than N / 2 without no transition being detected in the received signal, we pass into state "E" where the bit following the 16th^th useful bit is treated and sampled as a stop bit. Then, one passes to the state “F” already discussed above (closing of the detection window and continuation of the decrementation of the counter).

0080From state "F", we go to state "G" for processing the first or second stop bit, depending on whether the bit following the 16^th useful bit is treated and sampled as a 17^th useful bit (see state "D") or a stop bit (see state "E").

0081The <b><u>figure 7</u></b> presents in detail an example of detection of a 17^th useful bit. The signal received on the RxD input (top line), the cnt value of the counter (middle line), and the successive states of the state machine (bottom line) are shown. In this example, a transition is detected while the value of the counter is between N and N / 2. The 17th^th useful bit is taken into account here before the counter goes down to N / 2. The successive states are therefore: "A", "B", "C", "D" and "F".

0082The <b><u>figure 8</u></b> presents in detail the detection of a first and a second stop bit. Again, the signal received on the input RxD (top line), the value cnt of the counter (middle line), and the successive states of the state machine (bottom line) are shown. In this example, no transition is detected during the bit nature detection window following the 16^th useful bit (i.e. neither during the upward phase of the counter, from N / 2 to N, nor during the downward phase, from N to N / 2). The first stop bit is taken into account here when the counter reaches N / 2. The successive states are therefore: "A", "B", "C", "E" and "F". The detection of the second stop bit is performed in the same way as that of the first stop bit.

0083Figures 5 and 6 make it easier to view the operation of the decoder 14, each presenting a timing diagram of the various input / output signals and of the intermediate signals at the decoder (see Figure 3). The<b><u>figure 5</u></b> corresponds to the case of a frame comprising 17 useful bits and two stop bits. The<b>figure <u>6</u></b> corresponds to the case of a frame comprising 16 useful bits and a stop bit.

0084On the first line 51, 61, there is shown the clock signal used to carry out the coding ("tclkmanchester"), and which one seeks to reconstruct in the decoder.

0085On the second line 52, 62, the signal received on the input of the decoder (“RxD”) is shown.

0086On the third line 53, 63, the current value of the counter (“cnt”) is shown.

0087On the fourth line 54, 64, the progress parameter of the Manchester reception state machine (“msize”) is shown.

0088On the fifth line 55, 65, the number of data received ("data_count") is represented.

0089On the sixth line 56, 66, there is shown a signal representing the detection windows ("Detect Window").

0090On the seventh line 57, 67, the reconstructed clock ("clk_out") is shown.