EP1522176A1

A multi-chassis broadcast router having a common clock

Abstract

This record has no abstract on file.

Term

Term ended

Projected expiry passed 17 June 2023, 3.3 years ago.

  1. Priority
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  3. Published
  4. Projected expiry
  5. Today

11 claims: 2 independent, 9 dependent

  1. 1
    Claims of equivalent WO 2004002089 A1 CLAIMS 1. A multi-chassis broadcast router ( 100), comprising:a first chassis (102c) in which a first routing engine (140) and at least one clock- demanding component (136-1 through 136-N, 138-1 through 138-M) reside;a second chassis (104c) in which a second routing engine and at least one clock- demanding component (142-1 through 142-N, 144-1 through 144-M) reside;a first link (1 10) coupling an input side of said first routing engine (140) residing in said first chassis (102c) and an input side of said second routing engine residing in said second chassis (104c);and a master clock (134) residing in said first chassis (102c), said master clock (134) coupled to said at least one clock-demanding component (136-1 through 136-N, 138-1 through 138-M) residing in said first chassis (102c) and to said at least one clock-demanding component (142-1 through 142-N, 144-1 through 144-M) residing in said second chassis (104c) via said first link (1 10),- said master clock (134) supplying said at least one clock- demanding component (136-1 through 136-N, 138-1 through 138-M) residing in said first chassis (102c) and said at least one clock-demanding component (142-1 through 142-N, 144-1 through 144-M) residing in said second chassis (104c) with a common clock signal.
  2. 7
    A multi-chassis broadcast router (100), comprising:a first chassis (102c), said first chassis (102c) supportably mounting a first router matrix card (102a), a redundant router matrix card (102b), at least one clock-demanding input card (136-1 through 136-N) and at least one clock-demanding output card (138-1 through 138- M);a second chassis (104c), said first chassis (104c) supportably mounting a first router matrix card (104a), a redundant router matrix card (104b), at least one clock-demanding input card (142-1 through 142-N) and at least one clock-demanding output card (144-1 through 144- M);a first master clock (134) residing on said first router matrix card (102a) supportably mounted within said first chassis (102c), said first master clock (134) coupled to said at least one clock-demanding input card (136-1 through 136-N) and said at least one clock-demanding output card (138-1 through 138-M) supportably mounted by said first chassis (102c) and to said at least one clock-demanding input card (142-1 through 142-N) and said at least one clock-demanding output card (144-1 through 144-M) supportably mounted by said second chassis (104c), said first master clock (134) supplying said at least one clock-demanding input card (136-1 through 136-N) and said at least one clock-demanding output card (138-1 through 138-M) supportably mounted by said first chassis (102c) and said at least one clock- demanding input card (142-1 through 142-N) and said at least one clock-demanding output card (144-1 through 144-M) supportably mounted by said second chassis (104c) with a common clock signal;a second master clock (154) residing on said redundant router matrix card (104b) supportably mounted within said second chassis (104c), said second master clock (154) coupled to said at least one clock-demanding input card (136-1 through 136-N) and said at least one clock-demanding output card (138-1 through 138-M) supportably mounted by said first chassis (102c) and to said at least one clock-demanding input card (142-1 through 142-N) and said at least one clock-demanding output card (144-1 through 144-M) supportably mounted by said second chassis (104c), said second master clock (154) supplying said at least one clock-demanding input card (136-1 through 136-N) and said at least one clock-demanding output card (138-1 through 138-M) supportably mounted by said first chassis (102c) and said at least one clock-demanding input card (142-1 through 142-N) and said at least one clock- demanding output card (144-1 through 144-M) supportably mounted by said second chassis (104c) with a redundant common clock signal;and control logic (148, 156) coupled to said first master clock (134) and said second master clock (154), said control logic (148, 156) determining whether said first master clock (134) should issue said common clock signal or whether said second master clock (154) should issue said redundant common clock signal.