Method for shaping a periphal edge of a wafer

0001The invention relates to a process for forming a Edge area of ​​a wafer.

0002In the modern semiconductor technology, in particular for power semiconductor components, such as power MOSFETs, IGBTs, Thyristors and the like, the tendency is towards a Reduction of wafer thickness, thereby the on R_{DS, ON} to reduce the semiconductor device and to so that the conduction and switching losses of the semiconductor device to optimize. Today's semiconductor wafers are therefore before or during the manufacture of the power semiconductor components ground thin, typically of a thickness 140μm and less.

0003Such thin wafers are, however, due to their reduced Thickness compared to your diameter and due their mechanical properties very difficult to handle. In particular, very thin polished or etched wafer tend to fluttering edges and edge chipping. particularly serious this effect in ultra thin wafers in the area of about 70 microns. This issue was subsequently on the basis of Partial sections (a) and (b) shown in Figure 1:

0004Figure 1 (a) shows a wafer 1 on the surface 2 a Number of layers 6 are applied. The wafer 1 is mounted on a slide 8 on a Chuck. 9 The on the Surface 2 coated layers 6, however, cover the Wafers not 1 completely, rather, the wafer 1 in the edge region 7 uncovered. These uncovered edge regions 7 are to avoid production problems also required.

0005For this purpose, the wafer 1 a bead removal on, ie, has on the wafer edge in the immediate edge region 7 the wafer 1 not resist on. "EBR" or often also "Edge Exclusion" called is in semiconductor technology common term and defines the unusable Area at the edge of a wafer by non-uniformities the force applied to the wafer layers or through the paint removal itself comes about. This Randendlackung is required, thus the space required for the structuring Photoresist does not reach the back of the wafer 3. 1 Would the wafer 1 in such a case on a hot slices (Hot-plate) are placed for baking the photoresist, can stick the wafer there and replaced only with great effort again will. To avoid this, takes the wafer backside be cleaned after each Belackungsprozess, which at a Plurality of patterning steps very complicated and therefore would be very costly. Moreover, there is in principle the problem of contamination from below on the same hot plate to be processed wafers.

0006Due to the necessity of the surface is Randendlackung 2 of the wafer 1 in the Randendlackung necessarily also uncovered. The requirement, however, that the wafer 1 must be uncovered in an edge region 7, but leads straight with very thick layers 6 to the fact that one of each additionally applied layer 6 taller stage 22 on Edge 7 of the wafer 1 results. This problem is particularly serious with power semiconductor components, in which the deposited semiconductor layers, in particular for isolating serving field oxide and the metallization, especially are formed thick. For example, this level 22 in the edge region with a standard IGBT used today or MOS process a thickness D5 of more than 10 microns and a abhängende of the specified edge bead removal width of at least 1 mm. This edge region 7 of the wafer 1 depends so to speak, on the applied layers 6 over. In a standard thickness having wafer has this overhangs little effect on the stability of the wafer Edge region 7. However, the wafer 1 is thinned, then begins the overhanging portion of the wafer 1, which due to the very high level 22 inadequately supported by the adhesive sheet 8 is, "fluttering" in the grinding of the wafer 1 to. One speaks here of a jagged edge, which in Figure 1 (b) by reference numeral 20 is indicated. In the further processing of such thin wafer 1 'this can border or edge chipping 21 lead, which often has a wafer failure.

0007The problem of edge chipping is far evaded by that the wafer only to such a thickness ground thin are, at the edge outbreaks or flutter Border areas is avoided. On the other hand is also a suitable conversion of semiconductor processes prevents the mechanically unstable border areas of the ground-thin Wafers an excessive mechanical load to the edge chipping would lead, learn.

0008That does speak that although the problem of fluttering Wafer edges or edge outbreaks by appropriate Choice of semiconductor process technology can be bypassed, However, this problem has not been completely eliminated and thus still not been resolved.

0009The present invention is therefore based on the object, fluttering edges or edge chipping during or after Thinning of a wafer to be largely avoided.

0010According to the invention, this object is by a method comprising the features of patent claim 1. Accordingly, a A method for shaping an edge portion of a wafer provided, comprising the following method steps:<sl><li>(A) A wafer having a first and a second surface will be provided; </li><li>(B) an inner area of ​​the first surface applied at least one layer, so that at least a part of an edge region on the first surface remains uncovered by the at least one layer;</li><li>(C) The edge of the wafer is ablated until all edge regions on the first surface of the at least one layer are covered;</li><li>(D) The wafer is from the second surface thereof to a predetermined thickness ground thin.</li></sl>

0011The idea of ​​the present invention is based is is that by grinding the wafer edge the overhanging Edge area of ​​the wafer for the subsequent thinning process is completely removed. This makes it possible, Wafer despite the necessary edge bead removal at very low grind thicknesses of less than 140 microns thin, without the risk of outbreaks edge is. This reduces wafer failures and increases the efficiency significantly.

0012With the shaping of the edge of the wafer according to the invention is also a reduction in the effective wafer surface accompanied. However, since the area of ​​the edge bead and thus, the area of ​​the shaping Edge to be ablated, anyway no semiconductor devices having and not technical reasons anyway is available, the grinding of the rim does not lead to a reduction in the usable on a wafer semiconductor devices, so that the yield remains unchanged.

0013it is a further advantage of the process according to the invention therein, usually for the further processing of thin wafers Semiconductor processes used and the corresponding To use production machines. These processes and machines are not necessarily specifically on a gentle, mechanically the surface not very be optimized beanspruchende treatment. Thus arises an additional degree of freedom in the choice of the appropriate Manufacturing processes.

0014The removal takes place or abrasion of the edge of the wafer advantageously by means of a grindstone, the z. B. as and grinding wheel may be formed around the edge of the wafer is formed circumferentially. The grinding device may, however, also be designed differently, for. example, as a grinding wheel or Belt sander. The grinding wheel has a directed towards the wafer center Feed on. This ensures that the Grinding constantly contact with the outside surface of the wafer edge has this and thus can be paid off.

0015The wafer edge is today typically mechanically with a Grindstone various forms depending on wafer thickness having so processed, the result is a rounded edge. This process is fully automated advantageously. At the can ablating either the grinder to the wafer turn around or drive along the wafer or wafer can rotate with the grinder stationary is executed.

0016In a very advantageous embodiment, the grinding wheel an at least partially concave, after that curved outwards on abrasive surface. This ensures that the outer surfaces of the wafer edge and the Wafer surface after the removal of the covering layers rounded edge and formed approximately convex.

0017Advantageously, the edge area of ​​the wafer as well as the layer applied thereon according to the abrading or stripping a continuous outer surface, so that a step-shaped, discontinuous outer surface between the wafer and the layers applied thereon is avoided.

0018Additionally or alternatively the rim may ablation with the aid of a laser with high laser power and / or with the aid of a focused jet of water performed with high water jet speed. alternative can the edge ablation also Polierfilzmittel with ablative Property can be used. As Polierfilzmittel For example, a polishing felt or abrasive polishing be provided. The edge ablation means or Lasers- focusiertem waterjet are alternative ways to the grinding, the particular offer when For example, the grinding is not with the grinding stone works more. This may for example happen if materials available in the abraded layers are the glue or dull the stone. Here, advantageously contactless method with laser or be high pressure water jet more convenient and effective.

0019Before thinning by grinding the wafer is typically a Chuck hung and fixed, for example by means of vacuum. It is particularly advantageous, however, if instead of using a vacuum chuck typically used an electrostatic acting chuck is used. In this case, could also be an adhesive or protective film between wafers and Chuck are omitted. An electrostatic chuck is a Chuck which holds a wafer by means of charges. The main field of application Such electrostatic chucks is wafer production in the area of ​​the wafer holding in a vacuum, because there is just no suction of the wafer and with possible the hitherto customary Clamps always very high defect densities were possible. With the contactless holding a Wafer by charges in an electrostatic chuck is for a reduction of the defect density achievable and on the other hand a larger area use the wafer possible since the clamping devices uniformity of the Wafer surface does not bother.

0020The inventive method is especially advantageous in the manufacture of so-called thin wafers, in particular because with thin wafers, the problem of edge flutter or the edge terminations is particularly serious. Under a thin Wafer is a wafer having a thickness less than 140 microns, advantageously of less than 70 microns to understand. The invention The method is thus suitable in particular for so-called unstabilized wafer. Among unstabilized wafers to understand such wafer in which, because of the relationship of wafer thickness to diameter wafer planarity of Surface or the required rigidity of the wafer is no longer guaranteed. Unstabilized wafers is typically the problem of borders and border outbreaks fluttering inherent. The particular advantage of the present Invention is that also such unstabilized thin wafers without significant restriction or redesign the manufacturing technology by conventional methods and arrangements can be further processed. nevertheless it must be said that the inventive method of course, in conventional, ie not thin polished wafers, can be used advantageously.

0021Further advantageous embodiments and developments of the Invention are in the sub-reflection as well as the description removed with reference to the drawing.

0022The invention is described with reference to the figures of the Drawing specified embodiments explained in more detail. It shows:<dl tsize="7"><dt>figure 1</dt><dd>with reference to two schematic partial sections (a) and (B) a previously used method for thinning a wafer;</dd><dt>figure 2</dt><dd>based on schematic partial sections (a) - (g) The inventive method for thinning a wafer.</dd></dl>

0023are in all figures of the drawing identical or functionally identical Elements - unless otherwise indicated - with like reference numerals have been provided.

0024Figure 2 shows in sub-sections schematically the inventive Procedure for thinning a wafer. The subsequent numbering correspond to the respective Parts of Figure 2:<sl><li>(A) A designated with reference number 1 wafer, for example, made of silicon, is provided. The wafer 1 has a first surface 2, the so-called wafer front side, and a second surface 3, the so-called Wafer backside, on.</li><li>(B) The wafer 1 is processed semiconductor technology, ie it will be in the inner region 4, for the corresponding Semiconductor devices provided structures Semiconductor body produced (not shown in Figure 2 (b)). In an edge area 5 of the wafer 1 has typically no semiconductor components. additionally be in the inner area 4 one or more layers 6 applied to the first surface of the second In the present Case were a total of five layers 6, which by itself various graphs differ, shown. These layers 6, for example, of doped or undoped polysilicon, a dielectric such as silicon dioxide (SiO₂) or silicon nitride (Si₃N₄), An electrically conductive Layer, such as a metal, a metal silicide, a metal alloy, or the like, exist. The 6 layers can by sputtering, by deposition or in the case of thermal silicon dioxide by growing in an atmosphere containing oxygen at a high temperature be generated. The layers 6 can vary depending on the technology used overlap more or less over the edge region fifth by virtue of the problems described at the outset, that the Necessity of using an edge bead removal, at least a part of the edge region 5 of the not 6 layers covered. This uncovered edge region indicated in Figure 2 (b) with reference numerals. 7</li><li>(C) In the wafer back surface 3 of the wafer 1, an adhesive layer 8, for example, a double-sided adhesive film, an adhesive tape or an adhesive applied. The wafer assembly 10 consisting of wafer 1, layers 6 and adhesive layer 8 Then, with the adhesive layer 8 on a Support device 9, for example, a vacuum chuck 9, placed. The back 3 of the wafer 1 is then sucked by the vacuum chuck 9, whereby the entire wafer assembly 10 is fixed.</li><li>(D) By means of a circulating around the edge region 5 of the wafer 1 Grinding wheel 11 of the edge is ground. In order to the grinding wheel 11 undisturbed edit the edge region 5 can, it is - as shown in Figure 2 (d) - an advantage that the chuck 9 having a smaller diameter than the wafer 1 has. By the grinding of the edge area 5, the uncovered edge region 7 of the wafer 1 removed. The grinding process is about speed and feed of Grinding wheel 11 and on the grit of abrasive Surface 13 of the grinding wheel 11 set so that the uncovered edge regions 7 completely removed will. The result is therefore a continuous transition from the outer surface 12 at the edge 5 of the wafer 1 to the outer surface 14 of 6. An undesirable level layers between the layers 6 and the wafer front side 2 is thus avoided. In the present case, the grinding wheel 11 according to a outwardly curved abrasive surface. 13 This in about concave grinding surface 13 engages the Outer surfaces 12, 14 and thus leads to roughly convex, rounded outer surfaces 12, 14 To such ensure continuous transition of the outer surfaces 12, 14, it is necessary that even a slight Part of the layer 6 is removed with.</li><li>(E) The wafer assembly 10 is withdrawn from the chuck. 9 subsequently the adhesive layer 8 of the wafer backside replaced.</li><li>(F) On the side of the wafer front side 2, another Adhesive layer 15 applied to the layer. 6 The wafer assembly 10 is then onto a vacuum chuck 16, the not necessarily smaller in diameter than the wafer must have 1, down and sucked in by this. Subsequently, the wafer 1 from the wafer backside is 3 ago thinned. The thinning of the wafer 1 can for example by grinding, etching or the like done. When thinning the thickness of the wafer 1, the originally a thickness D1 in the range 500-800 microns has reduced to a smaller thickness D2 &lt;D1. It A thin wafer 1 '. After thinning, the thin wafers 1 'through the layer 6 and the adhesive layer 15 supported. Because of the thin wafer 1 'No naked Edge regions 7 has more, will flutter at the edge 5 and edge chipping largely avoided.</li><li>(G) Finally, the thin wafer 1 'again from Chuck 16 incurred and the adhesive Chic ht be detached 15th The thin wafer 1 'can now be further processed.</li></sl>

0025By shaping the rim 5 is a reduction the wafer diameter D3 associated, but this is irrelevant for arranged in the wafers 1 Semiconductor Components, because the removal at the edge compared to the wafer diameter D3 is negligible. The worn rim 5 Range is typically in the range of about 1-2 mm, which in today's popular wafer diameters D3 of 150, 200 or 300 mm is of no consequence on.

0026The accompanying the edging or edge shaping Reducing the wafer diameter D4 can be used for the subsequent Process steps, such as implantation, vapor deposition, sputtering, Annealing, etc. by suitable modification of the corresponding Manufacturing plants are compensated. There can sometimes necessary, the supports in this Manufacturing facilities, which serve to receive the wafer so interpreted, that they for wafers with slightly smaller diameters D4 are also designed.

0027In summary it can be stated that by a slight Removal of the edge of a wafer in this subsequent thinning in a very simple, but nevertheless despite very effectively before fluttering wafer edges and Border outbreaks can be prevented.

0028The present invention has embodiments using the above as shown, the principle of the invention and its practical application in the best possible explain However, the invention can of course at appropriate modification in diverse other embodiments realize.

LIST OF REFERENCE NUMBERS

0029<dl tsize="2" compact="compact"><dt>1</dt><dd>wafer</dd><dt>1'</dt><dd>thin wafers</dd><dt>2</dt><dd>first surface wafer front side</dd><dt>3</dt><dd>second surface, wafer backside</dd><dt>4</dt><dd>inner portion of the wafer</dd><dt>5</dt><dd>Border area / edge of the wafer</dd><dt>6</dt><dd>layers</dd><dt>7</dt><dd>not covered edge region</dd><dt>8th</dt><dd>Adhesive layer, adhesive film</dd><dt>9</dt><dd>(Vacuum) Chuck</dd><dt>10</dt><dd>wafer assembly</dd><dt>11</dt><dd>grinding wheel</dd><dt>12</dt><dd>Outer surface at the edge of the wafer</dd><dt>13</dt><dd>abrasive surface of the grinding wheel</dd><dt>14</dt><dd>Outer surface of the layer</dd><dt>15</dt><dd>Adhesive layer, adhesive film</dd><dt>16</dt><dd>(Vacuum) Chuck</dd><dt>20</dt><dd>Edge flutter of the wafer</dd><dt>21</dt><dd>Edge / edge chipping</dd><dt>22</dt><dd>step</dd></dl><dl tsize="6" compact="compact"><dt>D1, D2</dt><dd>Thickness of the wafer</dd><dt>D3, D4</dt><dd>Diameter of the wafer</dd><dt>D5</dt><dd>Thickness of the layer</dd></dl>