Process for the manufacture of a wiring for contact holes

p0001The present invention relates to a method for producing a wiring for contact holes and more particularly to a method for the simple and inexpensive production of a wiring with contact holes, which are free of spurious cavities.

p0002With the increasing complexity of integrated circuits as well as the increasing integration density on the one hand increases the number of respective wiring or metallization levels of an integrated circuit, on the other hand decreases a feature size of contact holes for contacting the respective wiring layers. The contact holes are in this case of an electrical connection between the different wiring layers, or a substrate plane, are formed on the respective electrical circuits. A filling of this contact holes or vias without generation of voids as well as the simple structure of the subsequent wiring level is in the manufacture of a wiring of an integrated circuit or a chip is a key problem.

p0003For example, it comes at a metal deposition upper metallization layers (second, third etc. level) often results in an accumulation of material on the upper edges of the contact hole or vias, which up to the blocking of a deposition in the lower region of the contact hole and hence to the formation of so-called voids can lead or cavities. This problem increases with increasing integration density or reducing the diameter of the contact holes and a tendency towards increasingly steeper sidewalls of the contact holes in future reduction processes or called Shrinks.

p0004To produce such finely textured vias with high aspect ratios in multiple wiring planes usually four manufacturing methods described below are applied.

p0005In a so-called W-CVD tungsten using a chemical vapor deposition (chemical vapor deposition, CVD) is formed in the contact holes, whereby this process is characterized by good filling properties, even at very small dimensions. However, such tungsten vias bring a variety of drawbacks, which speak against an application for easy and cost-effective production of a wiring for contact holes. A hand, during the manufacture of the risk of etching attack of a semiconductor substrate used by the used WF₆, Furthermore, tungsten has poor adhesion or adhesion to SiO₂ thereby providing possible contact problems. Above all, however, be caused by material heterogeneity between tungsten contact holes and the respective metallization layers of different wiring planes which are preferably made from Al-alloys material flow divergence. This material flow divergences lead to preferred formation of voids (void formation) at the interface between the tungsten contact holes and the respective metallization due to electrical and stress migration, which results in a reduction of service life of the entire chip. Furthermore, argues against the use of tungsten vias just in future Shrinks opposite the metallization or wiring levels relatively high contact resistance.

p0006Alternatively to the above-described tungsten deposition, there is the possibility of chemical vapor deposition of an aluminum metallization (Al-CVD deposition). However, Al-CVD method could not free himself because of their low deposition rate for the mass production of semiconductor integrated circuits or chips. Furthermore, the high temperatures of ≥ 500 ° C during the deposition to very large grains and associated difficulties in the subsequent patterning lead. Also by this Al-CVD method, an alloy such as AL0.5% Cu in the required quality can not be manufactured. Such a method can not be applied, therefore, for the simple and inexpensive production of a wiring.

p0007A further possibility, contact holes or vias to produce without voids, provides the so-called Al-PVD sputtering (physical vapor deposition, PVD) at high temperatures ≥ 500 degrees Celsius. A modification of this physical vapor deposition process is to first cold deposition for nucleation of Al-germination and subsequent temperature increase during sputtering. In this way, a good filling performance can indeed achieve, with an improved reliability is achieved compared to the tungsten contact holes. However, the underlying metallization and wiring planes by thermo-mechanical stress (stress) are damaged by the high temperatures in the deposition of ≥ 500 degrees Celsius. Furthermore, very thick adhesive layers of Ti necessary for filling gaps and voids by Al diffusion. This, together with the high temperature budget to form a pronounced TiAl₃Layer, thereby taking advantage of the lower resistance to the tungsten contact holes is nullified.

p0008A further possibility of manufacturing a wiring for contact holes are so-called "reflow". In these methods according to the conventional sputtering, a heat treatment at high temperature of preferably ≥ 500 degrees Celsius is carried out, in which a filler material can flow in previously filled vias and their cavities (reflow). This process is particularly effective for mass production because of its low cost and simplicity. However, a disadvantage with this method also, as in the above-described method, the damage to the underlying metallization and wiring planes by the high process or reflow temperature and the additional formation of a TiAl₃Layer before patterning with her unnecessarily high resistance. An alternative to this offer so-called "laser reflow process", in which the subsequent heat treatment of the metallization or wiring levels locally controlled with a laser beam is carried out. One drawback of lower metal layers is indeed reduced by a low-cost mass production is, however, not possible.

p0009Furthermore, a method is known eg from the document US 5,789,317 known is deposited in the preparation of a wiring for contact holes using a Sputterabscheideverfahrens AlGeCu using hydrogen (H) in the contact holes, thereby significantly reducing the flow properties and the risk of resulting cavities can , By the use of hydrogen in this case the metal bonds are loosened and achieves an improved flow behavior. Due to the greatly enlarged in this process roughness of the metal layer, however, must be carried out and a subsequent wiring layer can be applied over the whole area, which can be structured simply and finely in a subsequent step, first a chemical-mechanical polishing (CMP). These additional steps involve additional expenditure, not least in cost and time, which in addition has the risk of deteriorating contact.

p0010The invention is therefore based on the object to provide a method for producing a wiring of contact holes with small size, which allows easy and inexpensive reliable contact between different wiring layers.

p0011This object is achieved by the measures of claim 1.

p0012In particular, by forming a AlGeCu containing the second wiring layer to fill the contact holes by means of a PVD process and the direct patterning the second wiring layer by means of an anisotropic etching method, contact holes can be formed at low temperatures without voids, whereby there is no deterioration of deeper wiring levels or metallization layers. A forming the intermetallic phase TiAl₃ with their difficulties in patterning is minimized by the trained AlGeCu layer has sufficiently small particle sizes that they can be patterned directly by means of an anisotropic etching method. The commonly known CMP step (chemical mechanical polishing) can thus be dispensed with, whereby the method further simplified.

p0013Preferably, the second wiring layer is in a single-stage formed by depositing a layer AlGeCu at substrate temperatures of> 100 degrees Celsius. Usually, the substrate temperatures but below 420 degrees Celsius, and thus well below the so-called reflow temperature of> 500 degrees Celsius. In this way, the second wiring layer can be relatively quickly deposited in the contact holes without forming cavities.

p0014Further, the second wiring layer may be deposited in a two stage process by depositing a first AlGeCu layer at low temperatures and a second AlGeCu layer at high substrate temperatures, which can be improved in the contact holes further filling properties.

p0015Alternatively can be formed 100 degrees Celsius in a two stage process, the second wiring layer by depositing an AlCu layer at low substrate temperatures <at higher substrate temperatures 100 degrees Celsius and a AlGeCu layer>. This improved filling properties and contact resistances are obtained with shorter deposition times.

p0016In another alternative, the second wiring layer can be formed in a three-stage process by depositing a first AlCu layer, a AlGeCu layer and a second AlCu layer, thereby obtaining improved with continued optimum flow characteristics contact resistance and optimal structuring.

p0017Preferably, a Ti adhesion layer for the barrier layer is used, the thickness can be further reduced due to the improved flow properties and thus in turn allows for smaller feature sizes.

p0018Preferably, a reactive ion etching is applied directly on the second wiring layer for the anisotropic etching method, thereby obtaining a particularly simple to integrate into existing manufacturing processes, the method.

p0019In the further subclaims, further advantageous embodiments of the invention are characterized.

p0020The invention will now be described by way of example with reference to the drawings.

Show it:

p0021Figures 1A to 1E show simplified sectional views illustrating respective steps of the manufacturing method according to the invention.

p0022Figures 1A to 1E show simplified sectional views of process steps for manufacturing a wiring for contact holes according to the present invention, wherein like reference numerals designate like or similar elements or layers.

p0023According to Figure 1A is on a not shown substrate, for example, where electronic circuits are integrated, a first wiring layer 1. However, the wiring layer 1 does not have to lie directly on a substrate, but may also represent an overlying intermediate wiring plane. For the isolation of a further wiring layer, an insulation layer 2 is formed above the first wiring layer 1 according to Figure 1A. To produce an electrical connection to the first wiring layer 1 in a subsequent process step finely patterned contact holes or vias 3 are formed in the insulating layer. 2 The insulating layer 2 is preferably made of silicon dioxide. However, it may be made of any other insulating material or a plurality of layers. After the formation of the contact holes 3, which is preferably carried out by an anisotropic etching process is carried out in particular for cleaning the side surfaces of a wet-chemical and / or plasma-chemical cleaning of the Waber-surface or the contact holes third

p00241B, a barrier layer 4 is formed at least on the surface of the contact holes 3 in a subsequent process step, wherein it is preferably formed over the whole area on the wafer. The barrier layer 4 preferably consists of a Ti adhesion layer, resulting in a contact resistance between the first wiring layer 1 and the subsequent contact holes formed in the wiring layer decreases. The barrier layer and adhesive layer 4 here can be made very thin, whereby very finely structured contact holes 3 can be produced with steep edges.

p00251C, in a further method step, a AlGeCu-containing second wiring layer 5 on the surface of the insulation layer 2 by means of a physical vapor deposition (PVD, physical vapor deposition) is deposited, whereby the contact holes 3 are filled without voids. The temperatures for forming these AlGeCu-containing second wiring layer 5 in this case are well below the usual reflow temperatures of> 500 degrees Celsius and preferably below 400 degrees Celsius. can be formed in the contact holes 3 In particular, due to the use of a Ge-containing AlCu target therefore at very low temperatures, a highly flowable and electrically conductive layer. The second wiring layer 5 has consequently at least a layer of the alloy Al_(1-xy)Ge_xCu_y, As a eutectic temperature of 420 degrees Celsius at 5 weight percent Ge seen from the Al-Ge phase diagram, a sufficiently flowable metallization layer, by use of this physical low-temperature procedure also at a lower Ge content can be formed in the contact holes 3 at temperatures far below the reflow temperature of> 500 degrees Celsius, and typically below 420 degrees Celsius.

p0026According to Figure 1D, an antireflection layer 6 is formed on the surface of the second wiring layer 5 in a subsequent step that allows a very precise patterning of the second wiring layer. In a subsequent step, a mask layer 7 is for example formed and patterned, preferably using photolithographic methods are used.

p0027According to Figure 1E, the second wiring layer 5 is using the mask layer 7 now directly by means of an anisotropic etching method to form a second wiring layer 5 structured ', which due to the above-described low-temperature PVD process, the grain sizes of AlGeCu containing second wiring layer are sufficiently small in order to obtain a sufficiently precise patterning. The usually required CMP process with subsequent formation of a further metallization deleted by said no with negative effects contact resistances between the metallization layer formed inside and outside the contact holes. 3

p0028Accordingly, one obtains a simple and cost-effective production method, in which a particularly reliable wiring for contact holes can be generated.

p0029Subsequently, different embodiments of forming the second wiring layer will be described.

p0030According to a first embodiment, a AlGeCu layer is formed as a second wiring layer 5 in a single stage by means of a PVD deposition at elevated substrate temperatures> 100 degrees Celsius in the contact holes 3 as well as on the surface of the insulation layer 2. FIG. Preferably, a PVD deposition is applied, in which a Ge-containing target is bombarded (with Ge-homogeneous distribution). At such temperatures, the substrate, but still well below the usual reflow temperatures of> 500 degrees Celsius, is obtained an improved flow properties of the new alloy Al_(1-xy)Ge_xCu_y, This so-called void-free filling of the contact holes is made possible and ensured adequate contact between respective metallization or wiring planes. The flowing of the material introduced can be made accordingly already during the deposition, which is particularly important with very finely patterned contact holes beneficial.

p0031Further, the relatively low temperatures are due to the underlying metallization layers are not damaged during the PVD deposition below 500 degrees Celsius by thermo-mechanical stress and formed a relatively fine grained AlGeCu layer which can be patterned directly in a subsequent anisotropic etching process, thereby a wiring can be realized quickly and easily. Usually applied CMP process can be omitted accordingly. In order to improve the contact resistance In addition, the formed on the surface of the contact holes 3 barrier layer 4, which preferably consists of Ti is used.

p0032According to a second embodiment, the second wiring layer 5 <100 degrees Celsius and a second AlGeCu layer at substrate temperatures of> 100 degrees Celsius may alternatively be formed in a two stage process by PVD sputtering a first AlGeCu layer at substrate temperatures. Since substantially the same materials and deposition methods are used as in the first embodiment, will be omitted below detailed description thereof. In turn is produced, for example, a Ge-containing AlCu target homogeneous Ge distribution, the AlGeCu layer, wherein the alloy at 5 weight percent Ge a eutectic temperature of about 420 degrees Celsius yields and thus the second wiring layer at temperatures well < 420 degrees Celsius can be formed. By using the two-step process described above, in the relatively high amount of time and at relatively low temperatures below 100 degrees Celsius, a first relatively thin AlGeCu layer is formed and a subsequent formation of a second AlGeCu layer at substrate temperatures of> 100 degrees Celsius, which can be carried out very quickly as a rule, to obtain a highly reliable wiring wherein no cavities are formed in the contact holes. turn these trained in a two stage process AlGeCu layer has a very small particle size, which is why this layer may be patterned directly to the formation of the actual wiring in a subsequent patterning step.

p0033According to a third embodiment, the second wiring layer 5 is formed in a two stage process by depositing an AlCu layer at substrate temperatures <100 degrees Celsius and a AlGeCu layer at substrate temperatures of> 100 degrees Celsius. The method for depositing the PVD layer AlGeCu meet here again the deposition described above, will be omitted below, a detailed description. To further improve a deposition in the contact holes 3 as well as on the first wiring layer 1, which is preferably made of AlCu, an AlCu layer can be formed in a so-called cold process according to this third embodiment, first. Due to the low temperatures are again obtained a relatively low deposition rate, but the quality is improved. As in the second embodiment is obtained by a further improved wiring which now consists of two different layers and can in turn be structured very well.

p0034According to a fourth embodiment, the second wiring layer 5 is formed in a three-stage process by depositing a first AlCu layer, a subsequent layer AlGeCu and a subsequent second AlCu layer. The method in particular for forming the layer AlGeCu meet here again the above-described embodiments, will be omitted below, a detailed description. In addition to the first AlCu layer, a further layer of AlCu is superimposed as the top layer of the AlGeCu layer according to this embodiment, thereby reducing the sheet resistance, the reliability of the wiring and the structuring properties improve. The individual layers can in this case be formed at various substrate temperatures, but are preferably used, first a cold process and then hotter processes at substrate temperatures below and above 100 degrees Celsius.

p0035According to a further embodiment, the second wiring layer in a multi-stage process followed by depositing at least one AlGeCu layer in the contact holes 3 of a chemical mechanical polishing (CMP) and formed by subsequent whole-area deposition of an AlCu layer on the surface of the insulation layer 2. FIG. Again, corresponding to respective deposition the deposition described above, will be omitted below a repeated description. According to this embodiment, the AlGeCu layer is only in the areas of the contact holes 3, while a remaining part of the surface over the entire surface covered with a layer of AlCu. This in turn is obtained at the contact holes 3 optimum flow and filling for producing highly reliable and void-free contacts, while the entire second wiring layer 5 has a minimum sheet resistance. In addition, a structuring by means of anisotropic etching is further improved because the insulation layer 2 formed on the AlCu layer has minimum film resistors and smaller grain sizes, thus allowing a finer patterning.

p0036For patterning the second wiring layer 5, reactive ion etching (RIE) is used as the anisotropic etching method preferably. In this way, the above described method can easily be embedded in existing methods. Furthermore, can be carried out to improve properties of the respective material in all the embodiments described above, an additional heat treatment. In order to improve the patterning of the second wiring layer 5, the antireflection layer 6 is preferably made of a TiN layer, which can reduce unwanted stray lights targeted in particular when using the photolithographic patterning process.

p0037The present invention has been described with reference to a first and second wiring layer. These first and second wiring layer is not limited to a first and second metallization plane, but rather can be applied to all wiring levels within an integrated circuit or a semiconductor device. In particular, through the use of a special low-temperature PVD sputtering process yields a layer with small grains AlGeCu and minimum precipitates, which is why this layer can be directly patterned in a subsequent patterning step. A high quality and reliable wiring can be manufactured in this way particularly simple and inexpensive.