Microprocessor system and method of operation

The invention relates to a method for operating a microprocessor arrangement having a first and a further unit, a bus over which those units are connected together with a line for a state signal and lines for other bus signals and a bus control unit for controlling accesses to the first unit on the another unit. Moreover, the invention relates to a microprocessor arrangement which is suitable for performing the method.

Microprocessor arrangements comprise in addition to the central processing and control unit (CPU) integrated additional units such as memories or peripheral units for signal input and signal output in a single chip, called a microcontroller. Such Miro controller can be used in safety-related systems, such as smart cards. The microcontroller serves, inter alia, to encrypt the traffic between a reader and the smart card to verify access permissions and perform other covert operations.

It is known that can be used for spying of the function of the microcontroller, the timing of the consumed current by the microcontroller. For example, trigger points can be obtained to control subsequent measurements at the correct time from the current profile; or it can be drawn regarding the specific type of processor used in the calculation and encryption / decryption algorithms; or it can even parts of the processed payload are determined. especially bus accesses produce a characteristic power profile, as they expire after a predetermined signal protocol and provide the switching operations due to the high for driving capacitive loads a clear power profile. The use of conventional microcontrollers in safety-critical applications is therefore problematic.

The publication "Dallas Semiconductor Corp: Section 1: Introduction, 6 October 1993, databook Soft Microcontroller" shows that in a random sequence, on the bus, a dummy cycle is inserted in place of a real cycle. A dummy cycle encompasses any real data, but only randomly generated data, to increase the privacy of the bus system. The dummy data is applied in a randomly changing sequence of dummy cycles with Real cycles of cables for the bus signals. Such a method enables the concealment or camouflage the real data with dummy data, thereby increasing the security against spying of the transmitted data, but also increases the time duration of the data transmission of a data packet over the bus system.

The object of the invention is to provide a method for operating a microprocessor arrangement which is bugged, and that is improved over the prior art.

Another object is to provide a device suitable for carrying out the method microprocessor arrangement.

According to the invention, the object is on the process achieved by a method for operating a microprocessor arrangement with a first unit and another unit; a bus over which the first unit is connected to the further unit and comprises a line for a state signal indicating the operating state of the bus, and further lines for bus signals indicating a data value; a bus control unit for controlling accesses of the first unit to the other unit via the bus; in which process, when it is notified from the bus control unit via the line for the state signal is not being accessed by the first unit is carried out in the further unit, a data value is generated randomly, and is applied to the lines for the further bus signals.

A microprocessor arrangement for carrying out the method according to the invention comprises: a first unit and a further unit; a bus over which the first unit is connected to the further unit and comprises a line for a state signal indicating the operating state of the bus, and further lines for bus signals indicating a data value; a bus control unit for controlling accesses to the first unit to the other unit via the bus; a random number generator, which is connectable to the lines for the further bus signals when the state signal indicating that no access from the first unit is to be performed on the additional unit.

The bus state indicates for which task the bus from the central processing and control unit (CPU) is used at the moment. If the bus is considered clock section just in hibernation, are on the bus data lines of the bus to no valid signals. According to the invention, then a randomly generated signal over di data lines of the bus is transmitted. Thereby, the current profile is changed randomly. The current profile is thereby disguised in relation to the power transmitted over the bus payload, so that inferences much more difficult on the payload based on a statistical evaluation of the current profile or even made impossible.

According to the bus protocol may be provided that the bus state signal indicating the state of the bus lines one clock in advance. It is also possible that the bus state signal indicating the state of the other bus in the same cycle.

The addressable by the CPU units are assigned addresses. When the CPU by means of the bus control unit outputs a memory or a peripheral unit assigned address, it means that the memory and a memory cell or the corresponding peripheral unit contained therein is to be activated to receive data from the bus or to output to the bus. In the invention, if is then followed by the CPU does not access to a device connected to the bus unit, while an address outputted to the bus. However, this address is not an address that is assigned to a unit connected to the bus, but any other address. This has the result that none of the attached devices is activated. Nevertheless, this arbitrary address is transmitted via the bus and thereby generates a corresponding current profile. This address is generated randomly. The current profile is accordingly changed randomly. It does not ensure that the random number does not match a valid address of a unit connected to the bus.

The output onto the bus data value in this way contains the importance of an address by the respective state of the bus state signal. The bus state signal indicates Furthermore, supports that either an address is outputted to the data lines of the bus or output a date to the addressed unit (written) is. For the addresses, and to be read or to be written to the same data signal lines of the bus can be used. This is called a multiplexed data / address bus. The term data is to be understood generally and includes data values ​​representing an address or date data to be processed or instructions etc.. After the bus state has indicated that a resting state, in the following cycle, a random value is transmitted. If an address is transmitted, for which there is no device connected to the bus unit, for as long random values ​​are transferred to another existing unit is addressed by a valid address in the subsequent operating cycles. In recent microprocessors presented an address that was not assigned to any unit connected, a programming error. In the invention, however, the transfer of such randomized address is to be understood that access is performed on a non-existent target to the otherwise unused bus cycles to disguise.

The bus of the microprocessor arrangement may additionally include a line for an enable signal, which is fed to the other units connected to the bus. The enable signal transmitted to those units that access via the bus. The release line is driven advantageously by a signaled by the bus state hibernation with random values.

The invention is further illustrated by the embodiment shown in the drawing. Show it:<dl id="dl0001"><dt>figure 1</dt><dd>a block diagram with relevant elements of the invention and a microprocessor</dd><dt>figure 2</dt><dd>a signal flow diagram.</dd></dl>

The in <figref idrefs="f0001">figure 1</figref> Microcontroller illustrated comprises a central control and processing unit (CPU) 1, by the internal operations, particularly the accesses are controlled on the bus. 2 For this purpose, the CPU 1 of so-called multiplexed comprises a bus control unit 11. The bus itself comprises at least a signal line 21, which indicates the bus state, and a plurality of lines 22, over which both addresses of the connected units and data values ​​are successively transmitted, data / address bus. To the bus 2, a memory 3 is connected, are stored in the data to be processed values ​​and / or instructions. Furthermore, a first peripheral unit 4 is provided and a second peripheral unit 5, exchanged over the data with off-chip connected functional units. The microcontroller is used for example in a smart card application to communicate with a reader. Each of the units connected to the bus 3, 4, 5 has a bus interface 31, 41 and 51st The bus control unit 11 and the interfaces 31, 41, 51 work together in master-slave dependency.

When the bus 2 is idle, ie none of the connected units 3, 4, 5 is activated by the CPU 1 for access, then the data lines of the Busteuereinheit running 22 issued a series of randomly generated data values. For generating the random data values, a random generator 12 which is connected via a multiplexer 13 to the data lines 22 of the bus is used. If one of the units 3, 4, 5 is addressed by the CPU 1, the multiplexer 13 switches to the other terminal 14, which forwards the data sent or received to the other functional units of the CPU first

The bus state BS, which is transmitted on the line 21, is in <figref idrefs="f0001">figure 2</figref> shown together with the transferred on the data / address lines 22 B data values. The bus is intermittently operated so that respective signal states one clock period of the clock CLK are valid. The bus state BS is the IDLE state for hibernation, the ADR condition for the transmission of an address, the state WR for a write operation in which a date from the CPU 1 to one of the units 3, 4, 5 is transmitted, and a state RD for a read operation, in which a data value from one of the units 3, 4, 5 and transferred to the CPU 1, are taking. The bus is controlled so that the condition of the BS signal in a first clock indicating the state occupied by the data values ​​of the data / address lines B in the subsequent next clock. This means that via the address / data lines 22 transmitted data values ​​correspond to the immediately previously transmitted a clock state of the bus state signal BS.

The first three bars 31 indicate the signal flow in a write access to the memory 3. In the first cycle, the bus is idle, the bus state BS occupies the signal value IDLE. In the subsequent operating clock 22 a randomly generated by the random data 12 RNG is transmitted through the data / address lines. In the following cycle, the bus state BS is switched from the bus master 11 to the state of the ADR for the address transfer. This means for the data / address signal lines 22 of the bus that a valid address MEM is transferred to a memory cell contained in the memory. 3 Below signaled the bus state BS a write operation WR. The bus lines 22 lead to the memory 3 to be stored in the memory cell with the previously specified in the clock address MEM data DATA.

Subsequently, five bars long no access to the CPU 1 in any of the units 3, 4 or 5. For this purpose, a clock is transmitted first long for the bus state BS the state IDLE. On the data / address lines 22 of the bus, a random data value RNG is output in the immediately subsequent clock. Then, the bus state BS indicates the transmission of an address by the condition ADR. A data NON transmitted on the data / address lines 22 then corresponding none of lying in the address space of units 3, 4 and 5 address. The data NON generated randomly in random 12th From programming point of view, this means that a one unit is addressed with the address NON, which do not exist in real hardware. Subsequently take the bus state BS is a signal states RD, WR and RD. In the associated timing portions of the address / data signal lines 22 generated by the random 12 random values ​​are transmitted RNG. In practice, much more than the three shown exemplarily bar sections may be present with the transmission of random number values ​​to the address / data signal lines.

Subsequently, the bus state BS is again switched to the idle state IDLE, wherein the address / data lines, a random value RNG is transmitted. This is followed by a write access to the peripheral unit 4 with the address P1 and a read access to the peripheral unit 5 with the address P2.

In the invention, a random data is on the data / address lines 22 of the bus 2 if no access to a connected peripheral units 3, 4 or 5 is requested by the CPU 1 is outputted. This is the case when the bus state signal indicating BS that an idle condition exists (IDLE), or a unit has been addressed, which is not assigned to the units connected to output data values ​​then randomly generated during Bussignalzustands WR or RD to the bus , In this way, the current profile of the microcontroller is obscured.