Microprocessor system and method of operation

The invention relates to a method for operating a microprocessor arrangement with a first and a further unit, a bus connected to these units with each other via the are connected to a line for a status signal and lines for more bus signals and a bus controller for Control of accesses to the first unit on the other Unit. In addition, the invention relates to a microprocessor arrangement, which is suitable for carrying out the method is.

Microprocessor assemblies include in addition to the central processing and control unit (CPU) further units such as Memory or peripheral units for signal input and Signal output integrated on a single chip, so-called Microcontroller. Such microcontrollers can in safety Systems, such as smart cards used, will. The microcontroller is used, among other to traffic between a reader and the chip card to encrypt, to check access permissions execute and other secret operations.

It is known that the function of the microcontroller for spying the timing of the energy consumed by the micro-controller Current can be used. From the current profile can be obtained, for example, trigger points to subsequent measurements at the correct time to control; or it could Conclusions on the specific type of processor used in pulled calculation and encryption / decryption algorithms will; or it can even parts of the processed Payload are determined. Particularly generate bus access a characteristic current profile, since they for a run set signal protocol and switching operations Due to the high capacitive loads to be driven a clear Current profile deliver. The application of conventional microcontrollers is in safety-critical applications, therefore, problematic.

The object of the invention is a method for specify operating a microprocessor arrangement, the tap-proof is.

Another object is to provide an implementation of the specify the method suitable microprocessor arrangement.

According to the invention, the object is on the procedure achieved by a method for operating a microprocessor arrangement with a first unit and a further unit; a bus over which the first unit with the further Unit is connected and a line for a state signal, indicating the operating state of the bus, and Lines for more bus signals indicating a data value, comprising; a bus controller for controlling accesses the first unit to the other unit via the bus; in which method, when the bus control unit of is communicated via the line for the state signal, that no access from the first unit to the other unit a data value is performed, generating randomly and is applied to the lines for the further bus signals becomes.

A microprocessor arrangement for performing the method according to the invention comprises: a first unit and a further Unit; a bus over which the first unit with the other unit is connected and a line for a State signal indicating the operating state of the bus, and lines for other bus signals indicating a data value, comprising; a bus control unit for controlling accesses the first unit to the other unit via the Bus; a random number generator, which with the lines for Additional bus signals is connected when the state signal indicates that no access from the first unit on the additional unit is to perform.

The bus state indicates for which task the bus from the central processing and control unit (CPU) is used at the moment. When the bus under consideration Clock section just in hibernation, are on the Bus data no valid signals. According to the invention then a randomly generated signal over the transmit data lines of the bus. Thereby, the Current Profile randomly changed. The current profile is characterized in relation to the power transmitted over the bus payload veiled, so that conclusions about the payload due to a statistical analysis of the current profile be much more difficult or even impossible.

According to the bus protocol can be provided that the bus state the state of the bus one clock in advance indicates. It is also possible that the bus state signal the state of the other bus in the same cycle indicates.

The addressable by the CPU units are assigned addresses. When the CPU by means of the bus control unit a a Memory or a peripheral unit assigned address outputs, this means that the memory and contained therein Memory cell or the corresponding peripheral unit is to be activated to receive data from the bus or output to the bus. In the invention, then, if no access to a connected from the CPU to the bus Unit takes place, although an address issued on the bus. However, this address is no address a bus connected unit is assigned, but a any other address. This has the result that neither of the attached devices is activated. Nevertheless, is transfer them to any address via the bus and thus generates a corresponding current profile. This address is generated randomly. The current profile is accordingly randomly changed. It is sure that the random number is not a valid address to a bus connected unit matches.

receives the output on the bus in this way data value the importance of an address by the respective state of the Buszustandsignals. The bus state also shows in that on the data lines of the bus an address either is issued or a date to the addressed unit output is (written) or addressed by the unit is received (read). For the addresses and to read or write data to the same signal lines use of the bus. This is called multiplexed Data / address bus designated. The term data is to be understood generally and includes data values, which an address or date data to be processed or instructions etc. represent. After the bus state has indicated that a resting state, is in subsequent clock transmit a random value. If a transmit address for which no device connected to the bus Unit exists, be in the subsequent operation clocks transmitted as long random values ​​until again by a valid address an existing unit is addressed. In recent microprocessors presented an address any connected unit was assigned to a programming error . In the invention, however, the transmission is such a randomized address interpreted to understand that an access to a non-existent target is performed to the otherwise unused bus cycles to disguise.

The bus of the microprocessor arrangement may additionally include a line comprise a release signal to the at Bus connected additional units is performed. The enable signal transmitted to those units that access over the bus. The enable line is expediently signaled by a by the bus state Hibernate driven with random values.

The invention is based on the in the drawing Illustrated embodiment explained in more detail. Show it:<dl tsize="7"><dt>figure 1</dt><dd>a block diagram relevant to the invention Elements of a microprocessor and</dd><dt>figure 2</dt><dd>a signal flow diagram.</dd></dl>

The microcontroller shown in Figure 1 comprises a central Control and processing unit (CPU) 1, by the the internal operations, in particular the number of hits on the bus 2 are controlled. For this purpose, the CPU includes a 1 Bus control unit 11. The bus itself comprises at least one Signal line 21, which indicates the bus state, and Plurality of lines 22, over which both addresses of the connected transfer units and data values ​​sequentially are so-called multiplexed data / address bus. At the bus 2 is a memory 3 is connected, in the to be processed Data values ​​and / or program instructions stored are. Furthermore, a first peripheral unit 4 is provided and a second peripheral unit 5, on the data exchanged chip externally connected functional units will. The microcontroller is used for example application in a chip card, to communicate with a reader. Each of the units connected to the bus 3, 4, 5, a bus interface 31, 41 and 51, respectively. The bus control unit 11 and the interfaces 31, 41, 51 operate in a master-slave dependency together.

When the bus 2 is idle, ie not the connected units 3, 4, 5 from the CPU 1 for an access is activated, then from the bus control unit 1 on the data lines 22, a sequence of randomly generated Data values ​​outputted. To generate the random data values used a random number generator 12, the multiplexer via a 13 is connected to the data lines 22 of the bus. If one of the units 3, 4, 5, addressed by the CPU 1 is, the multiplexer 13 switched to the other terminal 14 to which the data sent or received further to the Functional units of the CPU 1 forwards.

The bus state BS which transmitted on line 21 is, in Figure 2 along with the data / address lines 22 transmitted data values ​​B shown. The bus is intermittently operated so that respective signal states one clock period of the clock CLK are valid. The Bus state BS is the IDLE state for hibernation the ADR condition for the transmission of an address, State for a write operation WR, in which a date of the CPU 1 of one of the units 3, 4, 5 is transmitted, and a state RD for a read operation in which a data value read out from one of the units 3, 4, 5 and to the CPU 1 is transmitted taking. The bus is controlled such that the condition of the BS signal in a first clock state indicating the in the data values ​​of the data / address lines B taking following the next clock. This means that via the address / data lines 22 transmitted data values the immediate one clock previously transmitted state of Bus state signal BS correspond.

The first three bars 31 indicate the signal flow in a Write access to the memory 3. In the first clock is the bus is in idle state, the bus state BS the signal value IDLE occupies. In the subsequent operating clock is on the data / address lines 22 a from the random number generator 12 randomly generated data transmitted RNG. In the following cycle, the bus state BS is the bus master 11 is switched to the state of the ADR for the address transfer. This means for the data / address signal line 22 of the bus, that a valid address in the memory MEM of a 3 Memory cell contained is transmitted. Below signaled the bus state BS a write operation WR. The Bus lines 22 lead then to the memory 3 to the Memory cell with the previously specified in the clock address MEM data to be stored value DATA.

Subsequently, five bars long no access to the CPU 1 on any of the units 3, 4, or 5. For this purpose, first one measure for the bus state BS the state IDLE transfer. is on the data / address lines 22 of the bus in the immediately subsequent clock a random data value RNG output. Then signals the bus state BS transmitting an address by the condition ADR. On the data / address lines 22 is then a data value NON transmitted, which none of the address space of units 3, equivalent to 4 and 5 lying address. The data value is NON generated randomly in random 12th From a programming View this means that a unit with the Address NON is addressed, which is in real hardware not there. Subsequently take the bus state BS the Signal states RD, WR and RD a. In the associated timing portions be for the address / data signal lines 22 from Random transferred 12 generated random values ​​RNG. In practice, far more than the three exemplary shown cycling segments with the transmission of random number values present on the address / data signal lines.

Subsequently, the bus state BS is again a Idle state IDLE switch, wherein the address / data lines a random value RNG is transmitted. subsequently carried out a write access to the peripheral unit 4 with the address P1 and a read access to the peripheral unit 5 with the address P2.

In the invention, on the data / address lines 22 of the Bus 2 if no access to one of the connected Peripheral units 3, 4 or 5 requested by the CPU 1 is a random data output. This is the Case where the bus state BS indicates that a state of rest been addressed is present (IDLE), or a unit is associated with none of the member units, while to then randomly generated data values a Bussignalzustands WR or RD output to the bus. In this way, the current profile of the microcontroller veiled.