EP1035518A2

Arrangement for the protection of a security module

Abstract

The method involves monitoring the state of the use or exchange of the security module using at least two functional units, such as a microprocessor (120), a monitoring unit (12) and a detection unit (13). The state is signaled using the microprocessor. Sensitive data are erased by the monitoring unit when improper use or exchange is detected. The monitoring unit may monitor the correct installation or state of a battery (134). The detection unit may block the functionality on the basis of an exchange of the security module or a destruction condition. An Independent claim is included for an apparatus for performing the method.

EP1035518A2, drawing sheet 1
Sheet 1 of 13

Term

Term ended

Projected expiry passed 25 February 2020, 6.6 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

16 claims: 3 independent, 13 dependent

  1. 1
    Method of protecting a security module, comprising the following steps:• monitoring the state, the proper use or replacement of the safety module at least by means of two functional units (120, 12, 13), Signaling at least one state (220, 230, 240, 250, 260, 270, 280, 290) controlled by means of a first functional unit (120) and • Deletion of sensitive data due to improper use or replacement at least by means of a second functional unit (12).
  2. 2
    Proceeding, according to Ansprunch 1, characterized by in that a time sequence is detected by means of the first functional unit (120) and that another sequence of procedures is carried out to restore the functions, with the fonts:• Reinitialize by means of the first functional unit (120) of previously deleted sensitive data after proper use or replacement of the safety module, and • Recommissioning by activating the functional units (12, 13) of the safety module (100).
  3. 13
    Arrangement according to claims 10 to 12, characterized by . in that the processor (120) stores (122, 124), to which an operating voltage Ub + is conducted by a voltage monitoring unit (12) via the line (138), the processor (120) is supplied with system voltage Us + and has a fourth connection (pin 4), to reset the state of latching of the detection unit (13) via the line (137) and a fifth terminal (pin 5), to which the line (139) is connected, to query the state of the detection unit (13).