Nova Patents
EP0973262A2

Current mode logic circuit

Abstract

A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

EP0973262A2, drawing sheet 1
Sheet 1 of 61

Term

Term ended

Projected expiry passed 12 July 2019, 7.2 years ago.

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23 claims: 12 independent, 11 dependent

  1. 1
    An apparatus, comprising:a first resistor coupling a first reference voltage to a first output and to said first electrode of said third transistor;a second resistor for coupling said first reference voltage to a second output and to first electrodes of said first and second transistors and to a second electrode of said third transistor;a first input coupled to a second electrode of said first transistor;a second input coupled to a second electrode of said second transistor;and means for coupling a second reference voltage to a third electrodes of said first, second and third transistors.
  2. 6
    The apparatus of any one of Claims 1-5, wherein said first reference voltage is V DD .
  3. 7
    The apparatus of any one of Claims 1-6, wherein said second reference voltage is V SS .
  4. 10
    The apparatus of any one of Claims 1-5, 8, 9, wherein the voltage swing of a signal coupled to said first input is approximately in the range 400 to 800 mVolts.
  5. 11
    The apparatus of any one of Claims 1-5, 8, 9, and 10 wherein the voltage swing of a signal coupled to said second input is approximately in the range 400-800 mVolts.
  6. 12
    The apparatus of any one of Claims 1-5, 8, 9, and 10 wherein said first and second inputs are single ended inputs.
  7. 13
    The apparatus of any one of Claims 1-5, 8, 9, and 10 wherein said apparatus is a logic gate.
  8. 14
    The apparatus of any one of Claims 1-5, 8, 9, and 10 further comprising a fourth transistor having a first electrode coupled to first electrodes of said first and second transistors and to a second electrode of said third transistor;a third input coupled to a second electrode of said fourth transistor, and a third electrode of said fourth transistor coupled to said third electrodes of said first, second, and third transistors.
  9. 15
    A prescaler circuit, comprising:an input buffer for coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;a first input of said first flip-flop coupled to a first output of said second flip-flop;a second input of said first flip-flop coupled to a first output of said third flip-flop;a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;a second output of said second flip-flop coupled to a first input of said third flip-flop;a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;a third input of said third flip-flop coupled to the output of a logic gate;a first input of said logic gate coupled for receiving a select signal;a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop;a third input of said logic gate coupled to a first output of said sixth flip-flop;
  10. 18
    The prescaler circuit of any one of Claims 15-17, wherein:said first output of said first flip-flop is a non inverted output and said second out put is an inverted output;said first output of said second flip-flop is an inverted output and said second output is a non-inverted output;and said first output of said third flip-flop is an inverted output and said second output is a non-inverted output. said first output of said fourth flip-flop is an inverted output and said second output is a non-inverted output. said first output of said fifth flip-flop is an inverted output and said second output is a non-inverted output. said first output of said sixth flip-flop is an inverted output and said second output is a non-inverted output.
  11. 19
    A phase-lock-loop comprising:a charge pump for coupling a filter to a phase detector, said phase detector being further arranged to be coupled for receiving a clock signal;and a voltage controlled oscillator coupling a prescaler and an output to said filter, said prescaler being further coupled to said phase detector, said prescaler comprising: an input buffer for coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;a first input of said first flip-flop coupled to a first output of said second flip-flop;a second input of said first flip-flop coupled to a first output of said third flip-flop;a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;a second output of said second flip-flop coupled to a first input of said third flip-flop;a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;a third input of said third flip-flop coupled to the output of a logic gate;a first input of said logic gate coupled for receiving a select signal;a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop;and a third input of said logic gate coupled to a first output of said sixth flip-flop;
  12. 20
    19. A portable telephonic system, comprising:a duplex switch for coupling an antenna to a receiver and to a transmitter;a power supply arranged to be coupled to said receiver;baseband means for coupling said power supply to said receiver, transmitter and to a keypad and a speaker;a microphone coupled to said baseband means;and a phase-lock-loop for coupling said receiver to said transmitter, said phase-lock-loop comprising: a charge pump for coupling a filter to a phase detector, said phase detector being further arranged to be coupled for receiving a clock signal;and a voltage controlled oscillator for coupling a prescaler and an output to said filter, said prescaler being further arranged to be coupled to said phase detector;
Independent claims12