A method for fabricating a small area of contact between electrodes

Description of equivalent WO 9836446 A2

A METHOD FOR FABRICATING A SMALL AREA OF CONTACT BETWEEN ELECTRODES

BACKGROUND OF THE INVENTION

0003A. Field of the Invention

0004The present invention relates generally to semiconductor fabrication techniques and, more particularly, to a method for fabricating a small contact area between an upper and lower electrode for use in phase changeable memory devices such as, for

0005example, chalcogenide memory cells.

0006B. Description of the Prior Art

0007The use of electrically writable and erasable phase change materials, i.e., materials that can be electrically switched between generally amorphous and generally crystalline states or between different resistive states while in crystalline form, for

0008electronic memory applications is well known in the art. The use of phase change materials is disclosed, for example, in U.S. Patent No. 5,296,716, in the names of Ovshinsky et al., the disclosure of which is incorporated herein by reference. U.S. Patent No. 5,296,716 is believed to indicate generally the state of the art, and to

0009contain a discussion of the current theory of operation of chalcogenide materials.

0010Generally, as disclosed in the Ovshinsky patent, such phase change materials can be electrically switched between a first structural state where the material is generally amorphous and a second structural state where the material has a generally

0011crystalline local order. The material may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states. That is, the switching of such materials is not required to take place between completely amorphous and completely crystalline states, but rather, the material can be switched in incremental steps reflecting changes of local order to provide a "gray scale" represented by a

0012multiplicity of conditions of local order spanning the spectrum from the completely

0013amorphous state to the completely crystalline state.

0014Chalcogenide material exhibits different electrical characteristics depending

0015upon its state. For example, in its amorphous state the material exhibits lower

0016electrical conductivity than it does in its crystalline state. The operation of

0017chalcogenide memory cells requires that a region of the chalcogenide memory material,

0018called the chalcogenide active region, be subjected to a current pulse typically with a

0019current density between 10⁵ and 10⁷ amperes/cm², to change the crystalline state of the

0020chalcogenide material within the active region contained within a small pore. This

0021current density may be accomplished by first creating a small opening in a dielectric

0022material that is itself deposited onto a lower electrode material. A second dielectric

0023layer, typically of silicon nitride, is then deposited onto the dielectric layer into the

0024opening. The second dielectric layer is typically about 40 Angstroms thick. The

0025chalcogenide material is then deposited over the second dielectric and into the opening.

0026An upper electrode material is then deposited over the chalcogenide material. Carbon

0027is commonly used as the electrode material, although other materials have also been

0028used, for example, molybdenum and titanium nitride. A conductive path is then

0029provided from the chalcogenide material to the lower electrode material by forming a.

0030pore in the second dielectric layer by a well-known firing process.

0031Firing involves passing an initial high current pulse through the structure that

0032passes through the chalcogenide material and then provides dielectric breakdown of the second dielectric layer, thereby providing a conductive path via the pore created

0033through the memory cell. Electrically firing the thin nitride layer is not desirable for a

0034high density memory product due to the high current required and the large amount of

0035testing time required for the firing.

0036The active regions of the chalcogenide memory cells within the pores are

0037believed to change crystalline structure in response to applied voltage pulses of a wide

0038range of magnitudes and pulse durations. These changes in crystalline structure alter

0039the bulk resistance of the chalcogenide active region. The wide dynamic range of these

0040devices, the linearity of their response, and lack of hysteresis provide these memory

0041cells with multiple bit storage capabilities.

0042Factors such as pore dimensions (i.e., diameter, thickness and volume),

0043chalcogenide composition, signal pulse duration and signal pulse waveform shape have

0044an effect on the magnitude of the dynamic range of resistances, the absolute endpoint

0045resistances of the dynamic range, and the currents required to set the memory cells at

0046these resistances. For example, relatively large pore diameters, e.g., about one

0047micron, will result in higher programming current requirements, while relatively small

0048pore diameters, e.g., about 500 Angstroms, will result in lower programming current

0049requirements. The most important factor in reducing the required programming

0050current is the pore cross sectional area. The energy input required to adjust the crystalline state of the chalcogenide

0051active region of the memory cell is directly proportional to the dimensions of the

0052minimum lateral dimension of the pore, e.g., smaller pore sizes result in smaller energy input requirements. Conventional chalcogenide memory cell fabrication

0053techniques provide minimum lateral pore dimension, diameter or width of the pore,

0054that is limited by the photolithographic size limit. This results in pore sizes having

0055minimum lateral dimensions down to approximately 0.35 microns. However, further

0056reduction in pore size is desirable to achieve improved current density for writing to

0057the memory cell.

SUMMARY OF THE INVENTION

0059The present invention is directed at overcoming, or at least reducing the effects

0060of, one or more of the problems set forth above. In particular, the present invention

0061provides a method for fabricating a small contact area between electrodes of

0062chalcogenide memory cells, such that the contact area provides minimum dimensions

0063below the photolithographic limit, thereby reducing the required energy input to the

0064chalcogenide active region in operation. The electrodes are further selected to provide

0065material properties that permit enhanced control of the current passing through the

0066chalcogenide memory cell. As a result, the memory cells may be made smaller to

0067provide denser memory arrays, and the overall power requirements for the memory

0068cells are miriimized.

0069Additional advantages of the invention will be set forth in part in the description

0070that follows, and in part will be obvious from the description, or may be learned by

0071practice of the invention. In accordance with the purpose of the invention, as embodied and broadly

0072described herein, the invention comprises a method of manufacturing a semiconductor

0073device comprising the steps of providing a conductive layer on a substrate; patterning

0074the conductive layer to form a raised portion of the conductive layer; providing an

0075insulating layer on the conductive layer including the raised portion; and selectively

0076removing a portion of the insulative layer to expose part of the raised portion of the

0077conductive layer.

0078In another aspect, the present invention comprises an integrated circuit device

0079comprising: a substrate having a primary surface; a conductive layer provided on the

0080primary surface, the conductive layer having a raised portion; an insulative layer

0081overlying the first conductive layer and exposing part of the raised portion; and a layer

0082of programmable resistive material provided in contact with the exposed part of the

0083raised portion of the first conductive layer, the exposed part of the raised portion being

0084narrower than remaining part of the raised portion of the first conductive layer.

0085In still another aspect, the present invention comprises an integrated circuit

0086comprising: a first electrode having a first portion and a second portion, a width of the

0087first electrode narrowing continuously in a direction from the second portion to the first

0088portion of the first electrode; a layer of programmable resistive material provided in

0089contact with the first electrode; and a second electrode coupled to the layer of

0090programmable resistive material. It is to be understood that both the foregoing general description and the

0091following detailed description are exemplary and explanatory only and are not

0092restrictive of the invention, as claimed.

0093BRffiF DESCRIPTION OF THE DRAWINGS

0094The accompanying drawings, which are incorporated in and constitute a part of

0095this specification, illustrate one embodiment of the present invention and, together with

0096the description, serve to explain the principles of the invention. In the drawings:

0097FIG. 1 is a fragmentary cross sectional view of the deposition of a layer of

0098polysilicon onto a substrate of titanium nitride in accordance with a preferred

0099embodiment of the present invention;

0100FIG. 2 is a fragmentary cross sectional view of the deposition of a layer of

0101silicon oxide and a layer of resist material onto the layer of polysilicon;

0102FIG. 3 is a fragmentary cross sectional view of a contact pattern that is etched

0103in the layer of resist material and the silicon oxide layer using etching, masking, and

0104photoresist stripping techniques;

0105FIG. 4(a) is an overhead view of a generally rectangular contact pattern formed

0106from the resist material and silicon oxide layers;

0107FIG. 4(b) is an overhead view of a generally circular contact pattern formed

0108from the resist material and silicon oxide layers;

0109FIG. 5 is fragmentary cross sectional view of the device after the resist material

0110layer has been stripped away using strip etching techniques; FIG. 6 is a fragmentary cross sectional view of a portion of the layer of

0111polysilicon material not covered by the silicon oxide layer pattern that is etched using

0112conventional undercut isotropic etching techniques to form a frusto-conical shaped tip

0113in the layer of polysilicon material;

0114FIG. 7 is a fragmentary cross sectional view of the device after the contact

0115pattern has been removed using conventional wet etch techniques;

0116FIG. 8 is a fragmentary cross sectional view of the depositing of a layer of

0117insulative material onto the layer of polysilicon material, including the tip, using

0118conventional thin film deposition methods to isolate the layer of polysilicon material,

0119including the tip;

0120Fig. 9 is a fragmentary cross sectional view of planarization of the layer of

0121insulative material using a conventional chemical mechanical planarization (CMP)

0122process;

0123FIG. 10 is a fragmentary cross sectional view of a chalcogenide material layer

0124that is deposited using conventional thin film deposition methods;

0125FIG. 11 is a fragmentary cross sectional view of a layer of conductive material

0126deposited over the chalcogenide layer using conventional thin film deposition

0127techniques;

0128FIG. 12 is a fragmentary cross sectional view of the layer of chalcogenide

0129material and the second layer of conductive material after they are etched back using

0130conventional masking and etching techniques; FIG. 13 is a fragmentary cross sectional view of a second layer of insulative

0131material that is applied using conventional thin film deposition techniques;

0132FIG. 14 is a fragmentary cross sectional view of the second layer of insulating

0133material after it is etched back; and

0134FIG. 15 is a fragmentary cross sectional view of the complete chalcogenide

0135memory cell including an upper conductive grid layer.

DESCRIPTION OF THE PREFERRED EMBODIMENT

0137A method of fabricating a small area of contact between electrodes of

0138chalcogenide memories is presented that provides an area of contact with the lower

0139electrode by the upper electrode, via the chalcogenide material, that is smaller than that

0140presently provided using conventional photolithographic techniques. In particular, the

0141preferred embodiment of the present invention provides a method of fabricating

0142electrodes for chalcogenide memories in which a minimum area of contact of the lower

0143electrode with the upper electrode is formed by creating a tip on the lower electrode.

0144In this manner, the lower electrode having a minimum area of contact as small as

01450.00785 μm² is obtained. The present preferred embodiment thus provides enhanced

0146control of the current passing through the resulting chalcogenide memory, and thus,

0147^"reduces the total current and energy input required to the chalcogenide active region in

0148operation. The total current passing through the chalcogenide active region is two

0149milliamps (mA). Thus, the current density required by the preferred embodiment is 1

0150x 10⁶ A/cm² to 1 x 10⁷ A/cm². Furthermore, the preferred embodiment allows the memory cells to be made smaller and thus allow the production of denser memory

0151arrays, and allows the overall power requirements for the memory cell to be

0152minimized.

0153Reference will now be made in detail to the present preferred embodiment of

0154the invention, an example of which is illustrated in the accompanying drawings.

0155Wherever possible, the same reference numbers will be used throughout the drawings

0156to refer to the same or like parts.

0157Turning to the drawings and referring to FIGs. 1 to 15, a preferred embodiment

0158of a method for fabricating a small area of contact between an upper and lower

0159electrode for chalcogenide memories will now be described. A layer 22 of conductive

0160material, preferably polysilicon, is deposited onto a substrate 20 using conventional

0161thin film deposition methods such as, for example, chemical vapor deposition (CVD),

0162as illustrated in FIG. 1. The layer 22 of conductive material may have a substantially

0163uniform thickness ranging from 5000 to 7000 Angstroms, and preferably will have a

0164substantially uniform thickness of approximately 6500 Angstroms. Substrate 20 may

0165also be comprised of a conductive material such as, for example, silicon, TiN, Carbon,

0166WiSi_x, or Tungsten, and preferably will be comprised of silicon. The substrate 20 will

0167further preferably comprise a lower electrode grid (not shown) used for accessing an

0168array of chalcogenide memories. A layer 23 of silicon oxide is deposited onto the substrate 22, preferably by

0169CVD, and preferably will have a thickness of 500 Angstroms. A layer 24 of resist

0170material is spun onto the silicon oxide layer 23, as illustrated in FIG. 2. The layer 24 of resist material preferably will have a substantially uniform thickness of

0171approximately 15,000 Angstroms.

0172A contact pattern 26, is then etched in the resist layer 24 and the silicon oxide

0173layer 23 using conventional masking, exposing, etching, and photoresist stripping

0174techniques as shown in FIG. 3. The contact pattern 26 may be formed from the resist

0175layer 24 and silicon oxide layer 23, for example, as a generally rectangular block as

0176shown in FIG. 4(a), or as a substantially circular block as shown in FIG. 4(b). Contact

0177pattern 26 is preferably formed using a conventional contact hole mask resulting in the

0178substantially circular block shown in FIG. 4(b). The minimum lateral dimension of the

0179contact pattern 26 preferably will be approximately 0.4 μm. The contact pattern 26

0180includes a generally horizontal bottom surface 28, common to the polysilicon layer 22,

0181and generally vertical side walls 27 at its outer periphery.

0182The resist layer 24 is then removed using conventional stripping techniques

0183after the contact 26 has been patterned in the silicon oxide layer 23, as shown in FIG.

01845. Thus, the silicon oxide layer 23 remains as the contact pattern 26. The silicon

0185oxide layer 23 contact pattern is used as a masking layer when the polysilicon layer 22

0186is subsequently etched.

0187The portion of the polysilicon layer 22 not covered by silicon oxide layer

0188pattern 23 is etched, and the portions beneath silicon oxide pattern 23 are undercut, using wet etch or dry plasma etching techniques to form a frusto-conical shaped tip 30

0189in the polysilicon layer 22, as shown in FIG. 6. The resulting tip 30 is frusto-conical

0190in shape preferably having a minimum frustum lateral dimension of approximately 0.1 μm. The base of the tip 30 preferably will have a base rninimum lateral dimension of

0191approximately 0.4 μm, i.e., the same dimension as the lateral dimension of the contact

0192pattern 26. Tip 30 will preferably have a height of approximately 2000 Angstroms.

0193The removal of the silicon oxide layer pattern 23 is accomplished using conventional

0194wet etch techniques as shown in FIG. 7. Contact pattern 26 thus provides a means for

0195defining the area of contact of the base of the frusto-conical tip 30 of layer 22 of

01960.00785 μm² [π x (0.1/2)²].

0197A layer 32 of insulative material is deposited onto the polysilicon layer 22,

0198including the tip 30, using conventional thin film deposition methods such as, for

0199example, CVD, to isolate the polysilicon layer 22, including the tip 30, as illustrated in

0200FIG. 8. The layer 32 of insulative material may have a substantially uniform thickness

0201of approximately 2000 to 5000 Angstroms, and preferably will have a substantially

0202uniform thickness of approximately 2000 Angstroms, i.e. , the same thickness as the

0203height of the tip 30. Layer 32 of insulative material may be comprised of silicon oxide

0204or silicon nitride, and preferably will be comprised of silicon oxide.

0205The layer 32 of insulative material is then preferably planarized using a

0206conventional chemical mechanical planarization (CMP) process as illustrated in FIG..9.

0207The CMP process is performed to expose the top surface 24 of the tip 30 formed on the

0208polysilicon layer 22 that may also be referred to as the lower electrode.

0209The chalcogenide memory cell is then formed incorporating the tip 30 of the

0210polysilicon layer 22 using conventional semiconductor processing techniques such as,

0211for example, thin-film deposition, masking, and etching processes. As shown in FIG. 15, the chalcogenide memory cell preferably includes a layer 34 of chalcogenide

0212material, a layer 36 of conductive material serving as an upper electrode, an interlayer

0213dielectric (ILD) layer 38, and an upper conductive layer 40.

0214The chalcogenide material layer 34 may be deposited using conventional thin

0215film deposition methods, as shown in FIG. 10. Chalcogenide material layer 34

0216preferably is approximately 500 Angstroms thick. Typical chalcogenide compositions

0217for these memory cells include average concentrations of Te in the amorphous state

0218well below 70% , typically below about 60% and ranging in general from as low as

0219about 23% up to about 56% Te, and most preferably to about 48% to 56% Te.

0220Concentrations of Ge are typically above about 15 % and range from a low of about

022117% to about 44% on average, and remain generally below 50% Ge, with the

0222remainder of the principal constituent elements in this class being Sb. The percentages

0223are atomic percentages which total 100% of the atoms of the constituent elements. In a

0224particularly preferred embodiment, the chalcogenide compositions for these memory

0225cells comprise a Te concentration of about 56%, a Ge concentration of about 22% , and

0226a Sb concentration of about 22% . The materials are typically characterized as

0227Te.Ge_bSb_l0(Ha+b), where a is equal to or less than about 70% and preferably between

0228about 40% to about 60% , b is above about 15% and less than 50% , and preferably

0229between about 17% to 44% , and the remainder is Sb.

0230The carbon layer 35 is preferably 600 Angstroms thick and is provided over the

0231chalcogenide layer 34 using conventional thin film deposition techniques, as shown in

0232FIG. 11. Layer 36 of conductive material is deposited over the carbon layer 35 using conventional deposition techniques, as further shown in FIG. 11. The layer 36 of

0233conductive material thereby provides an upper electrode for the chalcogenide memory

0234cell. The layer 36 of conductive material is preferably titanium nitride (TiN), but may

0235comprise TiN or carbon, and has a thickness of approximately 500 Angstroms. Layers

023634-36 are subsequently etched back using conventional masking and etching techniques,

0237as shown in FIG. 12.

0238As shown in FIG. 13, the ILD layer 38 is then applied using conventional thin

0239film deposition techniques. The ILD layer 38 preferably is approximately 3500

0240Angstroms thick, and comprises silicon oxide. The ILD layer 38 is then etched back,

0241as shown in FIG. 14, using conventional masking and etching processes to provide

0242access to the layer 36 of conductive material or upper electrode by the upper

0243conductive grid 40. Upper conductive grid interconnect 40 may be formed by first

0244applying a blanket deposition of conductive material using conventional thin film

0245deposition processes and then by etching the conductive material to form the upper

0246conductive grid interconnect extending above the surface of the ILD layer 38, as shown

0247in FIG. 15. The upper conductive grid 40 material may comprise materials such as,

0248for example, Ti, TiN, or aluminum, and preferably it will comprise aluminum.

0249In a particularly preferred embodiment, the methods described above are

0250utilized to form an array of chalcogenide memory cells that are addressable by an X-Y

0251grid of upper and lower conductors, i.e., electrodes. In the particularly preferred

0252embodiment, diodes are further provided in series with the chalcogenide memory cells

0253to permit read/write operations from/to individual chalcogenide memory cells as will be recognized by persons of ordinary skill in the art. The present invention includes the

0254fabrication of a plurality of tips 30 on the lower electrode, i.e. , the polysilicon layer

025522, such that a plurality of chalcogenide memory cells may be created. The drawings

0256show only a single tip 30 for ease of illustration of the present invention. Furthermore,

0257while a range of materials may be utilized for each layer, the particular materials

0258selected for each layer must be selected to provide proper selectivity during the various

0259etching processes as will be recognized by persons of ordinary skill in the an.

0260Other embodiments of the invention will be apparent to those skilled in the art

0261from consideration of the specification and practice of the invention disclosed herein.

0262It is intended that the specification and examples be considered as exemplary only, with

0263a true scope and spirit of the invention being indicated by the following claims.