Television receiver, video signal processing device, image processing method and device
Abstract
The television receiver including a display device capable of displaying a video signal having a predetermined display format of this invention includes: a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
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30 claims: 6 independent, 24 dependent
- 1A television receiver including a display device capable of displaying a video signal having a predetermined display format, the television receiver comprising:a plurality of video signal sources;a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources;and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
- 3A television receiver including a display device capable of displaying a video signal having a predetermined display format, the television receiver comprising:a plurality of video signal sources;a selection circuit for selecting at least two of a plurality of video signals output from the plurality of video signal sources;and an image processor for converting a format of each of the at least two video signals selected by the selection circuit into a predetermined display format, and processing the at least two video signals so that synthesized images are displayed on the display device, wherein a video signal output from the processor is supplied to the display device.
- 5A video signal processing apparatus comprising:a plurality of video signal input terminals for receiving a plurality of video signals;a selection circuit for selecting one of the plurality of video signals input via the plurality of video signal input terminals;and an image processor for converting a format of the video signal selected by the selection circuit into a predetermined display format.
- 6A video signal processing apparatus comprising:a plurality of video signal input terminals for receiving a plurality of video signals;a selection circuit for selecting at least two of the plurality of video signals input via the plurality of video signal input terminals;and an image processor for converting a format of each of the at least two video signals selected by the selection circuit into a predetermined display format, and synthesizing the at least two video signals.
- 7An image processing device comprising:an input section for receiving image data to be processed;a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal processing section receiving, processing, and outputting the image data for each scanning line;an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;an output section for outputting processed image data;data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another;and control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data.
- 29A video signal processing device comprising:a first converter for receiving a plurality of video data units corresponding to a plurality of pixels connected to one scanning line as an input video signal, and converting the plurality of video data units into a plurality of video data sets, each of the plurality of video data sets including at least two video data units;an operator for processing the plurality of video data sets and outputting a plurality of processed video data sets;and a second converter for converting the plurality of processed video data sets into a plurality of processed video data units corresponding to a plurality of pixels connected to one scanning line, and outputting the plurality of processed video data units as an output video signal.
Independent claims6
266 paragraphs in 6 sections, as filed
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION:
0001The present invention relates to a television receiver, a video signal processing device, an image processing device, and an image processing method.
2. DESCRIPTION OF THE RELATED ART:
0002In recent years, the methods of broadcasting television signals have been diversified. For instance, not only have NTSC (National Television System Committee) signals been broadcasted using a ground wave but also both NTSC signals and high-definition signals have been broadcasted using a broadcasting satellite (BS). Further, just recently, digital signals have been broadcasted using a communication satellite (CS).
0003With the diversified methods of broadcasting, television receivers are demanded to have a capability of receiving various types of signals from such diversified broadcasting methods to display corresponding images.
0004Each of the different broadcasting methods uses a video format which is different from one another. For example, the NTSC signal broadcasting uses a video format of 525 horizontal scanning lines/interlace scanning, while the high-definition signal broadcasting uses a video format of 1125 horizontal scanning lines/interlace scanning. Further, in recent years, television receivers have been requested to display video signals having video formats of VGA (video graphics array) and SVGA (super VGA) which are output from computers. As such, the demands on the display function of television receivers have increasingly become strong.
0005When a television receiver capable of displaying video signals having a variety of video formats is attempted to be realized, one may consider providing different conversion devices for input signals having different image formats. Such a configuration, however, requires the same number of conversion devices as that of the possible different image formats, thereby increasing the circuit size and the cost.
0006A conventional image processing device for performing digital image processing for video signals such as television signals is shown in Figure <b>26.</b> Referring to Figure <b>26,</b> the image processing device includes a digital signal processing circuit <b>2200</b> constructed to perform a predetermined image processing for video signals and at least one field memory and/or frame memory <b>2202.</b>
0007In the case of a moving-image real-time processing, for example, a frame memory <b>2202A</b> and a field memory <b>2202B</b> are used for motion detection, while a frame memory <b>2202C</b> is used for motion adaption interpolation. An additional frame memory (not shown) may be used for time-axis conversion for converting a high-definition signal into an NTSC signal, for example.
0008Thus, a conventional digital image processing circuit needs more field memories or frame memories as more types of image processing are required. This is disadvantageous in the aspects of reducing the cost and size of the device. Dynamic random access memories (DRAMs) having a capacity of 1 to 2 M bits are used for general type field memories and frame memories. These DRAMs are extremely small in memory capacity compared with presently mainstream 16M-bit and 64M-bit dynamic RAMs, but are not so different in cost and chip size from the latter.
0009As the number of field memories and/or frame memories increases, the number of terminal pins of the digital signal processing circuit <b>2200</b> increases proportionally, thereby increasing the size of the resultant IC package.
0010Another problem is that the system with the above configuration is poorly adaptive to a variety of applications. For example, a system constructed for the NTSC signal using field memories having a capacity of 1.5 M bits is not used for the high-definition signal which needs field memories having a capacity of about 4 M bits.
0011Moreover, the usage of each of such a number of field memories and/or frame memories is restricted or specified in accordance with functions defined by a processing section of the digital signal processing circuit <b>2200.</b> Such a conventional image processing device therefore generally fails to be used for a variety of applications.
0012Conventionally, therefore, when one television receiver is intended to receive a variety of video signals such as an NTSC signal, a BS signal, a high-definition signal, and a signal output from a computer, it is required to incorporate all of the different types of digital signal processing circuits, together with relevant field/frame memories, exclusive for respective types of video signals. The resultant device is extremely high in cost and large in size.
0013In addition to the current demands being placed on the digital signal processing circuitry, with the onset of digital broadcasting and the enhancement of the broadcasting image quality, a video signal processing circuit incorporated in a television receiver and the like similarly has been demanded to have a function of processing video signals having different formats. Moreover, such a video signal processing circuit has been demanded to have a function of displaying as much information as possible simultaneously, such as a double-screen display and a multi-screen display. Under these circumstances, a single-instruction multiple-data (SIMD) type video signal processor has been used as the video signal processing circuit.
0014The SIMD video signal processor processes a video signal for each horizontal scanning line, and includes N processor elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub> wherein N is an integer more than the number of effective pixels connected to one horizontal scanning line. Each of the N processor elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub> processes video data corresponding to one of the pixels connected to one horizontal scanning line.
0015Figure <b>32</b> illustrates a configuration of a conventional video signal processor <b>3100.</b> The video signal processor <b>3100</b> includes a data input register <b>3101</b>, an operator <b>3102</b>, and a data output register <b>3105.</b>
0016The data input register <b>3101</b> outputs a plurality of serially input video data units to the operator <b>3102</b> in parallel. The data input register <b>3101</b> has a width of <b>s</b> bits and a depth of <b>N</b> words. The bit width <b>s</b> of the data input register <b>3101</b> is larger than a bit width of a general video signal to be processed. This is because there arises instances where a current luminance signal and a luminance signal delayed by one field must be input into the data input register <b>3101</b> simultaneously, for example.
0017The operator <b>3102</b> performs a predetermined arithmetic operation for the plurality of video data units output from the data input register <b>3101</b> in parallel. The operator <b>3102</b> includes N processor elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub>. Each of the processor elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub> includes a small-capacity memory <b>3103</b> which holds the input data and operation results and an operating element <b>3104</b> which performs a predetermined signal processing operation.
0018The data output register <b>3105</b> outputs the plurality of video data units processed by the operator <b>3102</b> in series. The data output register <b>3105</b> has a width of <b>t</b> bits and a depth of <b>N</b> words. The bit width <b>t</b> of the data output register <b>3105</b> is also larger than a bit width of a general video signal to be processed. This is because there arises instances where an output video signal and data relating to a motion delayed by one field must be output from the data output register <b>3105</b> simultaneously, for example.
0019Hereinbelow, the operation of the video signal processor <b>3100</b> will be described, taking as an example a process of removing a horizontal high frequency band component included in a video signal, i.e., a processing of performing horizontal low-pass filtering for a video signal (hereinbelow, referred to as an LPF processing).
0020Figure <b>33</b> illustrates operations of the data input register <b>3101</b>, the operator <b>3102</b>, and the data output register <b>3105</b> in the LPF processing. In Figure <b>33</b>, the x-axis represents the time.
0021The video signal processor <b>3100</b> operates in accordance with a horizontal synchronous signal which defines horizontal blanking periods and effective video periods as shown in Figure <b>33.</b>
0022During an effective video period <b>P</b><sub><b>i</b></sub>, a plurality of video data units corresponding to a plurality of effective images connected to one horizontal scanning lines are input into the data input register <b>3101</b> in series. For example, one horizontal scanning line may be the i-th horizontal scanning line. Hereinbelow, the i-th horizontal scanning line is referred to as the i line wherein i is an arbitrary integer.
0023During a horizontal blanking period <b>B</b><sub><b>i</b></sub> following the effective video period <b>P</b><sub><b>i</b></sub>, the plurality of video data units corresponding to the i line input into the data input register <b>3101</b> are transferred to the operator <b>3102</b> in parallel.
0024During an effective video period <b>P</b><sub><b>i+1</b></sub> following the horizontal blanking period <b>B</b><sub><b>i</b></sub>, the LPF processing is performed for the plurality of video data units corresponding the i line.
0025During a horizontal blanking period <b>B</b><sub><b>i+1</b></sub> following the effective video period <b>P</b><sub><b>i+1</b></sub>, a plurality of LPF-processed video data units corresponding to the i line are transferred to the data output register <b>3105</b> in parallel.
0026During an effective video period <b>P</b><sub><b>i+2</b></sub> (not shown in Figure <b>33</b>) following the horizontal blanking period <b>B</b><sub><b>i+1</b></sub>, the plurality of LPF-processed video data units corresponding the i line are output from the data output register <b>3105</b> in series.
0027The above-described process is also performed for a plurality of video data units corresponding to an (i-1) line and a plurality of video data units corresponding to an (i+1) line.
0028Figure <b>34</b> diagrammatically illustrates the LPF processing performed by the operator <b>3102</b>. In Figure <b>34</b>, the operator <b>3102</b> is shown to perform the LPF processing for video data units <b>D</b><sub><b>j-2</b></sub>, <b>D</b><sub><b>j-1</b></sub>, <b>D</b><sub><b>j</b></sub>, <b>D</b><sub><b>j+1</b></sub>, <b>D</b><sub><b>j+2</b></sub> corresponding to the i line, and output LPF-processed video data units <b>D'</b><sub><b>j-2</b></sub>, <b>D'</b><sub><b>j-1</b></sub>, <b>D'</b><sub><b>j</b></sub>, <b>D'</b><sub><b>j+1</b></sub>, <b>D'</b><sub><b>j+2</b></sub> corresponding to the i line.
0029The LPF-processed video data unit <b>D'</b><sub><b>j</b></sub> is obtained by the calculation of expression (1) below:<maths id="math0001" num="(1)"><math display="block"><mrow><msub><mrow><mtext>D'</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext> = 1/4·D</mtext></mrow><mrow><mtext>j-1</mtext></mrow></msub><msub><mrow><mtext> + 1/2·D</mtext></mrow><mrow><mtext>j</mtext></mrow></msub><msub><mrow><mtext> + 1/4·D</mtext></mrow><mrow><mtext>j+1</mtext></mrow></msub></mrow></math><img file="EP0905973A2_D0001.tif" /></maths>
0030The calculation of expression (1) is performed by the processor element <b>PE</b><sub><b>j</b></sub>. Similar calculations to that of expression (1) are performed by the processor elements <b>PE</b><sub><b>j-2</b></sub>, <b>PE</b><sub><b>j-1</b></sub>, <b>PE</b><sub><b>j+1</b></sub>, <b>PE</b><sub><b>j+2</b></sub>. Only one LPF processing is performed by each of the processor elements <b>PE</b><sub><b>j-2</b></sub>, <b>PE</b><sub><b>j-1</b></sub>, <b>PE</b><sub><b>j</b></sub>, <b>PE</b><sub><b>j+1</b></sub>, <b>PE</b><sub><b>j+2</b></sub> for one line. In this way, the LPF-processed video data units <b>D'</b><sub><b>j-2</b></sub>, <b>D'</b><sub><b>j-1</b></sub>, <b>D'</b><sub><b>j</b></sub>, <b>D'</b><sub><b>j+1</b></sub>, <b>D'</b><sub><b>j+2</b></sub> corresponding to the i line are obtained.
0031Thus, as described above, a plurality of video data units corresponding to one horizontal scanning line can be processed using a video signal processor including the number of processor elements equal to or more than the number of effective pixels connected to one horizontal scanning line.
0032In order to make video apparatuses such as television receivers more prevailing, further cost reduction of the video signal processor, as well as the sophistication thereof, are essential.
0033In the above-described conventional video signal processor, however, if the number of processor elements included in the video signal processor is smaller than the number of effective pixels connected to one horizontal scanning line, video data units corresponding to the effective pixels which have no corresponding processor elements fail to be processed. To avoid this problem, the number of processor elements included in the video signal processor must be increased as the number of effective pixels connected to one horizontal scanning line increases. This causes an increase in the cost of the video signal processor when the processing of high-precision video signals is involved.
SUMMARY OF THE INVENTION
0034The television receiver including a display device capable of displaying a video signal having a predetermined display format of this invention includes: a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
0035In one embodiment of the invention, each of the plurality of video signal sources includes at least one of an NTSC decoder, a MUSE decoder, and a digital decoder.
0036Alternatively, the television receiver including a display device capable of displaying a video signal having a predetermined display format of this invention includes: a plurality of video signal sources; a selection circuit for selecting at least two of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of each of the at least two video signals selected by the selection circuit into a predetermined display format, and processing the at least two video signals so that synthesized images are displayed on the display device, wherein a video signal output from the processor is supplied to the display device.
0037In one embodiment of the invention, each of the plurality of video signal sources includes at least one of an NTSC decoder, a MUSE decoder, and a digital decoder.
0038According to another aspect of the invention, a video signal processing apparatus is provided. The video signal processing apparatus includes: a plurality of video signal input terminals for receiving a plurality of video signals; a selection circuit for selecting one of the plurality of video signals input via the plurality of video signal input terminals; and an image processor for converting a format of the video signal selected by the selection circuit into a predetermined display format.
0039Alternatively, the video signal processing apparatus of this invention includes: a plurality of video signal input terminals for receiving a plurality of video signals; a selection circuit for selecting at least two of the plurality of video signals input via the plurality of video signal input terminals; and an image processor for converting a format of each of the at least two video signals selected by the selection circuit into a predetermined display format, and synthesizing the at least two video signals.
0040According to still another aspect of the invention, an image processing device is provided. The image processing device includes: an input section for receiving image data to be processed; a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal processing section receiving, processing, and outputting the image data for each scanning line; an image memory having a fixed memory region and capable of performing a write operation and a road operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line; an output section for outputting processed image data; data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data.
0041In one embodiment of the invention, the digital signal processing section includes: a data input portion for receiving in parallel for each scanning line at least one image data unit corresponding to at least one respective video signal; and a data output portion for outputting in parallel for each scanning line the at least one image data unit processed for each scanning line by the plurality of processing elements, wherein a data input operation for each scanning line by the data input portion, a processing operation for each scanning line by the plurality of processing elements, and a data output operation for each scanning line by the date output section are performed in a pipeline manner.
0042In another embodiment of the invention, the image memory includes: data write means for sequentially writing the input image data into the memory region in sequential addresses; data read means for reading the image data to be output from the memory region in sequential addresses; and pointer control means for controlling a write pointer and a read pointer for indicating a write address and a read address in the memory region, respectively, in accordance with the program data.
0043In still another embodiment of the invention, the image memory further includes: a plurality of input buffers each having at least first and second input buffer portions with a respective predetermined memory capacity; and means for controlling the plurality of input buffers such that when the first input buffer portion of the input buffer is filled with image data, writing of input image data into the second input buffer portion is started, and image data is read from the first input buffer portion to be written into the memory region, and when the second input buffer portion is filled with image data, writing of input image data into the first input buffer portion is started, and image data is read from the second input buffer portion to be written into the memory region.
0044In still another embodiment of the invention, a data rate at which image data is written into the memory region from the input buffer is selected to be different from a data rate at which image data is written into the input buffer.
0045In still another embodiment of the invention, the image memory further includes: a plurality of output buffers each having at least first and second output buffer portions with a respective predetermined memory capacity; and means for controlling the plurality of output buffers such that when the first output buffer portion of the output buffer has no image data, reading of image data from the second output buffer portion is started, and image data read from the memory region is written into the first output buffer portion, and when the second output buffer portion has no image data, reading of image data from the first output buffer portion is started, and image data read from the memory region is written into the second output buffer portion.
0046In still another embodiment of the invention, a data rate at which image data is written into the output buffer from the memory region is selected to be different from a data rate at which image data is read from the output buffer.
0047In still another embodiment of the invention, the data bus means includes: a first data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the digital signal processing section; a second data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the image memory; a third data bus portion for electrically connecting a data output terminal of the digital signal processing section with a data input terminal of the image memory; a fourth data bus portion for electrically connecting a data output terminal of the image memory with a data input terminal of the digital signal processing section; a fifth data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the output section; a sixth data bus portion for electrically connecting a data output terminal of the digital signal processing section with a data input terminal of the output section; and a seventh data bus portion for electrically connecting a data output terminal of the image memory with a data input terminal of the output section.
0048In still another embodiment of the invention, all of the first to seventh data bus portions are formed on a semiconductor chip.
0049In still another embodiment of the invention, the control moans includes: program data holding means for holding program data defining operation modes for the input section, the digital signal processing section, the image memory, the output section, and the data bus means; and program data distribution means for receiving program data and distributing the program data into the program data holding means.
0050According to still another aspect of the invention, an image processing method for processing image data by the image processing device is provided. The method includes the steps of: receiving image data corresponding to one video signal by the input section; performing a first processing for the image data output from the input section to the digital signal processing section by the digital signal processing section; writing the image data output from the digital signal processing section after the first processing into the image memory to temporarily store the image data in the image memory; and receiving the image data read from the image memory by the digital signal processing section again to perform a second processing.
0051In one embodiment of the invention, the image processing method further includes the steps of: writing the image data output from the digital signal processing section after the second processing into the image memory to temporarily store the image data in the image memory; and receiving the image data read from the image memory by the digital signal proceasing section again to perform a third processing.
0052Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving image data corresponding to one video signal by the input section; writing the image data output from the input section into the image memory to temporarily store the image data in the image memory; supplying the image data from the input section and the image data read from the image memory to the digital signal processing section in parallel, and performing a predetermined processing between these image data.
0053In one embodiment of the invention, the image data is read from two output ports of the image memory by delaying the image data by a predetermined delay amount and input in parallel into the digital signal processing section, and the predetermined processing is performed between the two units of image data from the image memory and the image data from the input section.
0054Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: writing only a portion of the image data corresponding to a portion of pixels for each scanning line and/or a portion of scanning lines for each field among the image data corresponding to one video signal into the image memory to temporarily store the portion of the image data in the image memory; and reading from the image memory the image data in the order in which the pixels and scanning lines have been written to the image memory.
0055Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: writing image data corresponding to one video signal into the image memory to temporarily store the image data in the image memory; reading the image data from the image memory intermittently for each pixel or for each scanning line; and supplying the image data read from the image memory to the digital signal processing section, and interpolating image data at positions of pixels or scanning lines which had been skipped in the intermittent reading of the image memory.
0056Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving first and second image data units corresponding to two image signals which ore asynchronous from each other by the input section; writing the first image data unit output from the input section into the image memory to temporarily store the first image data in the image memory; supplying the second image data unit output from the input section to the digital signal processing section, and simultaneously reading the first image data unit from the image memory to supply to the digital signal processing section in synchronization with the supply of the second image data unit; and performing a predetermined processing for the first and second image data units input in synchronization with each other by the digital signal processing section.
0057Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving first and second image data units corresponding to two image signals which are asynchronous from each other by the input section; supplying the first image data unit output from the input section to the digital signal processing section to perform a predetermined processing; supplying the first image data unit output from the digital signal processing section to the image memory, and simultaneously supplying the second image data unit output from the input section to the image memory; and reading the first and second image data units from the image memory in synchronization with a synchronous signal other than synchronous signals relating to the first and second image data units.
0058Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving image data corresponding to one video signal by the input section; supplying a former half of the image data output from the input section to the digital signal processing section during a first period; writing the image data output from the input section into the image memory and reading the written image data after a predetermined delay time; and supplying a latter half of the image data output from the image memory to the digital signal processing section during a second period.
0059In one embodiment of the invention, the image processing method further includes the steps of: writing the former half of the image data output from the digital signal processing section into the image memory and reading the written image data after a predetermined delay time; outputting the former half of the image data read from the image memory from the output section; outputting the latter half of the image data from the digital signal processing section; and outputting the latter half of the image data output from the digital signal processing section from the output section in succession with the former half of the image data.
0060In another embodiment of the invention, the image processing method further includes the steps of: adding a first overlap portion which overlaps a head portion of the latter half of the image data by a predetermined number of pixels to a tail portion of the former half of the image data input into the digital signal processing section during the first period; adding a second overlap portion which overlaps a tail portion of the former half of the image data by a predetermined number of pixels to a head portion of the latter half of the image data input into the digital signal processing section during the second period; and removing the first end second overlap portions at a stage of outputting the image data outside from the output section.
0061Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving image date corresponding to one video signal by the input section end performing a low-pass filtering processing by the input section; and supplying the image data output from the input section to the digital signal processing section or the image memory, and performing a decimation processing for information compression of the image data.
0062According to still another aspect of the invention, a video signal processing device is provided. The video signal processing device includes: a first converter for receiving a plurality of video data units corresponding to a plurality of pixels connected to one scanning line as an input video signal, and converting the plurality of video data units into a plurality of video data sets, each of the plurality of video data sets including at least two video data units; an operator for processing the plurality of video data sets and outputting a plurality of processed video data sets; and a second converter for converting the plurality of processed video data sets into a plurality of processed video data units corresponding to a plurality of pixels connected to one scanning line, and outputting the plurality of processed video data units as an output video signal.
0063In one embodiment of the invention, the operator includes a plurality of processor elements, and each of the plurality of processor elements processes at least two image data units included in each of the plurality of video data sets.
0064Thus, the invention described herein makes possible the advantages of (1) providing a television receiver and a video signal processing device which are adaptive to a variety of broadcasting methods without increasing the circuit size and the cost, (2) providing image processing device/method with a small-size circuit configuration which can be used for a variety of applications, (3) providing image processing device/method which effectively utilize resources inside the device to perform efficient high-level image processing, and (4) providing an video signal processing device with a reduced cost.
0065These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
0066<ul id="ul0001" list-style="none"><li>Figure <b>1</b> is a block diagram illustrating a configuration of a television receiver of Example 1 according to the present invention.</li><li>Figure <b>2</b> is a block diagram illustrating a configuration of a television receiver of Example 2 according to the present invention.</li><li>Figure <b>3</b> is a flowchart showing a procedure of a format conversion processing and a screen synthesization processing performed by an image processor of the television receiver of Example 2.</li><li>Figure <b>4</b> is a flowchart showing another procedure of the format conversion processing and the screen synthesization processing performed by the image processor of the television receiver of Example 2.</li><li>Figure <b>5</b> is a block diagram illustrating a configuration of a video signal processing device of Example 3 according to the present invention.</li><li>Figure <b>6</b> is a block diagram illustrating a configuration of a video signal processing device of Example 4 according to the present invention.</li><li>Figure <b>7</b> is a block diagram illustrating an overall circuit configuration of an image processor of Example 5 according to the present invention.</li><li>Figure <b>8</b> is a block diagram illustrating an exemplary configuration of data buses of the image processor of Example 5.</li><li>Figure <b>9</b> is a block diagram illustrating an exemplary circuit configuration of an input section of the image processor of Example 5.</li><li>Figure <b>10</b> is a block diagram illustrating an exemplary configuration of a scan video processor (SVP) of the image processor of Example 5.</li><li>Figure <b>11</b> is a block diagram illustrating an exemplary configuration of an image memory of the image processor of Example 5.</li><li>Figures <b>12A</b> to <b>12E</b> are views for describing the write/read operations of an input buffer of the image memory of the image processor of Example 5.</li><li>Figures <b>13A</b> to <b>13E</b> are views for describing the write/read operations of an output buffer of the image memory of the image processor of Example 5.</li><li>Figure <b>14</b> is a view illustrating an exemplary pointer control in the image memory of the image processor of Example 5.</li><li>Figure <b>15</b> is a block diagram illustrating an exemplary configuration of & timing control unit of the image processor of Example 5.</li><li>Figure <b>16</b> is a block diagram illustrating a functional configuration of a moving-image real-time processing system which can be realized by the image processor of Example 5.</li><li>Figure <b>17</b> is a view illustrating another exemplary pointer control in the image memory of the image processor of Example 5.</li><li>Figure <b>18</b> is a view illustrating an exemplary pixel pattern obtained by an image processing method in the image processor of Example 5.</li><li>Figure <b>19</b> is a timing chart for describing another image processing method in the image processor of Example 5.</li><li>Figure <b>20</b> is a view illustrating an exemplary pixel pattern obtained by the method of Figure <b>19</b>.</li><li>Figure <b>21</b> is a block diagram illustrating one exemplary application of the image processor of Example 5.</li><li>Figure <b>22</b> is a timing chart for describing still another image processing method in the image processor of Example 5.</li><li>Figure <b>23</b> is a view illustrating means and function for realizing the method of Figure <b>22</b>.</li><li>Figure <b>24</b> is a block diagram illustrating a configuration of a main portion of a television receiver using the image processor of Example 5.</li><li>Figure <b>25</b> is a block diagram illustrating a configuration of a main portion of another television receiver using the image processor of Example 5.</li><li>Figure <b>26</b> is a block diagram illustrating a configuration of a conventional image processing device.</li><li>Figure <b>27</b> is a block diagram illustrating a configuration of a video signal processor of Example 6 according to the present invention.</li><li>Figure <b>28</b> is a timing chart showing the operations of a data input register, an operator, and a data output register in an LPF processing in Example 6.</li><li>Figures <b>29A</b> to <b>29E</b> are timing charts showing the operations of a serial-parallel converter and the data input register in Example 6.</li><li>Figure <b>30</b> is a view diagrammatically illustrating the LPF processing performed by the operator in Example 6.</li><li>Figures <b>31A</b> to <b>31E</b> are timing charts showing the operations of a parallel-serial converter and the data output register in Example 6.</li><li>Figure <b>32</b> is a block diagram illustrating a configuration of a conventional video signal processor.</li><li>Figure <b>33</b> is a timing chart showing the operations of a data input register, an operator, and a data output register of the conventional video signal processor in the LPF processing.</li><li>Figure <b>34</b> is a view diagrammatically illustrating the LPF processing performed by the operator of the conventional video signal processor.</li></ul>
DESCRIPTION OF THE PREFERRED EMBODIMENTS
0067Hereinbelow, the present invention will be described by way of example with reference to the accompanying drawings.
(Example 1)
0068Figure <b>1</b> illustrates a configuration of a television receiver <b>1200</b> of Example 1 according to the present invention.
0069The television receiver <b>1200</b> of this example includes a display device <b>1050</b> capable of displaying a video signal having a predetermined display format. The predetermined display format is, for example, a format of 1125 horizontal scanning lines/interlace scanning.
0070The television receiver <b>1200</b> further includes a plurality of video signal sources <b>1210a</b>, <b>1210b</b>, <b>1210c</b>, <b>1210d</b> which output a plurality of video signals and a format conversion section <b>1100</b> which converts a video format of each of the plurality of video signals into the display format which is acceptable by the display device <b>1050.</b> The "video format" and the "display format" as used herein are defined to include the number of horizontal scanning lines, the aspect ratio, interlace scanning/non-interlace scanning, and the frequency of fields.
0071The video signal source <b>1210a</b> includes a V/UHF tuner <b>1001</b>, a VSB demodulator <b>1009</b>, a selection circuit <b>1012</b>, and an NTSC decoder <b>1015.</b> An NTSC broadcast signal sent via a ground wave is received by a V/UHF antenna (not shown). The NTSC broadcast signal received by the V/UHF antenna is supplied to the VSB demodulator <b>1009</b> via the V/UHF tuner <b>1001.</b> The VSB demodulator <b>1009</b> converts the NTSC broadcast signal into a base-band NTSC signal. The base-band NTSC signal is then supplied to the NTSC decoder <b>1015</b> via the selection circuit <b>1012.</b> The NTSC decoder <b>1015</b> decodes the base-band NTSC signal to output a RGB signal, which is supplied to the format conversion section <b>1100.</b> Thus, the RGB signal is supplied from the video signal source <b>1210a</b> to the format conversion section <b>1100.</b>
0072The video signal source <b>1210b</b> includes a BS tuner <b>1002</b>, an FM demodulator <b>1010</b>, and a MUSE decoder <b>1016.</b> A high-definition broadcast signal sent via a broadcasting satellite (BS) is received by a BS antenna (not shown). The high-definition broadcast signal received by the BS antenna is supplied to the FM demodulator <b>1010</b> via the BS tuner <b>1002.</b> The FM demodulator <b>1010</b> converts the high-definition broadcast signal into a base-band MUSE signal. The base-band MUSE signal is then supplied to the MUSE decoder <b>1016.</b> The MUSE decoder <b>1016</b> decodes the base-band MUSE signal to output a high-definition RGB signal, which is supplied to the format conversion section <b>1100.</b> Thus, the high-definition RGB signal is supplied from the video signal source <b>1210b</b> to the format conversion section <b>1100.</b>
0073The video signal source <b>1210c</b> includes a communication satellite (CS) tuner <b>1003</b>, a QPSK demodulator <b>1011</b>, and a digital decoder <b>1017.</b> A digital broadcast signal sent via a communications satellite is received by a CS antenna (not shown). The digital broadcast signal received by the CS antenna is supplied to the QPSK demodulator <b>1011</b> via the CS tuner <b>1003.</b> The QPSK demodulator <b>1011</b> converts the digital broadcast signal into a digital bit stream. The digital bit stream is then supplied to the digital decoder <b>1017.</b> The digital decoder <b>1017</b> decodes the digital bit stream in accordance with an MPEG2 method to output a RGB signal, which is supplied to the format conversion section <b>1100.</b> Thus, the RGB signal is supplied from the video signal source <b>1210c</b> to the format conversion section <b>1100.</b>
0074The video signal source <b>1210d</b> includes an input terminal <b>1022.</b> The television receiver <b>1200</b> is connected to a personal computer (PC) <b>1004</b> via the input terminal <b>1022.</b> A RGB signal output from the PC <b>1004</b> is supplied to the format conversion section <b>1100</b> via the input terminal <b>1022.</b> Thus, the RGB signal is supplied from the video signal source <b>1210d</b> to the format conversion section <b>1100.</b>
0075The RGB signals output from the video signal sources <b>1210a</b> and <b>1210c</b>, the high-definition RGB signal output from the video signal source <b>1210b</b>, and the RGB signal output from the video signal source <b>1210d</b> have different video formats from one another. For example, the RGB signals output from the video signal sources <b>1210a</b> and <b>1210c</b> have a video format of 525 horizontal scanning lines/interlace scanning. The high-definition RGB signal output from the video signal source <b>1210b</b> has a video format of 1125 horizontal scanning lines/interlace scanning. The RGB signal output from the video signal source <b>1210d</b> has a video format of VGA, SVGA, or the like.
0076The format conversion section <b>1100</b> includes a selection circuit <b>1030</b> which selects one of the plurality of video signals output from the plurality of video signal sources <b>1210a</b> to <b>1210d</b> and an image processor <b>1040</b> which converts the video format of the video signal selected by the selection circuit <b>1030</b> into a predetermined display format capable of being displayed by the display device <b>1050.</b> A general processor may be used in place of the image processor <b>1040.</b>
0077The selection circuit <b>1030</b> selects one of the plurality of video signals in accordance with a control signal output from a CPU <b>1020.</b> The video signal selected by the selection circuit <b>1030</b> is supplied to the image processor <b>1040.</b>
0078The image processor <b>1040</b> is a programmable real-time video signal processing device which performs a video signal processing in accordance with a program. The image processor <b>1040</b> reads a program corresponding to the format of the video signal selected by the selection circuit <b>1030</b> from a program memory <b>1045</b> in accordance with the control signal output from the CPU <b>1020</b>, to execute the program. This converts the format of the video signal selected by the selection circuit <b>1030</b> into a predetermined display format which can be displayed by the display device <b>1050.</b>
0079For example, when the RGB signal output from the NTSC decoder <b>1015</b> is selected by the selection circuit <b>1030</b>, the image processor <b>1040</b> receives a program for converting the video format of "525 horizontal scanning lines/interlace scanning" into a display format of "1125 horizontal scanning lines/interlace scanning" from the program memory <b>1045</b> under the control of the CPU <b>1020.</b> The image processor <b>1040</b> executes this format conversion program, resulting in providing the video signal of which format has been converted into the display format capable of being displayed by the display device <b>1050.</b> The video signal is supplied to the display device <b>1050</b> for display.
0080When the high-definition RGB signal output from the MUSE decoder <b>1016</b> is selected by the selection circuit <b>1030</b>, the image processor <b>1040</b> receives a program for allowing the high-definition RGB signal output from the MUSE decoder <b>1016</b> to pass therethrough without any processing from the program memory <b>1045</b> under the control of the CPU <b>1020.</b> This is because the video format of the high-definition RGB signal is the same as the display format capable of being displayed by the display device <b>1050</b>, thereby requiring no format conversion.
0081When the RGB signal output from the digital decoder <b>1017</b> is selected by the selection circuit <b>1030</b>, The processing performed by the image processor <b>1040</b> is similar to that performed when the RGB signal output from the NTSC decoder <b>1015</b> is selected by the selection circuit <b>1030.</b> That is, the video format of "525 horizontal scanning lines/interlace scanning" is converted into the display format of "1125 horizontal scanning lines/interlace scanning". As a result, the video signal of which format has been converted into the display format capable of being displayed by the display device <b>1050</b> is provided as the output of the image processor <b>1040.</b> The video signal is supplied to the display device <b>1050</b> for display.
0082When the RGB signal input into the input terminal <b>1022</b> is selected by the selection circuit <b>1030</b>, the image processor <b>1040</b> receives a program for converting the video format of the input RGB signal (e.g., VGA, SVGA) into the display format of "1125 horizontal scanning lines/interlace scanning" from the program memory <b>1045</b> under the control of the CPU <b>1020.</b> The image processor <b>1040</b> executes this format conversion program, resulting in providing the video signal of which format has been converted into the display format capable of being displayed by the display device <b>1050</b> as the output of the image processor <b>1040.</b> The video signal is supplied to the display device <b>1050</b> for display.
0083As described above, the CPU <b>1020</b> controls the selection circuit <b>1030</b> and the image processor <b>1040.</b> The control signals output from the CPU <b>1020</b> are supplied to the selection circuit <b>1030</b> and the image processor <b>1040</b> via system control buses. The values of the control signals are determined in accordance with user operation information input via a control input terminal <b>1021.</b> The user operation information includes a channel selection signal.
0084The CPU <b>1020</b> also controls the tuning of the V/UHF tuner <b>1001</b>, the BS tuner <b>1002</b>, and the CS tuner <b>1003.</b>
0085The CPU <b>1020</b> further controls the selection circuit <b>1012</b> which selects the input into the NTSC decoder <b>1015.</b> The selection circuit <b>1012</b> is controlled so as to connect the output of the VSB demodulator <b>1009</b> to the NTSC decoder <b>1015</b> when it receives the NTSC broadcast signal via a ground wave, or connect the output of the FM demodulator <b>1010</b> to the NTSC decoder <b>1015</b> when it receives the NTSC broadcast signal via a BS.
0086Thus, according to the television receiver <b>1200</b>, video signals having different video formats can be converted into video signals having a predetermined display format by executing format conversion programs corresponding to the respective formats of the video signals. As a result, one television receiver becomes adaptive to a variety of broadcasting methods without increasing the circuit size and the cost.
0087In particular, a scan-line video processor (SVP) type image processor described in Japanese Laid-Open Publication No. 3-258179 can be preferably used as the image processor <b>1040.</b> The SVP type image processor is constructed to process a scanning-line type signal for each scanning line, which is suitable for the format conversion processing such as the conversion of the number of scanning lines.
0088However, the SVP type image processor is not suitable for the synchronous processing in the decoding of the NTSC signal. Further, the SVP type image processor is not suitable to perform the processing such as inverse discrete cosine transformation or perform error correction in the decoding of the digital broadcast signal. In Example 1, the decoders <b>1015</b> to <b>1017</b> for decoding video signals and the format conversion section <b>1100</b> including the image processor <b>1040</b> are separately disposed so that only the scanning-line type signal can be supplied to the image processor <b>1040.</b> With this configuration, the image processor <b>1040</b> is optimized to obtain a high cost performance.
(Example 2)
0089Figure <b>2</b> illustrates a configuration of a television receiver <b>1220</b> of Example 2 according to the present invention. The same components as those shown in Figure <b>1</b> are denoted by the same reference numerals, and the descriptions thereof are omitted here.
0090A format conversion section <b>1100</b> includes: a selection circuit <b>1031</b> which selects two of a plurality of video signals output from a plurality of video signal sources <b>1210a</b> to <b>1210d</b>; and an image processor <b>1041</b> which converts the formats of the two video signals selected by the selection circuit <b>1031</b> into a predetermined display format capable of being displayed by a display device <b>1050</b> in accordance with a program, and processes the two video signal so that synthesized images can be displayed on the display device <b>1050.</b>
0091The selection circuit <b>1031</b> selects two of the plurality of video signals in accordance with a control signal output from a CPU <b>1020.</b> The two video signals selected by the selection circuit <b>1031</b> are supplied to the image processor <b>1041.</b> The two video signals selected by the selection circuit <b>1031</b> may be an arbitrary combination of two of the plurality of video signals.
0092The image processor <b>1041</b> reads programs corresponding to the formats of the two video signals selected by the selection circuit <b>1031</b> from the program memory <b>1045</b> in accordance with a control signal output from the CPU <b>1020</b>, to execute the programs. This converts the formats of the two video signals selected by the selection circuit <b>1031</b> into a predetermined display format which can be displayed by the display device <b>1050.</b> Moreover, the image processor <b>1041</b> synthesizes the two video signals selected by the selection circuits <b>1031</b> in accordance with a synthesization program, so that synthesized images are displayed on the display device <b>1050.</b>
0093Figure <b>3</b> shows a procedure of the format conversion processing and the screen synthesization processing performed by the image processor <b>1041.</b>
0094In the procedure shown in Figure <b>3</b>, it is assumed that the RGB signal (<b>A</b>) output from the NTSC decoder <b>1015</b> and the high-definition RGB signal (<b>B</b>) output from the MUSE decoder <b>1016</b> have been selected by the selection circuit <b>1031.</b> Under this situation, the image processor <b>1041</b> converts the format of the RGB signal (<b>A</b>) (525 horizontal scanning lines/interlace scanning) into a predetermined display format (1125 horizontal scanning lines/interlace scanning) (step <b>S1031</b>). Subsequently, the image processor <b>1041</b> synthesizes a format-converted RGB signal (<b>A'</b>) and the high-definition RGB signal (<b>B</b>) in accordance with a synthesization program (step <b>S1032</b>). As a result, a synthesized video signal (<b>C</b>) having a display format of 1125 horizontal scanning lines/interlace scanning is obtained. The format conversion of the high-definition RGB signal (<b>B</b>) is not necessary since the signal (<b>B</b>) has the same format as the display format.
0095Figure <b>4</b> shows another procedure of the format conversion processing and the screen synthesization processing performed by the image processor <b>1041.</b>
0096In the procedure shown in Figure <b>4</b>, it is assumed that the RGB signal (<b>A</b>) output from the NTSC decoder <b>1015</b> and the high-definition RGB signal (<b>B</b>) output from the MUSE decoder <b>1016</b> are selected by the selection circuit <b>1031.</b> Under this situation, the image processor <b>1041</b> converts the format of the high-definition RGB signal (<b>B</b>) (1125 horizontal scanning lines/interlace scanning) into the format of the RGB signal (<b>A</b>) (525 horizontal scanning lines/interlace scanning) (step <b>S1041</b>). Subsequently, the image processor <b>1041</b> synthesizes a format-converted high-definition RGB signal (<b>B'</b>) and the RGB signal (<b>A</b>) in accordance with a synthesization program (step <b>S1042</b>). As a result, a synthesized video signal (<b>C</b>) having a display format of 525 horizontal scanning lines/interlace scanning is obtained. Thereafter, the image processor <b>1041</b> converts the format of the synthesized video signal (<b>C</b>) (525 horizontal scanning lines/interlace scanning) into a predetermined display format (1125 horizontal scanning lines/interlace scanning) (step <b>S1043</b>). As a result, a synthesized video signal (<b>D</b>) having a display format of 1125 horizontal scanning lines/interlace scanning is obtained.
0097The screen synthesization processing is performed by use of a field memory (not shown). The procedure shown in Figure <b>4</b> is advantageous over the procedure shown in Figure <b>3</b> in that the data amount stored in the field memory is small. More specifically, in the procedure shown in Figure <b>3</b>, a data amount corresponding to one field in the format of 1125 horizontal scanning lines/interlace scanning must be stored in the field memory. On the other hand, in the procedure shown in Figure <b>4</b>, only a data amount corresponding to one field in the format of 525 horizontal scanning lines/interlace scanning is required to be stored in the field memory. In the procedure shown in Figure <b>4</b>, however, the image quality is degraded, compared with the procedure shown in Figure <b>3</b>, because the format of 1125 horizontal scanning lines/interlace scanning is once converted into the format of 525 horizontal scanning lines/interlace scanning.
0098As described above, the procedures shown in Figures <b>3</b> and <b>4</b> have their merits and demerits. Accordingly, which procedure should be employed, the procedure shown in Figure <b>3</b> or the procedure shown in Figure <b>4</b>, is determined in consideration of the cost of the field memory and the image quality required.
0099Thus, according to the television receiver <b>1220</b> of this example, video signals having different video formats can be converted into video signals having a predetermined display format by executing format conversion programs corresponding to the respective formats of the video signals. As a result, one television receiver becomes adaptive to a variety of broadcasting methods without increasing the circuit size and the cost. Moreover, synthesized images can be displayed on the display device <b>1050</b> by synthesizing a plurality of video signals.
0100Although two video signals are selected from a plurality of video signals in this example, the number of video signals selected is not limited to two. The present invention also allows for selecting more than two video signals from a plurality of video signals and performing the format conversion processing and the synthesizing processing for the more than two video signals selected.
(Example 3)
0101Figure <b>5</b> illustrates a configuration of a video signal processing device <b>1300</b> of Example 3 according to the present invention. The video signal processing device <b>1300</b> includes the format conversion section <b>1100</b> of the television receiver <b>1200</b> shown in Figure <b>1.</b> The CPU <b>1020</b> and the control input terminal <b>1021</b> for system control also constitute the video signal processing device <b>1300.</b>
0102The video signal proceasing device <b>1300</b> includes a plurality of video signal input terminals <b>1101</b>, <b>1102</b>, <b>1103</b>, <b>1104</b> for receiving a plurality of video signals. The plurality of video signals typically have different video formats from one another. For example, the RGB signal output from the NTSC decoder <b>1015</b> (Figure <b>1</b>) is input into the video signal input terminal <b>1101</b>, and the high-definition RGB signal output from the MUSE decoder <b>1016</b> (Figure <b>1</b>) is input into the video signal input terminal <b>1102.</b>
0103The plurality of video signals input via the plurality of video signal input terminals <b>1101</b> to <b>1104</b> are supplied to the format conversion section <b>1100.</b>
0104The format conversion section <b>1100</b> includes the selection circuit <b>1030</b> and the image processor <b>1040.</b> The configurations and operations of the selection circuit <b>1030</b> and the image processor <b>1040</b> are as described in Example 1.
0105Video signals of which formats have been converted by the image processor <b>1040</b> are output from the video signal processing device <b>1300</b> via a video signal output terminal <b>1110.</b>
0106Thus, the video signal processing device <b>1300</b> is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost.
0107The video signal processing device <b>1300</b> shown in Figure <b>5</b> is applicable to a large-screen projection type display system. In recent years, an increasing number of large-screen projection type display systems have been installed in public facilities and the like. Such a system is basically constructed in combination of a projection type display device and a signal reproduction device. The video signal processing device <b>1300</b> of this example may be used as the signal reproduction device. In such an application, the video signal processing device <b>1300</b> converts the formats of video signals input via the video signal input terminals into a predetermined display format, and supplies format-converted video signals to the projection type display device. The format conversion is performed by executing programs corresponding to the formats of the video signals. This realizes a system which is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost. Additionally, the resultant system can programmably respond to a change in the format of an input video signal and a change in the projection type display device. Thus, the video signal processing circuit <b>1300</b> is highly versatile.
(Example 4)
0108Figure <b>6</b> illustrates a configuration of a video signal processing device <b>1320</b> of Example 4 according to the present invention. The video signal processing device <b>1320</b> includes the format conversion section <b>1100</b> of the television receiver <b>1220</b> shown in Figure <b>2</b>. The CPU <b>1020</b> and the control input terminal <b>1021</b> for system control also constitute the video signal processing device <b>1320.</b>
0109The video signal processing device <b>1320</b> includes a plurality of video signal input terminals <b>1101</b> to <b>1104</b> for receiving a plurality of video signals. The plurality of video signals have different video formats from one another. For example, the RGB signal output from the NTSC decoder <b>1015</b> (Figure <b>1</b>) is input into the video signal input terminal <b>1101</b>, and the high-definition RGB signal output from the MUSE decoder <b>1016</b> (Figure <b>1</b>) is input into the video signal input terminal <b>1102.</b>
0110The plurality of video signals input via the plurality of video signal input terminals <b>1101</b> to <b>1104</b> are supplied to the format conversion section <b>1100.</b>
0111The format conversion section <b>1100</b> includes the selection circuit <b>1031</b>, the image processor <b>1041</b>, and the program memory <b>1045.</b> The configurations and operations of the selection circuit <b>1031</b>, the image processor <b>1041</b>, and the program memory <b>1045</b> are as described in Example 2.
0112Video signals of which formats have been converted by the image processor <b>1041</b> are output from the video signal processing device <b>1320</b> via a video signal output terminal <b>1110.</b>
0113Thus, the video signal processing device <b>1320</b> is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost.
0114The video signal processing device <b>1320</b> shown in Figure <b>6</b> is applicable to a large-screen projection type display system for the same reason as that described in Example 3.
0115Thus, in Examples 1 and 2 above, the television receiver according to the present invention selects one of a plurality of video signals output from a plurality of video signal sources. The format of the selected video signal is converted into a display format capable of being displayed by the display device in accordance with a relevant program. Thus, even if the plurality of video signals output from the plurality of video signal sources have different formats from one another, the plurality of video signals can be converted into a predetermined display format by executing programs corresponding to the respective formats. As a result, a television receiver which is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost is realized.
0116Specifically with respect to Example 2 above, the television receiver selects at least two of a plurality of video signals output from a plurality of video signal sources. The formats of the selected at least two video signals are converted into a predetermined display format capable of being displayed by the display device in accordance with relevant programs. Additionally, the selected at least two video signals are processed so that synthesized images are displayed on the display device. As a result, a television receiver which is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost and which also displays synthesized images on the screen of the display device is realized.
0117In Examples 3 and 4 above, the video signal processing device according to the present invention selects one of a plurality of video signals input via a plurality of video signal input terminals. The format of the selected video signal is converted into a predetermined display format in accordance with a relevant program. Thus, even if the plurality of video signals input via the plurality of video signal input terminals have different formats from one another, the plurality of video signals can be converted into a predetermined display format by executing programs corresponding to the respective formats. As a result, a video signal processing device which is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost is realized.
0118Specifically with respect to Example 4 above, the video signal processing device selects at least two of a plurality of video signals input via a plurality of video signal input terminals. The formats of the selected at least two video signals are converted into a predetermined display format in accordance with relevant programs. Additionally, the selected at least two video signals can be synthesized. As a result, a video signal processing device which is adaptive to a variety of broadcasting methods without increasing the circuit size and the cost and outputs a synthesized video signal is realized.
(Example 5)
0119Figure <b>7</b> illustrates a circuit configuration of an image processor of Example 5 according to the present invention.
0120The image processor of this example includes: an input section <b>2040</b> which receives a digital video signal from outside as image data to be processed; a scan-line video processor (SVP) <b>2014</b> which receives, processes, and outputs the image data for each scanning line; an image memory <b>2050</b> in/from which the image data is written/read for each scanning line; on output section <b>2070</b> which outputs processed image data outside; and data buses <b>2072</b> which connect the input section <b>2040</b>, the SVP <b>2014</b>, the image memory <b>2050</b>, and the output section <b>2070</b> with one another. Each of the data buses <b>2072</b> may, for example, be formed on one semiconductor chip.
0121The image processor of this example also includes: a program memory <b>2010</b> made of a RAM which holds a program for the SVP <b>2014</b>; and an instruction generation circuit (IG) <b>2012</b> which retrieves instructions one by one from the program memory <b>2010</b> and supplies a control signal such as a microinstruction corresponding to the retrieved instruction to the SVP <b>2014.</b> These components are provided to enable the SVP <b>2014</b> to operate as a single-instruction multiple-data (SIMD) type digital signal processing section.
0122The image processor further includes a timing control unit (TCU) <b>2074</b> serving as a control means which supplies necessary timing control signals to the input section <b>2040</b>, the SVP <b>2014</b>, the image memory <b>2050</b>, the output section <b>2070</b>, and the IG <b>2012</b>.
0123The image processor also includes a ROM loader <b>2076</b> and on inter IC-bus (I<sup>2</sup>C bus) interface circuit <b>2078</b>, which serve to distribute external program data to program data holding portions (memories, registers, etc.) disposed sporadically in the components of the image processor, i.e., the input section <b>2040</b>, the SIMD type digital signal processing section (the program memory <b>2010</b>, the IG <b>2012</b>, and the SVP <b>2014</b>), the image memory <b>2050</b>, and the output section <b>2070</b>, via an internal bus <b>2080</b>. A clock circuit (not shown) composed of a PLL circuit, for example, for supplying necessary clocks to the respective components of the image processor is also included.
0124The program data holding portion of the SIMD type digital signal processing section is the program memory <b>2010</b>. The I<sup>2</sup>C bus interface circuit <b>2078</b> is connected to an external controller (not shown) under the I<sup>2</sup>C bus standard, so as to receive program data from the controller by serial transmission, for example, and after converting the received data into parallel data, transfer a relevant portion of the converted program data to a designated destination (program data holding portion).
0125The ROM loader <b>2076</b> is connected to an external ROM (not shown). Upon receipt of a desired program number from the external controller via the I<sup>2</sup>C bus interface circuit <b>2078</b>, the ROM loader <b>2076</b> reads data of a predetermined application program corresponding to the program number, and loads the data to the program data holding portions of the respective components. Although the external ROM is required for the ROM loader <b>2076</b>, this data distribution method is advantageous in that the program data can be distributed in a significantly short time compared with the method where the program data is distributed to the respective portions by an external controller via the I<sup>2</sup>C bus interface circuit <b>2078</b>.
0126Figure <b>8</b> illustrates a concrete example of the data bus arrangement of the image processor shown in Figure <b>7</b>. As shown in Figure <b>8,</b> multiplexers <b>2082</b>, <b>2084</b>, and <b>2086</b> are disposed at stages preceding the input terminals of the SVP <b>2014</b>, the image memory <b>2050</b>, and the output section <b>2070</b>, respectively.
0127In the illustrated example, the input section <b>2040</b> is configured to be able to receive up to two sets of 16-bit digital video signals, for example, simultaneously from outside as image data VS to be processed by the processor. The SVP <b>2014</b> includes input ports for receiving up to three digital video signals (image data units) simultaneously and output ports for outputting up to three image data units simultaneously. The image memory <b>2050</b> includes three input ports/input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, and <b>SDI</b><sub><b>C</b></sub> for receiving up to three image data units simultaneously and three output ports/output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, and <b>SDO</b><sub><b>C</b></sub> for outputting up to three image data units simultaneously.
0128Two-channel output ports of the input section <b>2040</b> are connected to input terminals of the first multiplexer <b>2082</b> and also connected to input terminals of the second multiplexer <b>2084.</b> The first and second output ports of the three-channel output ports of the SVP <b>2014</b> are connected to the input terminals of the second multiplexer <b>2084</b>, while the first and third output ports thereof are connected to input terminals of the third multiplexer <b>2086.</b> The first, second, and third output ports of the three-channel output ports of the image memory <b>2050</b> are connected to the input terminals of the first multiplexer <b>2082</b>, while the first and second output ports thereof are connected to the input terminals of the third multiplexer <b>2086.</b>
0129The three-channel output terminals of the first multiplexer <b>2082</b> are connected to the input ports of the SVP <b>2014.</b> The three-channel output terminals of the second multiplexer <b>2084</b> are connected to the input ports of the image memory <b>2050.</b> The two-channel output terminals of the third multiplexer <b>2086</b> are connected to the input ports of the output section <b>2070.</b>
0130With the data bus configuration described above, the input ports and the outputs ports of the SVP <b>2014</b> and the image memory <b>2050</b> are connected with each other in the crossing relationship via the multiplexers <b>2082</b> and <b>2084.</b> The switching in each of the multiplexers <b>2082</b>, <b>2084</b>, and <b>2086</b> is controlled by a timing control signal supplied from the TCU <b>2074</b> (Figure <b>7</b>).
0131Figure <b>9</b> illustrates an exemplary circuit configuration of the input section <b>2040.</b> In the illustrated example, the input section <b>2040</b> includes four input portions <b>2040A</b>, <b>2040B</b>, <b>2040C</b>, and <b>2040D</b> corresponding to four signals <b>VS</b><sub><b>1Y</b></sub>, <b>VS</b><sub><b>1C</b></sub>, <b>VS</b><sub><b>2Y</b></sub>, <b>VS</b><sub><b>2C</b></sub>, i.e., a luminance signal (<b>Y</b>) and a color signal (<b>C</b>) for each of the two series of input video signals. Each input portion includes a buffer <b>2042</b>, a filter <b>2044</b>, a multiplexer <b>2046</b>, and a setting value register <b>2048.</b> Each input image data unit is first input into the buffer <b>2042.</b> Then, the image data unit is supplied directly to the multiplexer <b>2046</b> to be output outside or sent to the filter <b>2044</b> to be subjected to low-pass filtering for band limit, for example, before being supplied to the multiplexer <b>2046</b> to be output outside, depending on the switching position of the multiplexer <b>2046.</b>
0132The above switching of the multiplexer <b>2046</b> and the filtering of the filter <b>2044</b> are controlled by setting values (i.e., program data <b>PD</b> and a timing control signal <b>TC</b> supplied from the TCU <b>2074</b>) loaded into the setting value register <b>2048</b> of the relevant input portion from the ROM loader <b>2076</b> or the I<sup>2</sup>C bus interface circuit <b>2078</b> via the internal bus <b>2080</b> as described above.
0133Referring back to Figures <b>7</b> and <b>8</b>, the SVP <b>2014</b> includes a three-layer structure composed of a data input register (DIR) <b>2016</b>, a processing portion <b>2018</b>, and a data output register (DOR) <b>2020.</b>
0134Figure <b>10</b> illustrates an exemplary internal configuration of the SVP <b>2014.</b> The DIR <b>2016</b> operates in accordance with a timing control signal from the TCU <b>2074</b>, a clock from the clock circuit, and an address (<b>ADDRESS</b>) from the IG <b>2012</b>, and receives three channels (e.g., 48 bits) of image data units <b>D</b><sub><b>1</b></sub> to <b>D</b><sub><b>N</b></sub> for each scanning line repeatedly.
0135The processing portion <b>2018</b> is composed of processing elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub> (Figure <b>7</b>) arranged in parallel, the number of which is equal to the number N of pixels connected to one horizontal scanning line (e.g., 864). The processing elements <b>PE</b><sub><b>1</b></sub>, <b>PE</b><sub><b>2</b></sub>, ..., <b>PE</b><sub><b>N</b></sub> operate in parallel in accordance with the address (<b>ADDRESS</b>) and a microinstruction (<b>MICROINSTRUCTION</b>) from the IG <b>2012</b> and a clock from the clock circuit, and perform the same image processing operation for the corresponding pixel data units <b>D</b><sub><b>1</b></sub><b>, D</b><sub><b>2</b></sub><b>, ..., D</b><sub><b>N</b></sub><b>.</b> within one horizontal scanning period.
0136The DOR <b>2020</b> operates in accordance with a control signal from the TCU <b>2074</b>, a clock from the clock circuit, and an address (<b>ADDRESS</b>) from the IG <b>2012</b>, and outputs data units of the operation results from the processing elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub> as three channels at maximum of image data units <b>D</b><sub><b>1</b></sub><b>'</b> to <b>D</b><sub><b>N</b></sub><b>'</b> for each scanning line.
0137The clocks supplied to the DIR <b>2016</b>, the processing portion <b>2018</b>, and the DOR <b>2020</b> may be asynchronous from one another. Each of the data transfer from the DIR <b>2016</b> to the processing portion <b>2018</b> and the data transfer from the processing portion <b>2018</b> to the DOR <b>2020</b> is performed within one horizontal blanking period.
0138Thus, the data input, the parallel operation, and the data output for pixel data units corresponding to one horizontal scanning line are performed by the DIR <b>2016</b>, the processing portion <b>2018</b>, and the DOR <b>2020</b>, respectively. Each of these processes are performed asynchronously and in parallel in a pipeline manner, to realize real-time image processing.
0139The operations of the respective portions of the SVP <b>2014</b> will be briefly described with reference to Figure <b>10</b>. As described above, the operations of the respective portions of the SVP <b>2014</b> are controlled by the addresses and microinstructions from the IG <b>2012</b>, the timing control signal from the TCU <b>2074</b>, the clocks from the clock circuits, and the like.
0140Referring to Figure <b>10</b>, the DIR <b>2016</b> has a memory capacity capable of storing up to three channels of the input image data units <b>VS</b> (<b>D</b><sub><b>1</b></sub> to <b>D</b><sub><b>N</b></sub>) for one line, and is blocked for each pixel. During the transfer of the input image data units <b>D</b><sub><b>1</b></sub> to <b>D</b><sub><b>N</b></sub> inside the DIR <b>2016</b>, the image data units <b>D</b><sub><b>K-2</b></sub>, <b>D</b><sub><b>K-1</b></sub>, <b>D</b><sub><b>K</b></sub>, <b>D</b><sub><b>K+1</b></sub>, <b>D</b><sub><b>K+2</b></sub><b>, ...</b> are received by corresponding register groups of blocks <b>K-2, K-1</b>, <b>K</b>, <b>K+1</b>, <b>K+2, ...</b> of the DIR <b>2016</b> one by one.
0141Each processing element <b>PE</b><sub><b>K</b></sub> of the processing portion <b>2018</b> includes: a pair of register files <b>RF</b><sub><b>0</b></sub> and <b>RF</b><sub><b>1</b></sub>; a 1-bit arithmetic logic unit (ALU) <b>2024</b>; a plurality of (e.g., four) working registers (WRs) (M, A, B, C) <b>2026</b>; and a left/right (L/R) communication portion (LRCOM) <b>2028</b> which exchanges data with a plurality of left and right adjacent (e.g., four each) processing elements (<b>PE</b><sub><b>K-4</b></sub>, <b>PE</b><sub><b>K-3</b></sub>, <b>PE</b><sub><b>K-2</b></sub>, <b>PE</b><sub><b>K-1</b></sub>, <b>PE</b><sub><b>K+1</b></sub>, <b>PE</b><sub><b>K+2</b></sub>, <b>PE</b><sub><b>K+3</b></sub>, <b>PE</b><sub><b>K+4</b></sub>).
0142The register file <b>RF</b><sub><b>0</b></sub> is connected to the register groups of the corresponding block of the DIR <b>2016</b>, while the register file <b>RF</b><sub><b>1</b></sub> is connected to register groups of the corresponding block of the DOR <b>2020.</b> One-bit data read from one or both of the register files <b>RF</b><sub><b>0</b></sub> and <b>RF</b><sub><b>1</b></sub> is supplied to either of the working registers (M, A, B, C) <b>2026</b> and also supplied to the eight left and right adjacent processing elements (<b>PE</b><sub><b>K-4</b></sub>, <b>PE</b><sub><b>K-3</b></sub>, <b>PE</b><sub><b>K-2</b></sub>, <b>PE</b><sub><b>K-1</b></sub>, <b>PE</b><sub><b>K+1</b></sub>, <b>PE</b><sub><b>K+2</b></sub>, <b>PE</b><sub><b>K+3</b></sub>, <b>PE</b><sub><b>K+4</b></sub>) via a multiplexer <b>2030</b> and a latch circuit <b>2032</b> of the L/R communication portion <b>2028.</b>
0143Simultaneously with the above operation, data units from the left and right adjacent processing elements (<b>PE</b><sub><b>K-4</b></sub>, <b>PE</b><sub><b>K-3</b></sub>, <b>PE</b><sub><b>K-2</b></sub>, <b>PE</b><sub><b>K-1</b></sub>, <b>PE</b><sub><b>K+1</b></sub><b>, PE</b><sub><b>K+2</b></sub>, <b>PE</b><sub><b>K+3</b></sub>, <b>PE</b><sub><b>K+4</b></sub>) are supplied to multiplexers <b>2034</b> and <b>2036</b> of the L/R communication portion <b>2028</b> of the current processing element <b>PE</b><sub><b>K</b></sub>. One of these data units is selected and input into one of the working registers (M, A, B, C) <b>2026.</b> In Figure <b>10</b>, one of the data units from the left adjacent processing elements (<b>PE</b><sub><b>K-4</b></sub>, <b>PE</b><sub><b>K-3</b></sub>, <b>PE</b><sub><b>K-2</b></sub>, <b>PE</b><sub><b>K-1</b></sub>) is selected and input into the working register (<b>A</b>).
0144The ALU <b>2024</b> performs a predetermined operation for data supplied from the working registers (M, A, B, C) <b>2026</b> and outputs the operation results. Data of the operation results is written in either one of the register files <b>RF</b><sub><b>0</b></sub> and <b>RF</b><sub><b>1</b></sub><b>.</b> In general, data of the last operation result during each horizontal scanning period is written in the register file <b>RF</b> on the output side as the pixel data unit <b>DK'</b>, and transferred from the register file <b>RF</b> to the register of the corresponding block of the DOR <b>2020</b> during the immediately following horizontal blanking period.
0145The DOR <b>2020</b> has a capacity corresponding to the number of channels, the number of bits, and the number of pixels of the output image data units <b>D</b><sub><b>1</b></sub><b>'</b> to <b>D</b><sub><b>N</b></sub><b>'</b>, and is blocked for each pixel. The pixel data units <b>VS'</b> (<b>D</b><sub><b>1</b></sub><b>'</b> to <b>D</b><sub><b>N</b></sub><b>'</b>) as the operation results are supplied from the processing portion <b>2018</b> to the blocks of the DOR <b>2020</b>, and output sequentially from the blocks of the DOR <b>2020</b> during one horizontal scanning period, starting from the leftmost pixel data unit <b>D</b><sub><b>1</b></sub><b>'</b> followed by the subsequent pixel data units <b>D</b><sub><b>2</b></sub><b>'</b>, <b>D</b><sub><b>3</b></sub><b>'</b>, <b>...</b> in succession.
0146The register files <b>RF</b><sub><b>0</b></sub> and <b>RF</b><sub><b>1</b></sub> of the processing portion <b>2018</b> can accumulate the image data corresponding to one or two lines. This realizes the function of a line memory. The processing portion <b>2018</b> can also perform individual processing for a plurality of channels of image data units within one horizontal scanning period in a time-sharing manner.
0147Figure <b>11</b> illustrates a specific configuration of the image memory <b>2050</b> (Figure <b>7</b>). The illustrated image memory <b>2050</b> uses a synchronous dynamic random access memory (SDRAM) <b>2052</b> as a high-speed memory for temporarily storing image data. The SDRAM <b>2052</b> has a memory capacity of about 16M bits, for example, and includes a mapped memory region in a continuous address space. During memory accessing, a high-speed clock <b>CK</b> is supplied to the SDRAM <b>2052</b>, in addition to an memory address and control signals (RAS, CAS), so that the SDRAM <b>2052</b> can performs data strobing at a timing of the clock <b>CK.</b>
0148The other portions of the image memory <b>2050</b> other than the SDRAM <b>2052</b> constitute an interface portion (SDRAM interface).
0149Each of the input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, <b>SDI</b><sub><b>C</b></sub> and the output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, <b>SDO</b><sub><b>C</b></sub> is provided with a write (W) pointer register <b>2054</b> or <b>2058</b> for supplying pointing information indicating a write address (position) in the buffer and a read (R) pointer register <b>2056</b> or <b>2060</b> for supplying pointing information indicating a read address (position) in the buffer. The read pointer register <b>2056</b> on the input side also has a write address generation function for SDRAM accessing. The write pointer register <b>2058</b> on the output side also has a read address generation function for SDRAM accessing.
0150The output terminals of the input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, and <b>SDI</b><sub><b>C</b></sub> are connected to a data input terminal of the SDRAM <b>2052.</b> SDRAM addresses generated by the read pointer registers <b>2056</b> on the input side are supplied to an address terminal of the SDRAM <b>2052</b> via a multiplexer <b>2062.</b> SRAM addresses generated by the write pointer registers <b>2058</b> on the output side are supplied to the address terminal of the SDRAM <b>2052</b> via a multiplexer <b>2064</b> and the multiplexer <b>2062.</b>
0151A control portion <b>2066</b> includes a setting value register which receives program data for defining the operation mode of the image memory <b>2050</b> from the ROM loader <b>2076</b> or from an external controller via the I<sup>2</sup>C interface circuit <b>2078</b> and holds the program data therein (Figure <b>7</b>). The control portion <b>2066</b>, serving as a means for controlling the input buffers and the output buffers, controls the operations of the buffers and the pointer registers on the input and output sides, the switching of the multiplexers <b>2062</b> and <b>2064</b>, and the memory accessing to the SDRAM <b>2052</b> in accordance with the program data stored in the setting value register thereof and various timing control signals from the TCU <b>2074.</b>
0152Each of the input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, and <b>SDI</b><sub><b>C</b></sub> has a memory capacity corresponding to 128 pixels when the image data unit of one pixel is 16 bits, for example, and this memory capacity is divided into two portions, forming first and second input buffer portions.
0153The write/read operations of the input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, and <b>SDI</b><sub><b>C</b></sub> will be described with reference to Figures <b>12A</b> to <b>12E.</b> First, data is sequentially written in the first (left) input buffer portion starting from a head address (Figure <b>12A</b>). A write pointer <b>P</b><sub><b>W</b></sub> increments in accordance with a clock synchronized with the input image data <b>VS</b> (Figure <b>11</b>).
0154Once the first input buffer portion is filled with the input image date, the write pointer <b>P</b><sub><b>W</b></sub> points to the head address of the second (right) input buffer portion which is vacant. Upon start of the writing of the input image data into the second input buffer portion, a read pointer <b>P</b><sub><b>R</b></sub> points to the head address of the first input buffer portion, starting the reading of the input image data from the first input buffer portion (Figure <b>12B</b>).
0155The image data read from the input buffer is supplied to the data input terminal of the SDRAM <b>2052.</b> The memory address generated by the address generation function of the read pointer register <b>2056</b> is supplied to the address terminal of the SDRAM <b>2052</b> via the multiplexer <b>2062</b> simultaneously with the supply of the image data to the data input terminal of the SDRAM <b>2052.</b> At the same time, the address value increments as the read pointer <b>P</b><sub><b>R</b></sub> increments. The control portion <b>2066</b> selectively activates the read operations of the input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, and <b>SDI</b><sub><b>C</b></sub> by its arbitration function.
0156The read pointer <b>P</b><sub><b>R</b></sub> is synchronous with a data write clock for the SDRAM <b>2052.</b> While the transmission rate of normal image data is 10 MHz, the operation clock <b>CK</b> for the SDRAM <b>2052</b> is several times as high as the above rate, e.g., 80 MHz. In the input buffer, therefore, the read pointer <b>P</b><sub><b>R</b></sub> increments several times as fast as the write pointer <b>P</b><sub><b>W</b></sub><b>.</b> Thus, the reading is performed at a data rate several times as high as the writing (Figure <b>12C</b>).
0157As a result, the reading from the first input buffer portion terminates before the completion of the writing into the second input buffer portion, and the read pointer <b>P</b><sub><b>R</b></sub> stands by at the boundary position (Figure <b>12D</b>). Once the writing into the second input buffer portion is completed (Figure <b>12E</b>), the read pointer <b>P</b><sub><b>R</b></sub> points to the head address of the second input buffer portion, starting the reading from the second input buffer portion. At this time, the write pointer <b>P</b><sub><b>W</b></sub> returns to the head position of the first input buffer portion which is now vacant (in the state where all the image data has been read), and starts again the writing into the first input portion. In this way, the above procedure is repeated.
0158The read pointer <b>P</b><sub><b>R</b></sub> is only required to read all data in the input buffer which is filled with the data. The order of the reading is not necessarily the same as that of the writing by the write pointer <b>P</b><sub><b>W</b></sub><b>.</b> Incidentally, in the output buffers described hereinafter, the order of the writing by the write pointer <b>P</b><sub><b>W</b></sub> follows the order of the reading by the read pointer <b>P</b><sub><b>R</b></sub> in the input buffer.
0159In the image memory <b>2050</b> (Figure <b>8</b>), each of the output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, and <b>SDO</b><sub><b>C</b></sub> also has a memory capacity corresponding to 128 pixels, and the memory capacity is divided into two, forming first and second output buffer portions.
0160The write/read operations of the output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, <b>SDO</b><sub><b>C</b></sub> will be described with reference to Figures <b>13A</b> to <b>13E.</b> The operations of the output buffers are basically the same as those of the input buffers described above.
0161First, data is sequentially written in the first (left) output buffer portion starting from a head address (Figure <b>13A</b>). The data to be written is the image data read from the SDRAM <b>2052</b> (Figure <b>11</b>). The write pointer <b>P</b><sub><b>W</b></sub> increments in synchronization with the high-speed clock <b>CK</b> for the SDRAM <b>2052.</b>
0162The memory address generated by the address generation function of the write pointer register <b>2058</b> is supplied to the address terminal of the SDRAM <b>2052</b> via the multiplexers <b>2064</b> and <b>2062</b> in synchronization with a read clock of the SDRAM <b>2052.</b> At the same time, the address value increments.
0163The control portion <b>2066</b> selectively activates the write operation of the output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, <b>SDO</b><sub><b>C</b></sub> (Figure <b>8</b>) by its arbitration function. The control portion <b>2066</b> also performs the arbitration between the write operation of the output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, <b>SDO</b><sub><b>C</b></sub> and the read operation of the input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, <b>SDI</b><sub><b>C</b></sub>.
0164Once the first output buffer portion is filled with the output image data, the write pointer <b>P</b><sub><b>W</b></sub> stands by at the termination position. Upon start of the reading from the output buffer, the read pointer <b>P</b><sub><b>R</b></sub> points to the head address of the first output buffer portion, to perform the reading of the output image data from the first output buffer portion (Figure <b>13B</b>). At the same time, the writing of the output image data into the second output buffer portion is started. The read pointer <b>P</b><sub><b>R</b></sub> increments in synchronization with a clock corresponding to the transmission rate of the image data set or selected by the control portion <b>2066</b>, which is however lower than the rate of the write pointer <b>P</b><sub><b>W</b></sub><b>.</b>
0165Accordingly, the writing into the second output buffer portion terminates before the completion of the reading from the first output buffer portion, and the write pointer <b>P</b><sub><b>W</b></sub> stands by at the termination position (Figures <b>13C</b> and <b>13D</b>).
0166Once the reading from the first output buffer portion is completed (Figure <b>13E</b>), the read pointer <b>P</b><sub><b>R</b></sub> points to the head address of the second output buffer portion, and starts the reading from the second output buffer portion. At this time, the write pointer <b>P</b><sub><b>W</b></sub> returns to the head position of the first output buffer portion, and starts again the writing into the first output portion. In this way, the above procedure is repeated.
0167Thus, the image memory <b>2050</b> of this example can receive a plurality of channels of image data via the plurality of input ports or input buffers <b>SDI</b><sub><b>A</b></sub>, <b>SDI</b><sub><b>B</b></sub>, <b>SDI</b><sub><b>C</b></sub> in parallel synchronously or asynchronously, and output a plurality of channels of image data via the plurality of output ports or output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, <b>SDO</b><sub><b>C</b></sub> in parallel synchronously or asynchronously.
0168In the image memory <b>2050</b>, a single interface portion, in particular, the control portion <b>2066</b> efficiently controls under a unified management the exchanges of the image data between the input buffers <b>SDI</b><sub><b>A</b></sub><b>, SDI</b><sub><b>B</b></sub><b>, SDI</b><sub><b>C</b></sub> and the common SDRAM <b>2052</b> and between the SDRAM <b>2052</b> and the output buffers <b>SDO</b><sub><b>A</b></sub>, <b>SDO</b><sub><b>B</b></sub>, <b>SDO</b><sub><b>C</b></sub> in synchronization with the high-speed clock <b>CK.</b>
0169The image processor of this example can be constructed on a single semiconductor chip. Even when the SDRAM <b>2052</b> is externally mounted, the required number of terminal pins can be small, realizing a reduction of the device size.
0170Since the plurality of input/output ports are provided with the plurality of write pointers/read pointers and the relationships between the pointers can be programmably set, a variety of memory functions can be realized.
0171For example, as discussed below with respect to Figure <b>14</b>, one channel of image data may be written into the SDRAM <b>2052</b> via one input buffer, e.g. the input buffer <b>SDI</b><sub><b>A</b></sub>, and the image data written into the SDRAM <b>2052</b> may be read via the first and second output buffers <b>SDO</b><sub><b>A</b></sub> and <b>SDO</b><sub><b>B</b></sub> in parallel by using a time delay of a predetermined delay time. With this operation, the image data delayed by one field and the image data delayed by two fields con be obtained simultaneously.
0172Referring to Figure <b>14</b>, a write address (pointer) <b>AW</b> of the SDRAM <b>2052</b> corresponds to the read pointer <b>P</b><sub><b>R</b></sub> of the input buffer, and two read addresses (pointers) <b>AR</b><sub><b>a</b></sub> and <b>AR</b><sub><b>b</b></sub> correspond the write pointers <b>P</b><sub><b>W</b></sub> of the output buffers <b>SDO</b><sub><b>A</b></sub> and <b>SDO</b><sub><b>B</b></sub>.
0173In this example, the SDRAM <b>2052</b> is used for the image memory <b>2050.</b> Any other memory which has the equivalent memory function may also be used. For example, Rambus memories may be used. Alternatively, the image memory <b>2050</b> may be composed of a plurality of memory chips.
0174Figure <b>15</b> illustrates a specific configuration of the TCU <b>2074.</b> The illustrated TCU <b>2074</b> includes a main control portion <b>MC,</b> a vertical timing generation portion <b>VTG</b>, and a horizontal timing generation portion <b>HTG.</b> The TCU <b>2074</b> with the above configuration supplies timing control signals <b>TC</b> to the respective portions of the image processor shown in Figure <b>7</b>, i.e., the input section <b>2040</b>, the SIMD type digital signal processing section (<b>2010, 2012, 2014</b>), the image memory <b>2050</b>, the output section <b>2070</b>, the data buses <b>2072</b> (the multiplexers <b>2082</b>, <b>2084</b>, and <b>2086</b>), and the like in accordance with a vertical synchronous signal, a horizontal synchronous signal, and a pixel clock extracted from the video signals (the image data <b>VS</b>) input into the input section <b>2040.</b>
0175The main control portion <b>MC</b> includes a program counter, a program memory, a control logic, and the like. The main control portion <b>MC</b> generates a frame-base timing control signal <b>TC</b><sub><b>MC</b></sub> in accordance with the vertical synchronous signal, and controls the vertical timing generation portion <b>VTG</b> and the horizontal timing generation portion <b>HTG</b> of the TCU <b>2074.</b> The vertical timing generation portion <b>VTG</b> includes a sequence memory <b>VSM</b> and a loop memory <b>VLM</b>, and generates a line-base timing control signal <b>TC</b><sub><b>VTG</b></sub> and an internal control signal in accordance with the horizontal synchronous signal. The horizontal timing generation portion <b>HTG</b> includes a sequence memory <b>HSM</b> and a loop memory <b>HLM</b>, and generates a pixel-base timing control signal <b>TC</b><sub><b>HTG</b></sub> in accordance with the pixel clock.
0176Various types of program date supplied from the ROM loader <b>2076</b> or the I<sup>2</sup>C interface circuit <b>2078</b> via the internal bus are stored in various memories such as the program memory and the sequence memories in the main control portion <b>MC</b>, the vertical timing generation portion <b>VTG</b>, and the horizontal timing generation portion <b>HTG.</b>
0177The output section <b>2070</b> is composed of the output buffers, circuits for inserting blanking signals into the output image data, and the like. The function of the output section <b>2070</b> is also controlled by the program data supplied from the ROM loader <b>2076</b> or the I<sup>2</sup>C interface circuit <b>2078</b> via the internal bus and the timing control signal <b>TC</b> from the TCU <b>2074.</b>
0178Hereinbelow, the overall operation of the image processor with the above configuration will be described.
0179Figure <b>16</b> is a functional block diagram of an exemplary moving-image real-time processing system for illustrating the moving-image real-time processing to be performed by the image processor of this example.
0180In the illustrated moving-image real-time processing system, two field memories <b>2090</b> and <b>2092</b> at the input stage constitute one frame memory. A subtracter <b>2094</b> calculates a difference Δ between the input image data <b>VS</b> and image data output from the field memory <b>2092.</b> The difference Δ is supplied to an absolute circuit (ABS) <b>2096</b> and then to a nonlinearization circuit <b>2098</b>, so as to obtain a signal ΔS representing the degree of the change of the current screen from a screen preceding one frame for each pixel.
0181The signal ΔS is then supplied to an averaging circuit in the two-dimensional direction composed of a line memory <b>2100</b> and an adder <b>2102</b> and then to an averaging circuit in the time-axis direction composed of a field memory <b>2104</b> and an adder <b>2108.</b> These two averaging circuits constitute a three-dimensional low-pass filtering portion, where noise is removed and a motion detection signal <b>K</b> (0≤K≤1) is obtained.
0182On the other hand, the input image data <b>VS</b> is supplied to a moving-image processing portion <b>2114,</b> i.e., an averaging circuit in the vertical direction composed of a line memory <b>2110</b> and an adder <b>2112</b>, to perform a moving-image processing. A mixing circuit <b>2124</b> for motion compensation composed of multipliers <b>2116</b> and <b>2118</b>, a coefficient converter <b>2120</b>, and an adder <b>2122</b> is disposed at the subsequent stage of the moving-image processing portion <b>2114.</b>
0183The motion detection amount is maximum when the motion detection signal <b>K</b> is 1. In such a case, the image data from the moving-image processing portion <b>2114</b> is output through the multiplier <b>2116</b> and the adder <b>2122</b> without any processing. At this time, the image data delayed by one field supplied from the field memory <b>2090</b> is blocked at the multiplier <b>2118.</b>
0184Conversely, the motion detection amount is minimum when the motion detection signal <b>K</b> is 0. In such a case, the image data from the moving-image processing portion <b>2114</b> is blocked at the multiplier <b>2116</b>, and the image data delayed by one field from the field memory <b>2090</b> is output through the multiplier <b>2118</b> and the adder <b>2122</b> as still-image processed image data.
0185When the motion detection signal <b>K</b> is a value between 0 and 1, the image data from the moving-image processing portion <b>2114</b> and the image data delayed by one field from the field memory <b>2090</b> are mixed with a weighting corresponding to the value, and averaged image data is output.
0186In order to realize the moving-image real-time processing system as described above, the respective portions of the image processor perform the following processing and operations.
0187First, the function of the field memories <b>2090</b> and <b>2092</b> at the input stage is realized by the image memory <b>2050</b> by being controlled as described above with reference to Figure <b>14.</b> More Specifically, the input into the field memory <b>2090</b> is realized via the first input buffer <b>SDI</b><sub><b>A</b></sub>, for example, while the outputs from the field memories <b>2090</b> and <b>2092</b> are realized via the first and second output buffers <b>SDO</b><sub><b>A</b></sub>, and <b>SDO</b><sub><b>B</b></sub>.
0188The processing by the subtracter <b>2094</b>, the absolute circuit <b>2096</b>, and the nonlinearization circuit <b>2098</b> are performed by the SMID type digital signal processing section (<b>2010, 2012, 2014</b>). More specifically, the DIR <b>2016</b> of the SVP <b>2014</b> receives the input image data from the input section <b>2040</b> (Figure <b>7</b>) and the image data delayed by one frame from the image memory <b>2050</b> (frame memory <b>2090</b>) simultaneously for each line by synchronizing the one-frame delayed image data with the input image data from the input section <b>2040.</b> This synchronization can be realized by matching the timing of the reading from the output buffer <b>SDO</b> of the image memory <b>2050</b> with the input image data.
0189After the image data corresponding to one line has been input into the DIR <b>2016</b>, the SVP <b>2014</b> (Figure <b>7</b>) performs all the processing by the portions <b>2094</b>, <b>2096</b>, <b>2098</b>, <b>2100</b>, <b>2102</b>, <b>2108</b> of the system shown in Figure <b>16</b> described above during the subsequent horizontal scanning period, and temporarily outputs data of the processing results, i.e., data of the motion detection signal <b>K</b> via one output port of the DOR <b>2020.</b>
0190The field memory <b>2104</b> of the three-dimensional low-pass filtering portion is realized by the image memory <b>2050.</b> Accordingly, the data of the motion detection signal <b>K</b> output from the SVP <b>2014</b> as described above is written in the SDRAM <b>2052</b> via the third input buffer <b>SDI</b><sub><b>C</b></sub> of the image memory <b>2050</b>, read after one field from the SDRAM <b>2052</b> via the third output buffer <b>SDO</b><sub><b>C</b></sub>, and input into the DIR <b>2016</b> of the SVP <b>2014.</b>
0191The processing by the moving-image processing portion <b>2114</b> and the mixing circuit <b>2124</b> are also performed by the SVP <b>2014</b> within the same horizontal scanning period as the above-described processing by the three-dimensional low-pass filtering portion. More specifically, the SVP <b>2014</b> receives the image data delayed by one field from the first output port of the image memory <b>2050</b> at the third input port thereof. The processed image data <b>VS'</b> is then output from one output port of the DOR <b>2020</b> different from the one mentioned above to the output section <b>2070.</b>
0192As described above, in the image processor of this example, while one channel or a plurality of channels of image data or other intermediate data is transferred a plurality of times mainly between the SVP <b>2014</b> and the image memory <b>2050</b> via the data buses <b>2072</b>, the SVP <b>2014</b> performs required processing in accordance with the program stored in the program memory <b>2010.</b> In this way, the image processor can realize the moving-image real-time processing system.
0193The number of field or frame memory functions can be increased by increasing the number of input ports (input buffers) and output ports (output buffers) of the image memory <b>2050.</b> In this way, in the above-described moving-image real-time processing system, for example, a noise reduction function may be additionally provided by subjecting the image data output from the mixing circuit <b>2124</b> to a low-pass filter composed of a field memory.
0194Alternatively, by increasing the input/output data rates in the SVP <b>2014</b> and the image memory <b>2050</b>, a plurality of series or a plurality of channels of image data or intermediate data may be input/output via a single port in a time-sharing manner within one unit period (e.g., one horizontal scanning period).
0195The above-described moving-image real-time processing is only an example. The image processor of the present invention can realize a variety of image processing depending on the programs installed therein from outside. Some of such processing will be described hereinbelow.
0196Figure <b>17</b> illustrates a pointing control of the image memory <b>2050</b> (Figure <b>8</b>) for displaying different series or channels of images simultaneously by dividing the screen into two. In the illustrated example, the first channel of image data is compressed to be written into the left half of each line in the SDRAM <b>2052</b> using a first write pointer <b>AW</b><sub><b>a</b></sub>. At the same time, the second channel of image data is compressed to be written into the right half of each line using a second write pointer <b>AW</b><sub><b>b</b></sub>. These two channels of image data may be written asynchronously, but the head write positions of the fields should be matched with one another.
0197The image data written in the SDRAM <b>2052</b> in the above-described manner is read for each line after a delay of a predetermined time using a first read pointer <b>AR</b><sub><b>a</b></sub>, for example. The read image data is sent to a display device for screen display. As a result, an image corresponding to the first channel is displayed on the left half of the screen, while an image corresponding to the second channel is displayed on the right half of the screen. A large and small window display can also be realized in a similar manner.
0198As shown in Figure <b>17</b>, in parallel with the double-screen display processing as described above, an arbitrary memory function, e.g., a field or frame memory function may be provided by utilizing remained ports and memory regions of the image memory <b>2050</b> and using another pair of write/read pointers (<b>AW</b><sub><b>c</b></sub> and <b>AR</b><sub><b>c</b></sub>).
0199When one set or a plurality of sets of pointing operations are to be performed in the image memory <b>2050</b> as described above, a predetermined amount of memory portion is allocated to each set, so that each pointer may be turned in a loop within the memory portion. This enables to form many independent memory portions in the memory region of the SDRAM <b>2052.</b>
0200As another application, in the writing of image data into the image memory <b>2050</b>, the image data corresponding to only a portion of pixels or scanning lines may be selectively written. This reduces the number of pixels and the number of scanning lines for each image. In this way, a contracted screen as shown in Figure <b>18</b> can be produced. In this case, however, the rate of image data when it is read from the image memory <b>2050</b> must be made equal to that when it is written into the image memory <b>2050.</b>
0201In the above decimation processing, in consideration of the reproducibility of the pattern of an image, the image data is preferably first supplied to the SVP <b>2014</b> (Figure <b>8</b>) first to be subjected to a low-pass filtering, and then written into the image memory <b>2050</b> in the above-described manner.
0202Alternatively, as shown in Figure <b>19</b>, in the reading of image data from the image memory <b>2050</b>, the image data may be read intermittently with respect to a read clock <b>CL</b> for pixels or scanning lines. This enables to expand the space between pixels or scanning lines as shown in Figure <b>20.</b> In this case, the image data read from the image memory <b>2050</b> may be input into the SVP <b>2014</b> to perform horizontal and vertical interpolations, so that image data may be added or inserted to the positions of the pixels or scanning lines which had been skipped in the above intermittent reading, as shown by the dotted lines in Figure <b>20.</b>
0203As shown in Figure <b>21</b>, two series of asynchronous image data units <b>VS</b><sub><b>1</b></sub> and <b>VS</b><sub><b>2</b></sub> may be input into the SVP <b>2014</b> and the image memory <b>2050</b>, respectively, and the image data units <b>VS</b><sub><b>1</b></sub> and <b>VS</b><sub><b>2</b></sub> may be read in synchronization with a synchronous signal other than synchronous signals for the image data units <b>VS</b><sub><b>1</b></sub> and <b>VS</b><sub><b>2</b></sub>, for example, a synchronous signal on the side of a display device <b>2130.</b> At this time, the image data units <b>VS</b><sub><b>1</b></sub> and <b>VS</b><sub><b>2</b></sub> may be read as image data for a double-screen synthesized display as shown in Figure <b>17.</b>
0204In the image processor in this example, when the number n of pixels per line of the input image data <b>VS</b> is remarkably larger than the number of pixels per line which can be processed at one time by the SVP <b>2014</b>, i.e., when n = 1600 the number N of processing elements <b>PE</b> = 864, a method as shown in Figures <b>22</b> and <b>23</b> may be employed.
0205Conceptually, as shown in Figure <b>22</b>, the input image data <b>VS</b> is divided into two portions, a former half <b>VS</b><sub><b>i</b></sub> and a latter half <b>VS</b><sub><b>j</b></sub>, with a time gap <b>td</b> of an appropriate amount (e.g., a gap corresponding to 100 pixels) interposed therebetween. The image data unit of each of the former half <b>VS</b><sub><b>i</b></sub> and the latter half <b>VS</b><sub><b>j</b></sub> is then sequentially input into the DIR <b>2016</b> (Figure <b>7</b>) of the SVP <b>2014</b> as a pixel data unit having n/2 (800) pixels per line.
0206The processing portion <b>2018</b> of the SVP <b>2014</b> allocates separate processing periods for the image data units of the former half <b>VS</b><sub><b>i</b></sub> and the latter half <b>VS</b><sub><b>j</b></sub>, and performs the same processing repeatedly. The DOR <b>2020</b> outputs the processed image data unit in series.
0207In the output operation, the image data unit of the former half <b>VS</b><sub><b>i</b></sub> is delayed by a time corresponding to the above time gap, while the image data unit of the latter half <b>VS</b><sub><b>j</b></sub> is output without any delay from the same port of the output section <b>2070.</b> As a result, the head of the image data unit of the latter half <b>VS</b><sub><b>j</b></sub> comes in contact with the tail of the image data unit of the former half <b>VS</b><sub><b>i</b></sub>, so that the processed image data having n (1600) pixels per line which is the same as the original input image data <b>VS</b> is obtained.
0208As described above, one line may be divided into two for high-precision image data having a remarkably large number n of pixels per line.
0209In the above series of processing, the process of dividing the input image data <b>VS</b> into the former half <b>VS</b><sub><b>i</b></sub> and the latter half <b>VS</b><sub><b>j</b></sub> and forming the time gap <b>td</b> therebetween is performed by using the image memory <b>2050</b> and the multiplexer <b>2082</b> as a delay line as shown in Figure <b>23.</b>
0210More specifically, the input image data <b>VS</b> from the input section <b>2040</b> is directly sent to a first input terminal of the multiplexer <b>2082</b> (Figure <b>8</b>), and is simultaneously input into the image memory <b>2050.</b> Delayed image data <b>VS</b><sub><b>D</b></sub> delayed by a time corresponding to the fixed time gap <b>td</b> behind the input image data <b>VS</b> is output from one output port of the image memory <b>2050</b>, to be sent to a second input terminal of the multiplexer <b>2082.</b>
0211The multiplexer <b>2082</b> switches to the first input terminal for a predetermined time starting from the timing at the head of the input image data <b>VS</b> in accordance with a timing control <b>TC</b><sub><b>M</b></sub> from the TCU <b>2074</b> (Figure <b>7</b>). Then, after a predetermined shut-off time, the multiplexer <b>2082</b> switches to the second input terminal. As a result, the input image data <b>VS</b> is divided into the former half <b>VS</b><sub><b>i</b></sub> and the latter half <b>VS</b><sub><b>j</b></sub> with the time gap <b>td</b> of a predetermined among therebetween, and supplied to the SVP <b>2014.</b>
0212By providing the time gap <b>td</b> of an appropriate amount between the former half <b>VS</b><sub><b>i</b></sub> and the latter half <b>VS</b><sub><b>j</b></sub>, the tail portion of the former half <b>VS</b><sub><b>i</b></sub> and the head portion of the latter half <b>VS</b><sub><b>j</b></sub> are prevented from interfering or colliding against each other. Thus, data is prevented from being lost.
0213As shown in Figure <b>23</b>, while securing the time gap <b>td</b> of an appropriate amount, preferably, a portion δ which overlaps the head portion of the latter half <b>VS</b><sub><b>j</b></sub> by a predetermined number of pixels (e.g., 10 pixels) may be added to the tail of the former half <b>VS</b><sub><b>i</b></sub>, and a portion δ which overlaps the tail portion of the former half <b>VS</b><sub><b>i</b></sub> by a predetermined number of pixels (e.g., 10 pixels) is added to the head of the latter half <b>VS</b><sub><b>j</b></sub><b>.</b> These overlap portions are also input into the SVP <b>2014</b>, so that the processing portion <b>2018</b> of the SVP <b>2014</b> can perform a high-precision processing for the tail portion of the former half <b>VS</b><sub><b>i</b></sub> and the head portion of the latter half <b>VS</b><sub><b>j</b></sub> as is performed for the intermediate portions.
0214The processing of making the head of the latter half <b>VS</b><sub><b>j</b></sub> in contact with the tail of the former half <b>VS</b><sub><b>i</b></sub> as the last output processing is performed by using the image memory <b>2050</b> and the multiplexer <b>2086</b> as the delay line in a configuration similar to that shown in Figure <b>23.</b>
0215The image processor of this example can realize image compression of the image data using the decimation function of the SVP <b>2014</b> or the image memory <b>2050</b> as described above. At this information compression, the input image data is first subjected to the low-pass filtering in the input section <b>2040</b> before being supplied to the SVP <b>2014</b> or the image memory <b>2050</b>, so as to avoid a degradation in image quality such as a folding distortion caused by the information compression.
0216Figure <b>24</b> illustrates an exemplary circuit configuration of a main portion of a television receiver which uses the image processor of this example.
0217The television receiver with the image processor of this example incorporated therein is adaptive to a variety of video signals such as a monitor output signal <b>PC</b> from a personal computer, a base-band signal <b>BB</b> from a VTR and the like, a high-definition signal <b>MUSE</b>, and an NTSC signal <b>NTSC.</b> For example, a variety of modes may be set, including a mode where the NTSC signal is displayed on a monitor after passing through a D/A converter and simultaneously another arbitrary video signal is output via a D/A converter and recorded to a VTR or the like, and a mode where the high-definition signal and the NTSC signal are synthesized to display both signals on a monitor. When one of these modes is selected, corresponding program data may be loaded in the respective sections of the image processor by a download method as described above.
0218Figure <b>25</b> illustrates an exemplary circuit configuration of another television receiver which uses the image processor of this sample.
0219The television receiver includes a US standard advanced TV (ATV) decoder incorporated therein. This ATV decoder can decode input video signal transmitted under any of 18 types of display formats (e.g., 480 lines × 640 pixels, 600 lines × 800 pixels, and 768 lines × 1024 pixels).
0220However, although a reproduced video signal having any of the 18 types of display formats is output from the ATV decoder, a display device incorporated in the television receiver (e.g., a CRT, an LCD, and a plasma display) is only allowed to display the image data under one type of format (e.g., 768 lines × 1024 pixels).
0221The image processor of this example converts the reproduced video signal from the ATV decoder into a display format used by the display device before supplying the signal to the display device.
0222Thus, as described above, according to the image processing device of the present invention, the SIMD type digital signal processing section and the image memory which can perform the write operation and the read operation in parallel and independently are connected with each other via the data buses, so that the respective sections of the device can be programmably operated. Accordingly, the device can be adaptive to a variety of applications with a reduced-size circuit configuration. Further, the resources inside the device can be effectively utilized, to realize an effective high-level image processing.
(Example 6)
0223Figure <b>27</b> illustrates a configuration of a video signal processor <b>3001</b> of Example 6 according to the present invention. The video signal processor <b>3001</b> includes a serial-parallel converter <b>3016</b>, a data input register <b>3011</b>, an operator <b>3012</b>, a data output register <b>3015</b>, and a parallel-serial converter <b>3017.</b>
0224The serial-parallel converter <b>3016</b> receives a plurality of video data units corresponding to a plurality of effective pixels connected to one horizontal scanning line sent in series as an input video signal <b>S3001.</b> The serial-parallel converter <b>3016</b> converts the plurality of video data units into a plurality of video data sets. For example, the serial-parallel converter <b>3016</b> generates the video data sets by coupling the current video data unit among the plurality of video data units with a video data unit which has been delayed by a flipflop (FF) by one cycle of a video clock. In this case, when the bit width of the video data unit is eight bits, the bit width of the video data set is 16 (= 8×2) bits. The current video data and the video data delayed by one cycle of the video clock constituting the video data set are input into the data input register <b>3011</b> in parallel, and a plurality of such video data sets are input into the data input register <b>3011</b> in series as a video signal <b>S3003.</b>
0225The data input register <b>3011</b> outputs the plurality of serially input video data sets in parallel. The data input register <b>3011</b> has a width of <b>s</b> bits and a depth of <b>N</b> words. The bit width <b>s</b> of the data input register <b>3011</b> needs to be n times or more as large as the bit width of the video data unit wherein n is an integer equal to or more than 2 representing the number of video data units included in the video data set. The value n also represents the degree of parallelism when a plurality of video data units are arranged in parallel.
0226The operator <b>3012</b> performs predetermined operations on the plurality of video data sets output from the data input register <b>3011</b> in parallel. The operator <b>3012</b> includes N processor elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub><b>.</b> Each of the processor elements <b>PE</b><sub><b>1</b></sub> to <b>PE</b><sub><b>N</b></sub> includes a small-capacity memory <b>3013</b> which holds the input data and an operation result and an operating element <b>3014</b> which performs a predetermined signal processing operation.
0227The data output register <b>3015</b> outputs the plurality of video data sets processed by the operator <b>3012</b> in series. The data output register <b>3015</b> has a width of <b>t</b> bits and a depth of <b>N</b> words. The bit width <b>t</b> of the data output register <b>3015</b> needs to be n times or more as large as the bit width of the video data unit wherein n is an integer equal to or more than 2 representing the number of video data units included in the video data set.
0228The parallel-serial converter <b>3017</b> receives the plurality of video data sets output in series from the data output register <b>3015</b> as a video signal <b>S3004</b>, and converts the plurality of video data sets into a plurality of video data units. For example, the parallel-serial converter <b>3017</b> converts the plurality of video data sets into a plurality of video data units by alternately selecting the current video data units and the video data units delayed by one cycle of the video clock included in the plurality of video data sets. The plurality of video data units are output in series as an output video signal <b>S3002.</b>
0229Hereinbelow, the operation of the video signal processor <b>3001</b> will be described, taking the LPF (low-pass filtering) processing as an example.
0230Figure <b>28</b> is a timing chart illustrating the operations of the data input register <b>3011</b>, the operator <b>3012</b>, and the data output register <b>3015</b> in the LPF processing.
0231The video signal processor <b>3001</b> operates in accordance with a horizontal synchronous signal, which defines a horizontal blanking period and an effective video period as shown in Figure <b>28.</b>
0232During an effective video period <b>P</b><sub><b>i</b></sub>, a plurality of video data sets corresponding to one horizontal scanning line are input into the data input register <b>3011</b> in series. For example, one horizontal scanning line may be the i-th horizontal scanning line. Hereinbelow, the i-th horizontal scanning line is referred to as the i line wherein i is an arbitrary integer.
0233During a horizontal blanking period <b>B</b><sub><b>i</b></sub> following the effective video period <b>P</b><sub><b>i</b></sub>, the plurality of video data sets corresponding to the i line input into the data input register <b>3011</b> are transferred to the operator <b>3012</b> in parallel.
0234During an effective video period <b>P</b><sub><b>i+1</b></sub> following the horizontal blanking period <b>B</b><sub><b>i</b></sub>, the LPF processing is performed for the plurality of video data sets corresponding to the i line.
0235During a horizontal blanking period <b>B</b><sub><b>i+1</b></sub> following the effective video period <b>P</b><sub><b>i+1</b></sub>, a plurality of LPF-processed video data sets corresponding to the i line are transferred to the data output register <b>3015</b> in parallel.
0236During an effective video period <b>P</b><sub><b>i+2</b></sub> following the horizontal blanking period <b>B</b><sub><b>i+1</b></sub> (not shown in Figure <b>28</b>), the plurality of LPF-processed video data sets corresponding to the i line are output from the data output register <b>3015</b> in series.
0237The above-described processing are also performed for a plurality of video data sets corresponding to an (i-1) line and a plurality of video data units corresponding to an (i+1) line.
0238Figures <b>29A</b> to <b>29E</b> illustrate the operations of the serial-parallel converter <b>3016</b> and the data input register <b>3011.</b>
0239The serial-parallel converter <b>3016</b> operates in accordance with the video clock of which waveform is shown in Figure <b>29A.</b>
0240The serial-parallel converter <b>3016</b> receives a plurality of video data units D<sub>j</sub> (j is an integer equal to or more than 0) corresponding to a plurality of effective pixels connected to one horizontal scanning line input in series as the input video signal <b>S3001.</b> The waveform of the input video signal <b>S3001</b> is shown in Figure <b>29B.</b>
0241The serial-parallel converter <b>3016</b> couples a current video data unit D<sub>2j+1</sub> with a video data unit D<sub>2j</sub> which has been delayed by a flipflop (FF) by one cycle of the video clock, so as to generate a video data set (D<sub>2j</sub>, D<sub>2j+1</sub>). For example, when the bit width of the video data unit D<sub>2j+1</sub> is eight bits, the bit width of the video data set (D<sub>2j</sub>, D<sub>2j+1</sub>) is 16 (= 8×2) bits. The current video data unit D<sub>2j+1</sub> and the video data D<sub>2j</sub> delayed by one cycle of the video clock are input into the data input register <b>3011</b> in parallel, and the plurality of video data sets (D<sub>2j</sub>, D<sub>2j+1</sub>) are input into the data input register <b>3011</b> in series as the video signal <b>S3003.</b> The waveform of the video signal <b>S3003</b> is shown in Figure <b>29C.</b>
0242The data input register <b>3011</b> controls the writing of the video signal <b>S3003</b> into the data input register <b>3011</b> in accordance with a write enable signal <b>WE.</b> In other words, the data input register <b>3011</b> permits the video signal <b>S3003</b> to be written thereinto when the write enable signal <b>WE</b> is in a high level, and prohibits the video signal <b>S3003</b> to be written thereinto when the write enable signal <b>WE</b> is in a low level. The waveform of the write enable signal <b>WE</b> is shown in Figure <b>29D.</b>
0243By using the write enable signal <b>WE</b> having the waveform shown in Figure <b>29D</b>, the video signal <b>S3003</b> is written into the data input register <b>3011</b> for each cycle of the write enable signal <b>WE.</b> In this way, the video data D<sub>2j</sub> and the video data unit D<sub>2j+1</sub> included in the video data set (D<sub>2j</sub>, D<sub>2j+1</sub>) are input into the data input register <b>3011</b> in parallel.
0244Figure <b>30</b> diagrammatically illustrates the LPF processing performed by the operator <b>3012.</b> In the example shown in Figure <b>30</b>, the operator <b>3012</b> performs the LPF processing for the video date units <b>D</b><sub><b>2j-2</b></sub><b>, D</b><sub><b>2j-1</b></sub><b>, D</b><sub><b>2j</b></sub><b>, D</b><sub><b>2j+1</b></sub><b>, D</b><sub><b>2j+2</b></sub><b>, D</b><sub><b>2j+3</b></sub> corresponding to the i line, and outputs the LPF-processed video data units <b>D'</b><sub><b>2j-2</b></sub><b>, D'</b><sub><b>2j-1</b></sub><b>, D'</b><sub><b>2j</b></sub><b>, D'</b><sub><b>2j+1</b></sub><b>, D'</b><sub><b>2j+2</b></sub><b>, D'</b><sub><b>2j+3</b></sub> corresponding to the i line.
0245The LPF-processed video data <b>D'</b><sub><b>2j</b></sub> is obtained by the calculation of expression (2) below, and the LPF-processed video data <b>D'</b><sub><b>2j+1</b></sub> is obtained by the calculation of expression (3) below.<maths id="math0002"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(2)</mtext><mtd><mrow><msub><mrow><mtext>D'</mtext></mrow><mrow><mtext>2j</mtext></mrow></msub><msub><mrow><mtext> = 1/4·D</mtext></mrow><mrow><mtext>2j-1</mtext></mrow></msub><msub><mrow><mtext> + 1/2·D</mtext></mrow><mrow><mtext>2j</mtext></mrow></msub><msub><mrow><mtext> + 1/4·D</mtext></mrow><mrow><mtext>2j+1</mtext></mrow></msub></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(3)</mtext><mtd><mrow><msub><mrow><mtext>D'</mtext></mrow><mrow><mtext>2j+1</mtext></mrow></msub><msub><mrow><mtext> = 1/4·D</mtext></mrow><mrow><mtext>2j</mtext></mrow></msub><msub><mrow><mtext> + 1/2·D</mtext></mrow><mrow><mtext>2j+1</mtext></mrow></msub><msub><mrow><mtext> + 1/4·D</mtext></mrow><mrow><mtext>2j+2</mtext></mrow></msub></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0905973A2_D0002.tif" /></maths>
0246The calculations of expressions (2) and (3) are performed by the processor element <b>PE</b><sub><b>j</b></sub><b>.</b> Similar calculations to those of expressions (2) and (3) are performed by each of the processor elements <b>PE</b><sub><b>j-1</b></sub> and <b>PE</b><sub><b>j+1</b></sub>. The number of LPF processing performed by each of the processor elements <b>PE</b><sub><b>j-1</b></sub>, <b>PE</b><sub><b>j</b></sub>, and <b>PE</b><sub><b>j+1</b></sub> is two for one line. In this way, the LPF-processed video data units <b>D'</b><sub><b>2j-2</b></sub><b>, D'</b><sub><b>2j-1</b></sub>, <b>D'</b><sub><b>2j</b></sub>, <b>D'</b><sub><b>2j+1</b></sub><b>, D'</b><sub><b>2j+2</b></sub>, <b>D'</b><sub><b>2j+3</b></sub> corresponding to the i line are obtained.
0247When the number of video data units included in the video data set is n, the number of LPF processing performed by each processor element is n.
0248Figures <b>31A</b> to <b>31E</b> illustrates the operations of the parallel-serial converter <b>3017</b> and the data output register <b>3015.</b>
0249The parallel-serial converter <b>3017</b> operates in accordance with a video clock of which waveform is shown in Figure <b>31A.</b>
0250The data output register <b>3015</b> controls the reading of the LPF-processed video data set (D'<sub>2j</sub>, D'<sub>2j+1</sub>) stored in the data output register <b>3015</b> in accordance with a read enable signal <b>RE.</b> In other words, the data output register <b>3015</b> permits the LPF-processed video data set (D'<sub>2j</sub>, D'<sub>2j+1</sub>) to be read therefrom when the read enable signal <b>RE</b> is in a high level, and prohibits the LPF-processed video data set (D'<sub>2j</sub>, D'<sub>2j+1</sub>) to be read therefrom when the read enable signal <b>RE</b> is in a low level. The waveform of the read enable signal <b>RE</b> is shown in Figure <b>31B.</b>
0251The parallel-serial converter <b>3017</b> receives the plurality of LPF-processed video data sets (D'<sub>2j</sub>, D'<sub>2j+1</sub>) input in series as the video signal <b>S3004.</b> The waveform of the video signal <b>S3004</b> is shown in Figure <b>31C.</b>
0252The parallel-serial converter <b>3017</b> delays the LPF-processed video data D'<sub>2j+1</sub> among the LPF-processed video data sets (D'<sub>2j</sub>, D'<sub>2j+1</sub>) input as the video signal <b>S3004</b> by one cycle of the video clock, so as to generate an internal video signal <b>S3005.</b> The waveform of the internal video signal <b>S3005</b> is shown in Figure <b>31D.</b> The LPF-processed video data D'<sub>2j+1</sub> can be delayed by the flipflop (FF), for example.
0253The parallel-serial converter <b>3017</b> outputs a plurality of LPF-processed video data units D'<sub>j</sub> (j is an integer equal to or more than 0) in series as the output video signal <b>S3002</b> by alternately selecting the most significant bit portion and the least significant bit portion of the internal video signal <b>S3005</b> for each cycle of the video clock. The waveform of the output video signal <b>S3002</b> is shown in Figure <b>31E.</b> The selection of the internal video signal <b>S3005</b> is realized by a selector, for example.
0254Thus, in this example, a plurality of video data units corresponding to a plurality of effective pixels connected to one horizontal line are converted into a plurality of video data sets by the serial-parallel converter <b>3016.</b> At least two video data units included in each video data set are processed by each processor element <b>PE</b><sub><b>j</b></sub>, and the plurality of video data sets are converted into the plurality of video data units corresponding to the plurality of effective pixels connected to one horizontal scanning line by the parallel-serial converter <b>3017.</b> In this way, the video data units corresponding to one horizontal scanning line can be processed using the number of processor elements <b>PE</b><sub><b>j</b></sub> smaller than the number of effective pixels connected to one horizontal scanning line. For example, when each video data set includes n video data units, the number of processor elements <b>PE</b><sub><b>j</b></sub> can be l/n of the number of effective pixels connected to one horizontal scanning line.
0255The processing performed by the operator <b>3012</b> is not restricted to the LPF processing. The LPF processing is merely an example of the processing which can be performed by the operator <b>3012.</b> The operator <b>3012</b> may perform an arbitrary processing other than the LPF processing, such as other filtering processing and image processing.
0256In this example, the degree of parallelism where a plurality of video data units are arranged in parallel for the serial-parallel converter <b>3016</b> and the parallel-serial converter <b>3017</b> is set at 2. The degree of parallelism is not restricted to 2, but can be an arbitrary integer equal to or more than 3 as well.
0257In the video signal processor according to the present invention, a plurality of video data units corresponding to a plurality of effective pixels connected to one scanning line are converted into a plurality of video data sets. Each of the plurality of video data sets includes at least two video data units. The plurality of video data sets are processed, and the plurality of processed video data sets are converted into the plurality of processed video data units. In this way, since the processing is performed for the video data set including at least two video data units as a unit, the processing efficiency is improved.
0258Each of the plurality of processor elements of the operator processes at least two video data units included in one video data set. Accordingly, the number of processor elements of the operator can be made smaller than the number of effective pixels connected to one scanning line. For example, when each video data set includes n video data units, the number of processor elements of the operator can be l/n of the number of effective pixels connected to one scanning line. By reducing the number of processor elements required to process one scanning line, the cost of the entire video signal processor can be reduced.
0259It will be appreciated that the video signal processor of this example may also be used in conjunction with the television receivers discussed above with respect to Figures <b>24</b> and <b>25.</b>
0260Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.
Contents6
36 sheets
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| Document | Relation | Office | Cited during |
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| EP1161084A3 | Cited by | European Patent Office (EPO) | Search report |
| US10572967B2 | Cited by | United States of America | Applicant |
| EP1645116B1 | Cited by | European Patent Office (EPO) | Examiner |
| US7599009B2 | Cited by | United States of America | Applicant |
| CN103024588A | Cited by | China | Search report |
| EP1161084A2 | Cited by | European Patent Office (EPO) | Search report |
| EP1645116A1 | Cited by | European Patent Office (EPO) | Examiner |
| EP0317218A2 | Cites | European Patent Office (EPO) | Search report |
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| EP0574901A2 | Cites | European Patent Office (EPO) | Search report |
| EP0594241A1 | Cites | European Patent Office (EPO) | Search report |
| EP0620681A2 | Cites | European Patent Office (EPO) | Search report |
| US5105387A | Cites | United States of America | Search report |
| US5132793A | Cites | United States of America | Search report |
| US5387939A | Cites | United States of America | Search report |
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| US5499375A | Cites | United States of America | Search report |
| US5708618A | Cites | United States of America | Examiner |
| US5708618A | Cites | United States of America | Examiner |
| HITACHI: "DATA SHEET HM530281R Series 311776-word x 8 bit Frame Memory", 19 April 1997, HITACHI | Non-patent | – | Examiner |
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| CN1230849A | China | A | |
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| US6353460B1 | United States of America | B1 | |
| CN1167006C | China | C | |
| JP3607798B2 | Japan | B2 | |
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Numbers
- Publication
- 0905973
- Application
- 981184609
Titles3
- German
- Fernsehempfänger, Vorrichtung zum Verarbeiten von Videosignalen , Verfahren und Vorrichtung zum Verarbeiten von Bildern
- English
- Television receiver, video signal processing device, image processing method and device
- French
- Récepteur de télévision, dispositif de traitement de signal vidéo, procédé et dispositif de traitement d'images
Classification
- CPC, 8
- H04N7/0122
- H04N5/45
- H04N5/46
- H04N5/907
- H04N7/01
- H04N21/4316
- H04N21/440218
- H04N21/4622
- IPC, 4
- H04N5 44
- H04N5 45
- H04N5 46
- H04N5 907
Designated states25
- Contracting states, 19
- Austria
- Belgium
- Switzerland
- Cyprus
- Germany
- Denmark
- Spain
- Finland
- France
- United Kingdom
- Greece
- Ireland
- Italy
- Liechtenstein
- Luxembourg
- Monaco
- Netherlands (Kingdom of the)
- Portugal
- Sweden
- Extension states, 6
- Albania
- Lithuania
- Latvia
- North Macedonia
- Romania
- Slovenia