Division circuit and method

A circuit and method for performing signed integer division by repeated division processing, in which a new partial remainder is formed by subtracting (or adding) a divisor from (to) a dividend or a partial remainder in accordance with the sign of the dividend or the partial remainder and the sign of the divisor, and a quotient bit is formed on the basis of the sign of the partial remainder and the sign of the divisor, wherein a pre-processing step corrects the dividend by subtracting 1 from the dividend if it is negative, and a post-processing step corrects the quotient formed by the repeated division processing on the basis of its sign.