Data processing system with synchronous dynamic memory in integrated circuit technology

The data processing system preferably employs standard components with general applicability in different architectures. A single chip main storage apparatus (102) is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode. Another chip comprises a microprocessor unit (101) and a main storage controller (104) which are respectively formed of independent cores inside the same chip. The microprocessor unit (101), the main storage controller (104) and the main storage apparatus (102) are coupled together by buses (153, 154). A control bus (156) supplies control signals from the main storage controller (104) to the main storage apparatus (102). Timing control for the data processing system is through a clock generator (103) which supplies synchronous clock signals to the microprocessor unit (101) via coupling line (150), to the main storage controller (104) via coupling line (152), and to the main storage apparatus (102) via coupling line (151). Circuitry to enable the control of parallel accesses to a plurality of memory banks in the main storage apparatus (102) and of setting an operation mode function to a mode register built in said synchronous dynamic memory is arranged in the main storage controller (104) so that both the conventional microprocessor unit (101) and the conventional main storage apparatus (104) are not burdened with special circuitry which would impair the use of processor IC cores and memory IC chips of standard design and high generality.