A Quantizer for video signal encoding system

0001The present invention relates to a quantizer and more particularly to a quantizer for quantizing scanned Discrete Cosine Transform (DCT) coefficients in a video signal encoding system.

0002Fig. 1 shows a block diagram of a conventional MPEG-2 video encoder comprising a frame memory, a subtracter (SUB), a Discrete Cosine Transform unit (DCT unit), a quantizer (Q), a scanning unit, a Variable Length Coding unit (VLC unit), an inverse quantizer (IQ), an Inverse Discrete Cosine Transform unit (IDCT unit), an adder (ADD), and a motion compensator (MC).

0003In Fig. 1, a differential video signal between a current video signal from the frame memory and a previous video signal motion-compensated in the motion compensator is calculated in the subtracter, and outputted to the DCT unit. In the DCT unit, the differential video signal is converted into DCT coefficients. The DCT coefficients are quantized in the quantizer, and the quantized DCT coefficients are outputted to the scanning unit and the inverse quantizer. In the scanning unit, the quantized two-dimension DCT coefficient series are converted into one-dimension coefficient series, and are outputted to the VLC unit or a Run Length Coding unit (RLC unit) for generating a final coded bit-stream.

0004As described above, in the conventional MPEG-2 video encoder, the scanning is performed after the video data have been quantized. However, due to the problem of latency caused by the structural restraint of the conventional video encoder, there has been a need for video encoder in which the scanning is performed prior to quantization of the video signals.

0005Fig. 2 shows a differential circuit except a motion compensator of a video encoder in which the scanning is performed prior to quantization. The video encoder comprises a orthogonal transform unit, a scanning unit, a quantizer, and a coding unit. In the orthogonal transform unit, input video signals are converted by DCT. In the scanning unit, the converted two dimension DCT coefficients are converted into one dimension coefficient series to be quantized. In the coding unit, the quantized one-dimension coefficient series are coded by a VLC or a RLC to generate a coded bitstream. The video encoder similar to the above is disclosed in U.S. Pat. No. 5,369,439.

0006In the MPEG-1 video encoder, the DCT coefficients, as shown in Fig. 3A, are converted to the one dimension coefficient series by a zigzag scanning. An alternate scanning, as shown in Fig. 3B, or the zigzag scanning may be used selectively in picture units in the MPEG-2 video encoder. This alternate scanning can also be efficiently used in an interlaced scanning screen.

0007However, as shown in Fig.2, when the scanning is performed before quantization, the quantizer must provide quantization matrixes corresponding to the zigzag and alternate scanning manner of the scanning unit. In MPEG-2 video encoder, the quantization is of adaptive quantization, since a weighted value is changed according to a spatial frequency. Accordingly, a matrix for quantizing an intra block (intra quantization matrix) and a matrix for quantizing, an inter block (inter quantization matrix) are required according to the coding mode. In the quantizer, only the zigzag manner is required for an input order of the matrix, however, an input order of video data changes by the scanning manner. Accordingly, in order to quantize the scanned DCT coefficients, the order of quantization matrix should correspond with the order of input video data affected by the scanning manner. Particularly, input video data couples should match quantization matrix couples when processing two pixels by 16 bits for a fast video coding in the quantizer.

0008In view of the foregoing, it is an object of the present invention to provide a quantizer for quantizing scanned DCT coefficients, which reads in a zigzag order or an alternate order, according to a scanned manner of DCT coefficients, a quantization matrix stored in a memory in a zigzag order and quantizes one dimension DCT coefficients.

0009In order to achieve the above object, the present invention provides a quantizer for quantizing scanned DCT comprising: <ul id="ul0001" list-style="none" compact="compact"><li>a memory having a first bank, which is constructed with a plurality of areas for storing an inter quantization matrix; and a second bank, which is constructed with a plurality of areas for storing an intra quantization matrix;</li><li>a memory control unit for generating a write address for writing the inter quantization matrix and the intra quantization matrix in the memory in a zigzag order, and a read address for reading corresponding quantization matrix from the memory in accordance with the scanned manner of the DCT coefficients, and controlling a write/read process for the inter quantization matrix and the intra quantization matrix in the memory according to the write address and the read address;</li><li>an arithmetic controller for obtaining and outputting a reciprocal value of corresponding quantization matrix from the memory control unit and a reciprocal value of a quantization scale supplied externally; and</li><li>an arithmetic unit for quantizing the scanned DCT coefficients by using the quantization scale value and the quantization matrix value from the arithmetic controller.</li></ul>

0010The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings, in which: <ul id="ul0002" list-style="none" compact="compact"><li>Fig. 1 is a block diagram illustrating an embodiment of the conventional video encoder;</li><li>Fig. 2 is a block diagram illustrating an another embodiment of the conventional video encoder;</li><li>Fig. 3A to 3B are views illustrating a zigzag scanned and an alternate scanned DCT coefficients;</li><li>Fig. 4 is a block diagram illustrating a quantizer in accordance with the present invention;</li><li>Fig. 5 is a detailed block diagram illustrating a RAM and a RAM controller in accordance with a first preferred embodiment of the present invention; and</li><li>Fig. 6 is a detailed block diagram illustrating a RAM and a RAM controller in accordance with a second preferred embodiment of the present invention.</li></ul>

0011Reference will now be made in detail to the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

0012Fig. 4 shows a block diagram of a quantizer in accordance with the present invention. The quantizer comprises a memory, namely a RAM <b>42</b> for storing an inter quantization matrix and an intra quantization matrix; a RAM controller <b>44</b> for generating a write address of a zigzag order and a read address in accordance with a scanned manner of DCT coefficients, and for controlling a read/write process of the quantization matrix from the RAM <b>42</b> according to the read/write address; an arithmetic controller <b>46</b> for obtaining and outputting a reciprocal value of a quantization scale and a reciprocal value of corresponding quantization matrix from the RAM <b>42</b>; and an arithmetic unit <b>48</b> for quantizing the scanned DCT coefficients by using the quantization scale value and the quantization matrix value from the arithmetic controller <b>46</b>.

0013Fig. 5 shows a detailed block diagram of a RAM <b>42</b> and a RAM controller <b>44</b> in accordance with the first preferred embodiment. In Fig. 5, the RAM <b>42</b> comprises a first bank <b>BANK1</b> for storing the inter quantization matrix and a second bank <b>BANK2</b> for storing the intra quantization matrix. The first bank <b>BANK1</b> comprises a first sub-RAM <b>BANK1A</b> and a second sub-RAM bank <b>BANK1B</b> for storing the same inter quantization matrix. The second bank <b>BANK2</b> comprises a third sub-RAM <b>BANK2A</b> and a fourth sub-RAM <b>BANK2B</b> for storing the same intra quantization matrix. The first sub-RAM to fourth sub-RAM <b>BANK1A</b>, <b>BANK1B, BANK2A, BANK2B</b> are 16 bits x 32 words in their size.

0014The RAM controller <b>44</b> comprises a write address generator, a first counter <b>50</b>, for generating a write address to store the inter quantization matrix and the intra quantization matrix into the RAM <b>42</b>; a read address generator comprising a second counter <b>51</b>, a programmable logic array (PLA) <b>52</b>, and a first multiplexer <b>53</b>, for generating a read address to read a corresponding quantization matrix from the RAM <b>42</b> in accordance with the scanned manner of the DCT coefficients; a data combiner comprising a second multiplexer <b>54</b> and a packing unit <b>55</b>, for combining the quantization matrix from the RAM <b>42</b> to form 16 bit data according to a coding mode or the scanning order.

0015Input/output signals into/from each block need to be defined and elaborated prior to describing each operation of the above quantizer.

0016Of input signals to the RAM controller <b>44</b>, "CLK" and "RST" indicate a system clock and a reset signal for active low operation, respectively. In "ID_CD", identifier <b>ID</b> represents a quantization matrix (namely, inter quantization matrix or intra quantization matrix) and <b>CD</b> represents succeeding quantization matrix data. "FLAG_ID" indicates that the current input ID_CD is valid. For example, ID_CD is read and the succeeding quantization matrix data <b>CD</b> is read in two pixel units, namely 16 bit if FLAG_ID is a "high" logic level. "mbs" indicates a macro block start.

0017Of input signals to the arithmetic controller <b>46</b>. "QUANT_SCALE_CODE" and "QUANT_SCALE_TYPE" are signals for indicating a quantization scale in MPEG-2. "DC PREC" indicates a size (accuracy) of DC coefficient of an intra block defined in MPEG-2; for example, the DC coefficient is represented to 8bit if it is 0 and the coefficient is represented to 11 bit if it is 3.

0018Of input signals to the arithmetic unit <b>48</b>, "DATA_EVEN" and "DATA ODD" indicate even and odd data of two pixel units converted by the DCT, respectively. Of output signals from the arithmetic unit <b>48</b>, "QUANT EVEN" and "QUANT ODD" are quantized output data of the input even and the odd data in two pixel units.

0019Referring to an operation of each block in Fig. 5, the inter quantization matrix data are stored in the first and the second sub-RAM <b>BANK1A, BANK1B</b> of the first bank <b>BANK1</b> of the RAM <b>42</b> in 16 bit units. The intra quantization matrix data are stored in the third and the fourth sub-RAM <b>BANK2A, BANK2B</b> of the second bank <b>BANK2</b> of the RAM <b>42</b> in 16 bit units. In the first sub-RAM <b>BANK1A</b> and the second sub-RAM <b>BANK1B</b> of the first bank <b>BANK1</b>, the same inter quantization matrix data are stored in 16 bit units in 32 areas that are indicated by a write address <b>WADD0</b>. In the third and the fourth sub-RAM <b>BANK2A, BANK2B</b> of the second bank <b>BANK2</b>, the same intra quantization matrix data are stored in 16 bit units in the 32 areas, which is indicated by a write address <b>WADD0</b>. The inter and the intra quantization matrix data are supplied from a system control unit (not shown), and they may be an user defined matrix or a default matrix defined in MPEG-2.

0020The RAM controller <b>44</b> is operated by a system clock <b>CLK</b> and a reset signal <b>RST</b>. The quantization matrix inputted through ID_CD is stored in an corresponding bank of the RAM <b>42</b> according to the write address <b>WADD0</b>. The quantization matrix in the RAM <b>42</b> is read by the read address RADD0 when the DCT coefficients are scanned in the zigzag order, whereas it is read by read addresses RADD1, RADD2 when the DCT coefficients are scanned in the alternate order. The read quantization matrix is outputted to the arithmetic controller <b>46</b>. Namely, in the RAM controller <b>44</b>, ID_CD is analyzed to identify the quantization matrix when FLAG_ID is a "high" logic level, and analyzed input quantization matrix is stored in corresponding sub-RAMs of banks of the RAM <b>42</b> according to the write address <b>WADD0</b>. Additionally, the quantization matrixes stored in the sub-RAMs are synchronized by the macro block start signal and they are read and outputted to the arithmetic controller <b>46</b> according to the read address <b>RADD0</b> and the read addresses <b>RADD1, RADD2</b> which correspond to the scanning manner. Each sub-RAM has a control signal for reading and writing (not shown), and a control signal for enabling an output (not shown). The control signals are supplied when the corresponding sub-RAM is selected by the RAM controller <b>44</b>.

0021Referring to Fig. 5, the first counter <b>50</b> (5 bits counter) counts 00_H to 3F_H according to a clock signal <b>CLK</b> after clearing a count value by reset signal <b>RST</b>. 32 write addresses <b>WADD0</b> are generated to store the quantization matrix data from the system control unit (not shown) in the first and second sub-RAMs <b>BANK1A, BANK1B</b>, and the third and the fourth sub-RAMs <b>BANK2A, BANK2B</b> in 16 bit units. Examples of the write address <b>WADD0</b> is represented in the following table 1. <tables id="tabl0001" num="0001"><img file="EP0808069A2_D0001.tif" /></tables><tables id="tabl0002" num="0002"><img file="EP0808069A2_D0002.tif" /></tables>

0022The above table 1 shows when the inter quantization matrix is stored in the first and the second sub-RAM <b>BANK1A, BANK1B</b>. The matrix data couple (00, 01) are stored in the area '00' indicated by the read address <b>WADD0</b> when the count value is 00₁₆. The matrix data couple (02, 03) are stored in the area 01 indicated by read address <b>WADD0</b> when the count value is 01₁₆. Namely, each inter quantization matrix couple is stored sequentially in the zigzag order, as shown in Fig. 3A, in the areas 00₁₆ - 1F₁₆ indicated by the write address. In the same manner, each intra quantization matrix couple is stored sequentially in the zigzag order in the areas 00₁₆ - 1F₁₆ of the third and the fourth sub-RAM <b>BANK2A, BANK2B</b>.

0023The second counter <b>51</b> (5 bit counter) counts 00_H to 1F_H according to the clock signal <b>CLK</b> after clearing the count value by the reset signal <b>RST</b>. After clearing, a rising edge of the macro block start signal <b>mbs</b> is detected in the second counter <b>51</b> and 32 count values are outputted to a PLA <b>52</b> and a packing unit <b>55</b>.

0024As shown in the following tables 2 and 3. in the PLA <b>52</b>. the read address <b>RADD0</b> is generated according to the zigzag scanning of the DCT coefficients and the count value of the second counter <b>51</b>. In addition, in the PLA <b>52</b>, the read addresses <b>RADD1, RADD2</b> are also generated according to the alternate scanning of the DCT coefficients and the count value of the second counter <b>51</b>. <tables id="tabl0003" num="0003"><img file="EP0808069A2_D0003.tif" /></tables><tables id="tabl0004" num="0004"><img file="EP0808069A2_D0004.tif" /></tables>

0025The above table 2 shows examples of the inter quantization matrix read from the first and the second sub-RAMs <b>BANK1A, BANK1B</b>. In the first and the second sub-RAM <b>BANK1A, BANK1B</b>, the matrix data couple (00, 01) stored in the area '00' are read by the read address <b>RADD0</b> when the count value is 00₁₆. In the first and the second sub-RAM <b>BANK1A, BANK1B</b>, the matrix data couple (02, 03) stored in the area '01' are read by the read address <b>RADD0</b> when the count value is 01₁₆. Namely, each matrix data couples stored in the areas 00₁₆ - 1F₁₆ indicated by the read address <b>RADD0</b> are read sequentially in the zigzag order as shown in Fig. 3A. In the same manner, each intra quantization matrix data couples stored in the areas 00₁₆ - 1F₁₆ of the third and the fourth sub-RAMs <b>BANK2A, BANK2B</b> are read sequentially in the zigzag order. Referring to the tables 1 and 2, the write address <b>WADD0</b> correspond with the read address <b>RADD0</b> when the DCT coefficients are scanned in the zigzag. <tables id="tabl0005" num="0005"><img file="EP0808069A2_D0005.tif" /></tables><tables id="tabl0006" num="0006"><img file="EP0808069A2_D0006.tif" /></tables>

0026The above table 3 shows the inter quantization matrix read from the first and the second sub-RAMs <b>BANK1A, BANK1B</b>. When the count value is 00₁₆, the matrix data couple (00, 01) stored in the area '00' are read by the read address <b>RADD1</b> in the first sub-RAM <b>BANK1A</b>, and the matrix data couple (02, 03) stored in the area '01' are read by the read address <b>RADD2</b> in the second sub-RAM <b>BANK1B</b>. When the count value is 01₁₆, the matrix data couple (02, 03) stored in the area '01' are read by the read address <b>RADD1</b> in the first sub-RAM <b>BANK1A</b>, and the matrix data couple (08, 09) stored in the area '04' are read by the read address <b>RADD2</b> in the second sub-RAM <b>BANK1B</b>. Namely, matrix data couples that are stored in the areas of the first and the second sub-RAM <b>BANK1A, BANK1B</b> indicated by each read address <b>RADD1, RADD2</b>, are read in the same order as shown in Fig. 3B according to the count values 00₁₆ - 1F₁₆ of the second counter <b>51</b>. In the same manner, for the intra quantization matrix, matrix data couples that are stored in the areas of the third and the fourth sub-RAM <b>BANK2A, BANK2B</b> indicated by each read address <b>RADD1, RADD2</b>, are read in the same order as shown in Fig. 3B according to the count values 00₁₆ - 1F₁₆ of the second counter 51.

0027In the multiplexer <b>53</b>, the read address of the zigzag order <b>RADD0</b> or the read address of the alternate order <b>RADD1, RADD2</b> from the PLA <b>52</b> is outputted selectively to the RAM <b>42</b> according to a scanning manner discriminating signal <b>ZZ/ALTER</b> from the system control unit (not shown). For example, the read address <b>RADD0</b> of zigzag order, as shown in the table 2, from the PLA <b>52</b> is selected by the first multiplexer <b>53</b> when the DCT coefficients are scanned in the zigzag manner. The selected read address <b>RADD0</b> is supplied to the corresponding bank in the RAM <b>42</b>. Meanwhile, the read address <b>RADD1, RADD2</b> of alternate order, as shown in table 3, from PLA <b>52</b> are selected by the first multiplexer <b>53</b> when the DCT coefficients are scanned in the alternate manner. The selected read address <b>RADD1, RADD2</b> are supplied to the corresponding bank in the RAM <b>42</b>.

0028In the second multiplexer <b>54</b>, according to a coding mode discriminating signal <b>INTER/INTRA</b> from the system control unit (not shown), the output data <b>DATA1A, DATA1B</b> of the first and the second sub-RAMs <b>BANK1A, BANK1B</b> are selected for the inter mode coding, whereas the output data <b>DATA2A, DATA2B</b> of the third and the fourth sub-RAMs <b>BANK2A, BANK2B</b> are selected for the intra mode coding.

0029In the packing unit <b>55</b>, upper and lower bits of two couples of 16 bit matrix data are combined selectively as 16 bit matrix couple data. The packed 16 bit matrix couple data are synchronized with the count value of the second counter <b>51</b> and they are outputted to the arithmetic controller <b>46</b>. The following table 4 shows examples of data combination when the coding mode of the DCT coefficients is the inter coding and the scanning manner is the zigzag scanning. <tables id="tabl0007" num="0007"><img file="EP0808069A2_D0007.tif" /></tables><tables id="tabl0008" num="0008"><img file="EP0808069A2_D0008.tif" /></tables>

0030Furthermore, the following table 5 shows examples when the coding mode of the DCT coefficients is the inter coding and the scanning manner is the alternate scanning. <tables id="tabl0009" num="0009"><img file="EP0808069A2_D0009.tif" /></tables><tables id="tabl0010" num="0010"><img file="EP0808069A2_D0010.tif" /></tables>

0031The arithmetic controller <b>46</b> is operated according to the system clock <b>CLK</b> and the reset signal <b>RST</b>. The quantization matrix from the RAM controller <b>44</b> is inputted in the arithmetic controller <b>46</b> and its reciprocal value is calculated. Additionally, the quantization type <b>QUANT_SCALE_TYPE</b> and the quantization code <b>QUANT SCALE CODE</b> signal from the system control unit (not shown) are inputted from the RAM controller <b>44</b> to the arithmetic controller <b>46</b>. A quantization scale value is obtained by calculating the quantization type <b>QUANT_SCALE_TYPE</b> and the quantization code <b>QUANT_SCALE_CODE</b>. Therefrom, a reciprocal number of the quantization scale value is obtained. A DC value is obtained by a <b>DC_PREC</b> value from the system control unit (not shown). A reciprocal number of the DC value is obtained therefrom. At this time. the quantization matrix value, the quantization scale value, and the DC value containing the reciprocal number, respectively from the arithmetic controller <b>46</b> are outputted to the arithmetic unit <b>48</b>. Furthermore, for the 16 bit matrix couple data, its reciprocal number is obtained in 8 bit units.

0032In the arithmetic unit <b>48</b>, DCT coefficients of 2 pixels <b>DATA_EVEN, DATA ODD</b> are multiplied by the reciprocal number of the quantization scale value from the arithmetic controller <b>46</b>. The calculated value is multiplied by the reciprocal number of the quantization matrix value and a round processing for the value is performed. The quantized data of 2 pixels <b>QUANT_EVEN, QUANT ODD</b> are outputted therefrom. At this time, the calculation in the arithmetic unit <b>48</b> is performed by a pipe line manner. Hence, a processing speed can be improved. Furthermore, the input order of the DCT coefficients and the order of the quantization matrix can be matched to each other according to the scanning manner when quantizing.

0033Thus, according to the first emhodiments of the present invention, the same inter quantization matrix is stored in two sub-RAMs and the same intra quantization matrix is stored in two sub-RAMs, respectively in order of the zigzag scanning manner, thus corresponding quantization matrix is read from a memory without data collision, according to the read address based on the scanned manner of DCT coefficients.

0034Fig. 6 shows a detailed block diagram of a RAM <b>42</b> and a RAM controller <b>44</b> in accordance with a second preferred embodiment. The RAM <b>42</b> comprises a first bank <b>BANK1</b> for storing the inter quantization matrix and a second bank <b>BANK2</b> for storing the intra quantization matrix. The first bank <b>BANK1</b> comprises a first sub-RAM and a second sub-RAM <b>BANK1A, BANK1B</b> having 8 bits x 22 words, and a third sub-RAM <b>BANK1C</b> having 8 bits / 20 words. The second bank BANK2 comprises a fourth sub-RAM <b>BANK2A</b> and a fifth sub-RAM <b>BANK2B</b> having 8 bits X 22 words, and a sixth sub-RAM <b>BANK2C</b> having 8 bits X 20 words.

0035The RAM controller <b>44</b> comprises a write address generator, a first counter <b>60</b> and a first PLA <b>61</b>, for generating a write address to store the inter quantization matrix and the intra quantization matrix into the RAM <b>42</b>; a data divider <b>62</b> for dividing matrix data of ID_CD into a corresponding sub-RAM of each bank; a read address generator, a second counter <b>63</b>, a second PLA <b>64</b>, a third PLA <b>65</b>, and a first multiplexer <b>66</b>, for generating a read address to read a corresponding quantization matrix from the RAM <b>42</b> according to a scanning manner for DCT coefficients; a data combiner, a second multiplexer <b>67</b> and a packing unit <b>68</b>, for combining the matrix data from the RAM <b>42</b> in 16 bits according to a coding mode or the scanning order.

0036Figs. 4 and Fig. 6 will be referred to describe a second embodiment of the present invention in detail. As input/output signals to each block are the same as discussed in the first preferred embodiment, they will be omitted from the following elaboration.

0037In the first bank <b>BANK1</b> of the RAM <b>42</b>, 64 inter quantization matrix data are divided and stored in 8 bit units in 22 areas of the first sub-RAM <b>BANK1A</b>, 22 areas of the second sub-RAM <b>BANK1B</b>, 20 areas of the third sub-RAM <b>BANK1C</b>, respectively. Each area of the first to the third sub-RAMs <b>BANK1A, BANK1B</b>, <b>BANK1C</b> is indicated by the write addresses <b>WADD1, WADD2, WADD3</b>, respectively. For the second bank <b>BANK2</b>, 64 intra quantization matrix data are divided and stored in 8 bit units in 22 areas of the fourth sub-RAM <b>BANK2A</b>, 22 areas of the fifth sub-RAM <b>BANK2B</b>, 20 areas of the sixth sub-RAM <b>BANK2C</b>, respectively. Each area of the fourth to the sixth sub-RAMs <b>BANK2A, BANK2B, BANK2C</b> is indicated by the write addresses <b>WADD1, WADD2, WADD3</b>, respectively. The inter and the intra quantization matrix are supplied from the system control unit (not shown), and they may be an user defined matrix or a default matrix defined by MPEG-2.

0038The RAM controller <b>44</b> is operated by a system clock <b>CLK</b> and a reset signal <b>RST</b> such that the quantization matrixes of ID_CD are stored in corresponding banks of the RAM <b>42</b> according to the write addresses <b>WADD1, WADD2, WADD3</b>. Additionally, the quantization matrixes in the RAM <b>42</b> are read by read addresses <b>RADD1, RADD2, RADD3</b> according to the scanning manner of the DCT coefficients and they are outputted to the arithmetic controller <b>46</b>. Namely, in the RAM controller <b>44</b>, ID_CD is analyzed to identify the quantization matrix type when FLAG_ID is a "high" logic level. The analyzed input quantization matrix is stored in a corresponding sub-RAM of each bank of the RAM <b>42</b>. Additionally, on being synchronized by a macro block start signal mbs, the quantization matrixes in each sub-RAM of the banks are read and outputted to the arithmetic controller <b>46</b>. Each sub-RAM has a control signal for reading and writing (not shown), and a control signal for enabling an output (not shown). The control signals are supplied when the corresponding sub-RAM is selected by the RAM controller <b>44</b>.

0039As illustrated in Fig. 6, the first counter <b>60</b> (5 bits counter) counts 00H to 1F_H according to a clock signal <b>CLK</b> after clearing a count value by reset signal <b>RST</b>. ID_CD are analyzed to identify the inter/intra quantization matrix when FLAG_ID is a "high" logic level. 32 count values are outputted to the first PLA <b>61</b> and the data divider <b>62</b> once ID is identified.

0040In the first PLA <b>61</b>, the writ addresses <b>WADD1, WADD2, WADD3</b> are generated to store the quantization matrix from the system control unit (not shown) in 8bit units in the first to the third sub-RAM <b>BANK1A, BANK1B, BANK3,</b> or the fourth to the sixth sub-RAM <b>BANK2A, BANK2B, BANK2C</b> according to the count value from the first counter <b>60</b>. The first PLA <b>61</b> also generates the read addresses <b>RADD1, RADD2, RADD3</b> when the DCT coefficients are scanned in the zigzag order. The following table 6 illustrates the write addresses <b>WADD1, WADD2, WADD3</b>. <tables id="tabl0011" num="0011"><img file="EP0808069A2_D0011.tif" /></tables><tables id="tabl0012" num="0012"><img file="EP0808069A2_D0012.tif" /></tables>

0041In the data divider <b>62</b>, 16 bit quantization matrix data of the zigzag order as shown in Fig. 3A, are divided to store in two of 3 sub-RAMs in 8 bit units according to the count value from the first counter <b>60</b>. In case of the inter quantization matrix, the 16 bit quantization matrix data are divided to store in the first to the third sub-RAMs <b>BANK1A, BANK1B, BANK1C</b>. In case of the intra quantization matrix, the 16 bit quantization matrix data are divided to store in the fourth to the sixth sub-RAMs <b>BANK2A, BANK2B, BANK2C</b>. The following table 7 illustrates the data division. <tables id="tabl0013" num="0013"><img file="EP0808069A2_D0013.tif" /></tables><tables id="tabl0014" num="0014"><img file="EP0808069A2_D0014.tif" /></tables>

0042The above tables 6 and 7 shows the inter quantization matrix stored in the first to the third sub-RAMs <b>BANK1A, BANKIB, BANK1C.</b> When the count value is 00₁₆, the matrix data (00) are stored in the area of the write address <b>WADD1</b> '00' of the first sub-RAM <b>BANK1A</b> and the matrix data (01) are stored in the area of the write address <b>WADD2</b> '01' of the second sub-RAM <b>BANK1B</b>. When the counter value is 01₁₆, the matrix data (03) are stored in the area of the write address <b>WADD2</b> '01' of the second sub-RAM <b>BANK1B</b> and the matrix data (02) are stored in the area of the write address <b>WADD3</b> '00' of the third sub-RAM BANK1C. Namely, the inter quantization matrix data of the zigzag order in 16 bit units, as in Fig. 3A, are stored in two sub-RAMs of the first to the third sub-RAMs as shown in table 7 in 8 bit units according to the write addresses <b>WADD1, WADD2, WADD3</b>. Similarly, the intra quantization matrix data of the zigzag order in 16 bit units, as in Fig. 3A, are stored in two sub-RAMs of the fourth to the six sub RAMs as shown in table 7 in 8 bit units according to the write addresses <b>WADD1, WADD2, WADD3</b>. At this time, the sub-RAM for allocating the address in the table 6 correspond to the sub-RAM for dividing the data in the table 7 when the count value is the same.

0043The second counter <b>63</b> (5 bit counter) counts 00_H to 1F_H according to the clock signal <b>CLK</b> after clearing the count signal by the reset signal <b>RST</b>. The 32 count values are outputted to the second PLA <b>64</b>, the third PLA <b>65</b>, and the packing unit <b>68</b> after detecting a rising edge of macro block signal <b>mbs</b>.

0044In the second PLA <b>64</b>, the read addresses <b>RADD1, RADD2, RADD3</b> are generated to read the corresponding quantization matrix from the RAM 42 when the DCT coefficients are scanned in the zigzag order. The second PLA <b>64</b> has the same construction as the first PLA <b>61</b>. The read addresses <b>RADD1, RADD2, RADD3</b> like in the following table 8 are generated in the second PLA <b>64</b> according to the count value from the second counter <b>63</b>. <tables id="tabl0015" num="0015"><img file="EP0808069A2_D0015.tif" /></tables><tables id="tabl0016" num="0016"><img file="EP0808069A2_D0016.tif" /></tables>

0045In the third PLA <b>65</b>, the read addresses <b>RADD1, RADD2, RADD3</b> are generated to read the corresponding quantization matrix from the RAM <b>42</b> when the DCT coefficients are scanned in the alternate order. The read addresses <b>RADD1</b>, <b>RADD2, RADD3</b> like the following table 9 are generated in the third PLA 65 according to the count value from the second counter <b>63</b>. <tables id="tabl0017" num="0017"><img file="EP0808069A2_D0017.tif" /></tables><tables id="tabl0018" num="0018"><img file="EP0808069A2_D0018.tif" /></tables>

0046The above table 9 shows the inter quantization matrix data read from the first to the third sub-RAMs <b>BANK1A, BANK1B, BANK1C</b>. When the count value is 00₁₆, the read address <b>RADD1</b> is generated to read the data (00) stored in the write address '00' from the first sub-RAM <b>BANK1A</b>, and the read address <b>RADD3</b> is generated to read the data (02) stored in the write address '00' from the third sub-RAM <b>BANK1C</b>. In addition, when the count value is 01₁₆, the read address <b>RADD2</b> is generated to read the data (03) stored in the write address '01' from the second sub-RAM <b>BANK1B</b>, and the read address <b>RADD3</b> is generated to read the data (09) stored in the write address '02' from the third sub-RAM <b>BANK1C</b>. Namely, the matrix data, which are stored in the areas of the first to the third sub-RAMs <b>BANK1A, BANK1B, BANK1C</b> indicated respectively by the read addresses <b>RADD1, RADD2, RADD3</b>, are read in the order shown in Fig. 3B according to the count values 00₁₆, - 1F₁₆. In the same manner, in case of the intra quantization, the matrix data, which are stored in the areas of the fourth to the sixth sub-RAMs <b>BANK2A, BANK2B, BANK2C</b> indicated respectively by the read addresses <b>RADD1, RADD2, RADD3</b>, are read in the order shown in Fig. 3B according to the count values 00₁₆ - 1F₁₆. As described above, the read address from the third PLA <b>65</b> is not sequential for reading the matrix data of the zigzag order in 3 sub-RAMs in the alternate order. For this reason, a matrix data is distributed and stored in two of 3 sub-RAMs by write address generated in the first PLA <b>61</b> such that the data collision phenomenon does not occur when a couple of matrix data are read by the read address generated in the third PLA <b>65</b> according to a scanning manner.

0047In the first multiplexer <b>66</b>, the read addresses <b>RADD1, RADD2, RADD3</b> of the zigzag order, or the read addresses <b>RADD1, RADD2, RADD3</b> of the alternate order are outputted selectively to the RAM <b>42</b> according to the scanned manner discriminating signa! <b>ZZ/ALTER</b> from the system control unit (not shown). For example, in the first multiplexer <b>66</b>, the read addresses <b>RADD1, RADD2, RADD3</b> of the zigzag order from the second PLA <b>64</b> like the table 8 are supplied selectively to the corresponding bank of the RAM <b>42</b> when the DCT coefficients are scanned in the zigzag manner. Meanwhile, in the first multiplexer <b>66</b>, the read addresses <b>RADD1, RADD2, RADD3</b> of the alternate order from the third PLA <b>65</b> like the table 9 are supplied selectively to the corresponding bank of the RAM <b>42</b> when the DCT coefficients are scanned in the alternating manner.

0048In the second multiplexer <b>67</b>, according to the code mode discriminating signal <b>INTER/INTRA</b> from the system control unit (not shown), the output data <b>DATA1A</b>, <b>DATA1B, DATA1C</b> of the first to the third sub-RAMs <b>BANK1A, BANK1B, BANK1C</b> are outputted selectively for the inter coding mode, and the output data <b>DATA2A</b>, <b>DATA2B, DATA2C</b> of the fourth to the sixth sub-RAMs <b>BANK2A, BANK2B, BANK2C</b> are outputted selectively for the intra coding mode.

0049In the packing unit <b>68</b>, two couples of 8 bit matrix data from the second multiplexer <b>67</b> are combined as 16 bit matrix couple data. The data are synchronized to the count value of the second counter <b>63</b> and they are outputted to the arithmetic controller <b>46</b>. The following table 10 shows the case that the coding mode of the DCT coefficients is the inter coding and its scanning manner is of zigzag scanning. <tables id="tabl0019" num="0019"><img file="EP0808069A2_D0019.tif" /></tables><tables id="tabl0020" num="0020"><img file="EP0808069A2_D0020.tif" /></tables>

0050Furthermore, the following table 11 shows the case that the coding mode of the DCT coefficients is the inter coding and its scanning manner is of alternate scanning. <tables id="tabl0021" num="0021"><img file="EP0808069A2_D0021.tif" /></tables><tables id="tabl0022" num="0022"><img file="EP0808069A2_D0022.tif" /></tables>

0051Here, the discussion of the arithmetic controller <b>46</b> and the arithmetic unit <b>48</b> is omitted since the operating procedures are same as described in the first embodiments.

0052Thus, according to the second embodiments of the present invention, 32 quantization matrix data of 16 bits unit are distributed and stored in two of 3 sub-RAMs in order of the zigzag scanning manner in unit of 8 bits. thus corresponding quantization matrix is read from a memory without data collision, according to the read address based on the scanned manner of DCT coefficients.

0053While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.