Method and device for connecting synchronisation errors

Disclosed viewing on a television screen, for example, auxiliary information such as teletext data types, VPS (Video Programming System in English) or WSS (Wide Screen Signaling in English) transmitted on predefined lines of the VBI (Vertical Blanking Interval in English).

The invention particularly relates to a method and a device for correcting timing errors of the auxiliary data sequences recovery operations transmitted on the invisible lines of the VBI of a video signal having a vertical synchronizing signal Vsync and a synchronization signal horizontal Hsync. Said Hsync and Vsync signals are used for synchronizing the opening of time windows for recovery of said data.

Vsync signal comprises a periodic succession of crenellations v each having a duration equal to the duration of a video frame while the Hsync signal comprises a periodic succession of pulses h of duration approximately 4 microseconds.

It is well known in the field of transmissions of television programs using predefined VBI lines to transmit data representing either of TELETEXT data types (inforrnations of all kinds such as weather or news, or information on the stock market), or VPS type enabling to program the recording start a program on a VCR or the time of automatic channel change, or the type Closed caption (caption accompanying programs to the attention of the hearing impaired).

The circuits used to extract this information from the video signal must be able to accurately detect the VBI lines containing auxiliary data and the time of occurrence of said data on each detected VBI line. A known solution in the prior art consists in using a line counter which is reset at the beginning of each video frame and whose counting is synchronized with the beginning of each video line. A suitable decoder is used to generate time windows for recovering ancillary data. Generally, the moment of opening a window is delayed from the start of a video line so prevent sinusoidal signals on each line such as, for example synchronizer color signal (color burst in English) be recovered.

Recovering auxiliary data therefore requires a vertical synchronization signal for determining the line of the VBI to explore and a horizontal synchronizing signal for opening at the predetermined appropriate time, the time windows for recovering ancillary data present on the online explored. In known manner, said synchronization signals are generally obtained from the line synchronizing signal and frame synchronizing signal transmitted with the video signal. Obtaining the vertical synchronization signal Vsync is performed easily by a known digital integration technique, while the horizontal synchronizing signal Hsync is obtained, so also known, through eg threshold detector and thus that its quality is closely related to the quality of the transmitted video signal. Indeed, if the transmitted video signal is of poor quality, the synchronization signals may suffer damage that make their random detection. This can cause errors of synchronization sequences recovering auxiliary data. These errors may be either the absence of horizontal synchronizing pulse, or in a presence of one or more erroneous additional pulses.

The object of the invention is to detect synchronization errors can cause loss of auxiliary information and to correct said errors quickly and automatically.

According to the method of the invention, in case of absence of a horizontal synchronization pulse at the end of a period equal to H + .DELTA.h, where H is the period of the signal Hsync and .DELTA.h is a first predetermined time period, a ha artificial synchronization pulse is generated.

Thus, the auxiliary data recovery operation is less sensitive to any disturbance likely to deteriorate the quality of the transmitted signal.

According to a first feature of the method of the invention, upon detection of a horizontal synchronizing pulse h, generates a masking signal of any signal capable of being detected during a period M equal to H-ΔH1, ΔH1 is where a second predetermined period of time.

Thus, the effects of additional pulses that may cause a synchronization error are systematically inhibited.

According to an essential characteristic of the process of the invention, in case of artificial synchronization is shifted in time the instant of opening of the auxiliary data recovery window so as to coincide with said time the beginning of the data sequence auxiliary to recover.

This offset is to open the time window at the end of a duration of at least three times the time .DELTA.h microseconds. Of course, this duration may be selected in a programmed manner based on the synchronization delay introduced by the absence of a pulse h.

The method according to the invention is implemented by means of a device comprising a threshold detector which receives a signal CVBS (Composite Video Baseband Signal English) and outputs a composite synchronizing signal Csync to a digital calculation unit designed extracting the vertical synchronization signal Vsync and horizontal HSYNC said composite signal Csync.

According to the invention, the digital calculation unit further includes multiplexing means for selecting from at least two different moment, a moment of opening of a time window for recovering the ancillary data contained in a line explored.

Other features and advantages of the invention emerge from the description which follows, taken by way of nonlimiting example, with reference to the appended figures in which:<ul><li>Figure 1 and Figure 2 are timing diagrams illustrating the extraction of a horizontal synchronizing signal Hsync from a composite signal Csync of the invention.</li><li>3 shows a timing diagram partially illustrating the extraction of a vertical synchronizing signal Vsync from the composite signal Csync of the invention.</li><li>4 shows block diagram of an auxiliary data recovery device according to the invention.</li><li>5 schematically shows a preferred embodiment of the apparatus of Figure 4.</li><li>6 shows examples of time slots auxiliary data recovery obtained by the process according to the invention.</li></ul>

Figure 1 shows a timing diagram showing part of a first step of a method of correcting timing errors auxiliary data recovery operations transmitted over the VBI invisible lines of a video signal carrying an image to be displayed on a screen. This video signal comprises a Vsync signal consisting of a periodic sequence of vertical synchronization slots v and a Hsync signal formed by a periodic succession of pulses of horizontal synchronizing h. Said Vsync and Hsync signals are used to synchronize circuits performing the opening of time windows for recovery of said auxiliary data on a scanned line.

As can be seen in Figure 1, the Hsync signal has a period M equal to the duration of a video line. The h2 pulse, shown in dotted illustrates an undetected pulse. In this case, after a period equal to H + DH, an artificial synchronization pulse ha is generated, where DH is a first predetermined time period. In addition, upon detection of a horizontal synchronizing pulse h, generates a signal masking any signal liable to be detected during a period M equal to H-ΔH1, ΔH1 which is a second predetermined time.

According to a preferred embodiment of the inventive method, the time .DELTA.h equals 4 microseconds and ΔH1 is equal to .DELTA.h / 2.

According to an essential characteristic of the process of the invention, in case of generation of an artificial synchronization pulse ha, shifting the instant of opening of the auxiliary data recovery window so as to coincide said opening timing with the beginning of the ancillary data sequence to recover.

Note that this step occurs in the case where a h synchronizing pulse is absent, as illustrated by Figure 1, and in the case where said h pulse is detected with a time delay.

As can be seen in Figure 1, the pulse generation h is synchronized to the falling edge of the composite signal Csync. Thus, upon the occurrence of a falling edge of the Csync signal, a pulse h1 and a first masking SM1 slots are generated. In case of generation of an artificial synchronization pulse is reduced the length M of the masking SM1 slot so as to avoid masking the correct horizontal synchronization pulse h2 following the missing horizontal synchronization pulse. In the case illustrated by Figure 1, where said next pulse h2 is not detected, and where an artificial pulse ha is generated, a second SM2 masking window is generated synchronously with the rising edge of the artificial pulse ha . The duration of SM2 slots is less than the first SM1 niche so as not to mask the following pulse h3.

In another step of the invention process, we define a quality criterion of the VBI lines pursuant to which the auxiliary data on a given line of the VBI will be recovered or abandoned. According to said quality criterion, upon detection of more than one pulse h during the masking period M, and in case of no detection pulse h during the period H + .DELTA.h, generating a pulse indication BTL an erroneous line. The number of pulses BTL is then sent to an acquisition unit, not shown, in charge of counting the number of detected incorrect lines. Note however that BTL pulse is generated at each detection of a half-line synchronization pulse, although the line scanned is not erroneous as shown in Figure 2. The number of pulses thus generated depends BTL the television standard used. The example of Figure 2 corresponds to the PAL standard in which the composite synchronization signal comprises nine half-line synchronization pulses I1, I2, I3, I4, I5, I6, I7, I8 and I9 to the odd field, and nine half-line synchronization pulses P1, P2, P3, P4, P5, P6, P7, P8 and P9 for the even field. In effect, the pulses I3, I5, I7 and I9 are generated during the masking period and thus produce BTL3 pulses respectively BTL5, BTL7 and BTL9. Similarly, the pulses P2, P4, P6 and P8 are also generated during the masking period and produce pulses respectively B2, B4, B6 and B8. The appearance of said BTL3 pulses BTL5, BTL7 and BTL9 well as BTL2 pulses BTL4, BTL6 BTL8 and does not correspond to the detection of errors within the meaning of the quality test in the process of the invention. Therefore the number of said pulses is deducted by the acquisition unit, the total number of errors that is provided.

Note that the detection of a half-line during the VBI causes the loss of a HSYNC pulse and therefore a one-line shift in the current frame. In this case, a correct resynchronization is automatically recovered after a number of video line which depends on the time .DELTA.h. By choosing .DELTA.h equal to 4μs, resynchronization is achieved after a period of eight video lines.

The method according to the invention is implemented by means of a device comprising a threshold detector 2 which receives a CVBS signal and outputs a composite synchronizing signal Csync to a digital computation unit 4 for extracting the vertical synchronization signals Vsync and horizontal Hsync said composite signal Csync. Said device further comprises a module 6 of VBI lines of detection comprising auxiliary data. According to an essential characteristic of the inventive device, said digital calculation unit 4 comprises, in addition, 7 multiplexing means for selecting from at least two different instants, an opening timing of a time window for recovering auxiliary data contained in a scanned line.

The selected time is previously determined using the module 6 line selection. The latter comprises a first counter 8 for pointing the line of VBI to explore, and a second counter 9 for determining the moment of opening of a time window in the dotted line. Said second counter 9 receives clock pulses at a frequency dependent on the desired or required resolution and determines, by counting said clock pulse, a time after which a window should be opened. This frequency may be 1 MHz for example. The period after which a window is to be opened is determined from the beginning of the explored VBI line. At the end of said line counter 8 is incremented by one line and the counter 9 is reset.

As can be seen from Figure 5 showing a preferred embodiment of the device implementing the method of the invention, the digital calculation unit 4 comprises two blocks operating in parallel, a first block 12 dedicated to the extraction the vertical synchronizing signal Vsync and a second block dedicated to the extraction of the horizontal synchronization signal Hsync, said first and second blocks are connected to an output S of the threshold detector 2, whereas the respective outputs of said first and second blocks are connected respectively to a first input e1 and e2 to a second input of a logic aND gate with the reference 16.

The first block 12 comprises a digital integrator 20 having an input connected to the output S of the threshold detector 2 and an output connected to a CLR input of reset of the first counter 8. The output of said first counter 8 is connected via a row decoder 22, the first entry e1 of the logic gate 16.

The second block comprises a separation means 24 of the Hsync signal having an input connected to the output S of the threshold detector 2 and a first output 26 connected to a first input 28 of the multiplexing means 7 while a second outlet 30 is connected on the one hand, to an input 32 of the first counter 8, and secondly, to a CLR1 input resetting the second counter 9. the latter receives periodic pulses supplied by a clock, not shown, and delivers the multiplexing means 7 at least two numerical values ​​respectively representing a first time prior WIN1 at a second time WIN2 opening auxiliary data recovery window.

The multiplexing means 7 includes a decoder 40 adapted to decode yet WIN1 and a decoder 42 adapted to decode yet WIN2.

In operation, the threshold detector 2 receives the signal CVBS (Composite Video Baseband Signal) and delivers the composite sync signal Csync including the vertical synchronization signals Vsync and horizontal Hsync. Said Vsync and Hsync signals are then extracts the Csync signal respectively in the first block 12 and second block 14. As previously mentioned, the extraction of the signal Vsync is performed, in known manner, by the integrator 20. the digital signal Vsync is then used to synchronize the reset of the first counter 8 line at the end of each frame of the transmitted image.

So when the first counter 8 detects VBI line, the second counter 9 determines, by counting the clock pulses, the time from which a time window must be open. Said time is transmitted to the multiplexing means 7 which simultaneously receives a TB control signal delivered by the separation means 24 of the signal Hsync. In case of an error due to the absence of pulse h after a duration of 68 microseconds, the separation means 24 consignment multiplexing means 7 a TO command signal for advancing the time of opening of the time window by activating a decoder 40. the latter decodes the first moment WIN1 allowing reflect the delay resulting from the absence of a pulse h and its replacement, 4μs later by a pulse ha. The digital value selected by the multiplexing means 7 is then sent to the second input e2 of the logic gate 16. The output of the logic gate 16 provides a time window for recovering ancillary data which are on the line of the VBI which number is provided by the line decoder 22 to the first entry e1 of the logic gate 16.

Figure 6 illustrates some examples of device uses the invention for generating time windows Auxiliary data recovery TXT-SW, SW-VPS and WSS-SW TELETEXT kind respectively, VPS and WSS.