A system for DC restoration of serially transmitted binary signals

This invention relates to direct current (DC) restoration of serially transmitted binary signals. More particularly, the invention relates to a hysteretic bipolar clamp DC restorer circuit particularly suited for use with automatic co-axial cable equalizers.

<u>BACKGROUND OF THE INVENTION</u>

In signal transmission applications where the average or DC component of a serially transmitted binary signal is non-zero, the DC component of the signal must be restored at the receiver in order to achieve accurate data reproduction. Where the transmission medium is a coaxial cable which includes AC coupling methods for signal transmission, there are two steps required to recover the transmitted data. The first step involves high frequency equalization to compensate for losses during transmission in the cable. The second step involves DC restoration of the equalized signal to recover the low frequency and DC components which are lost through the coupling circuits.

Quantized Feedback (QFB) is the standard technique for DC restoration of an AC coupled binary signal. The Quantized Feedback method has been utilized in practical implementations for cable equalizers for serial digital transmission applications. However, the Quantized Feedback method is sensitive to variations in the amplitude and rise time of the input waveform. As will be appreciated by one skilled in the art, this sensitivity places considerable emphasis on the performance of the high frequency equalizer because as the length of the transmission cable increases, the signal losses become more severe and precise equalization will eventually be impossible.As a result of this sensitivity, the Quantized Feedback method can introduce jitter into the restored waveform.

The present invention provides a new approach to DC restoration which, unlike the Quantized Feedback technique, can operate correctly over a wide variation of input signal quality, and therefore is inherently better suited for the role of DC restorer in cable equalizers.

In a first aspect, the present invention provides a device for restoring a binary signal having a DC value, the binary signal being coupled to said device by a capacitor, said device comprising: an input port coupled to the capacitor for receiving the binary signal and producing a coupled binary signal; clamping means for clamping the coupled binary signal when said coupled binary signal exceeds a predetermined range, said clamping means being connected to the capacitor; means for generating a signal component, said means for generating being coupled between the capacitor and the output of the device, said signal component corresponding to the DC value of said coupled binary signal; summing means for adding said signal component to the coupled binary signal to produce a restored binary signal, said summing means being connected to said means for generating and to the capacitor; and means for outputting the restored binary signal, said means for outputting being connected to said summing means.

In a second aspect the present invention provides a method for restoring a binary signal having a DC value, the binary signal being coupled through a capacitor, said method comprising the steps of: inputting the binary signal through the capacitor to produce a coupled binary signal; clamping said coupled binary signal when said coupled binary signal exceeds a predetermined range; generating a signal component corresponding to the DC value of said coupled binary signal; and summing said signal component to said coupled binary signal to produce a restored binary signal.

For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings which show a preferred embodiment of the present invention. <ul id="ul0001" list-style="none" compact="compact"><li>Figure 1 shows a typical co-axial transmission system in simplified block diagram form;</li><li>Figure 2(a) shows a typical binary signal (input waveform) prior to AC coupling;</li><li>Figure 2(b) shows the binary signal (of Figure 2(a)) after AC coupling;</li><li>Figure 3 shows a known system utilizing the Quantized Feedback method (prior art);</li><li>Figure 4 shows in block diagram form a hysteretic bipolar clamp DC restorer according to the present invention;</li><li>Figure 5 shows in schematic form the hysteretic bipolar clamp DC restorer of Figure 4;</li><li>Figure 6(a) shows a binary signal which has been subject to coaxial cable transmission and AC coupling;</li><li>Figure 6(b) shows the intermediate restoration of the binary signal (of Figure 6(a)) according to the present invention;</li><li>Figure 6(c) shows the complete restoration of the binary signal (of Figure 6(a)) according to the present invention;</li><li>Figure 7 shows in block form an improved cable equalizer utilizing a second embodiment of a hysteretic bipolar clamp DC restorer according to the present invention;</li><li>Figure 8 shows a circuit for the DC restorer of Figure 7 which is integrated with the automatic gain controller; and</li><li>Figures 9(a)-(e) show the various voltage and current waveforms associated with the clamping circuit of the hysteric bipolar clamp DC restorer of Figure 8.</li></ul>

<u>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS</u>

The transmission of serial encoded binary data requires a transmission medium with a wide bandwidth, since the frequency content of such signals is broad. Co-axial cables are utilized as the transmission medium in typical data transmission systems.

Figure 1 shows a typical known transmission system 1 in simplified block diagram form. The system 1 comprises a transmitter 2 and a receiver 4. The transmitter 2 and receiver 4 are coupled together by a co-axial cable 6 which serves as the transmission medium. In known manner, the transmitter 2 includes electronic circuitry (not shown) for encoding the information to be transmitted into serial binary data. Similarly, the receiver 4 includes circuitry (not shown) for decoding (e.g. demodulating) the transmitted serial binary data. In a system 1 where the co-axial cable 6 is AC coupled, the receiver 4 will include a cable equalizer circuit 7 which comprises a restoration circuit 8 and a high frequency equalizer 9. The function of the restoration circuit 8 is to recover the low frequency and DC components of the serial binary signal. The low frequency and DC components of the serial signal are lost through the AC coupling circuits (not shown) as will be understood by one skilled in the art. Before describing the restoration circuit 8 according to the present invention, a typical known restoration method and system will be discussed.

The Quantized Feedback method is a known standard technique for DC restoration of an AC coupled binary signal. In the following description, DC and AC refer to direct current and alternating current respectively. As will be shown below, the Quantized Feedback (QFB) method is sensitive to variations in the amplitude and rise time of the input binary signal waveform. This sensitivity places considerable demands on the high frequency equalizer 9, which as is known compensates for losses in the cable by restoring the amplitude of the binary signal. It will be appreciated by one skilled in the art that as the length of the co-axial cable increases, the signal losses become more severe and precise performance by the high frequency equalizer 9 is no longer possible. Thus, there will be a performance loss for the QFB method when utilized in cable equalizer 7 applications. Before explaining the details of the present invention, the Quantized Feedback method and its sensitivity to the shape of the input waveform will be considered in greater detail.

The serial binary signal (not shown in Figure 1) which is transmitted by the co-axial cable 6 is received by the receiver 4 as an input binary signal. Figure 2(a) depicts an input binary signal V_IN prior to AC coupling and Figure 2(b) shows an AC coupled binary signal waveform V_AC which represents the input binary signal V_IN subsequent to AC coupling. It will be appreciated by those skilled in the art that AC coupling techniques involve using a coupling capacitor (not shown) and such techniques are common features of co-axial transmission systems.

Referring to Figure 2(a), the input binary signal V_IN is shown as having a logic '1' defined by the voltage level +V₁, and a logic '0' defined by a voltage level -V₁, and a threshold voltage V_TH. The threshold voltage V_TH is the voltage level which defines the transition between the logic 1 level and the logic 0 level or vice versa. As shown in Figure 2(a), the threshold voltage V_TH for the input binary signal V_IN is taken as the mid-point between the logic 1 and logic 0 levels, which in this case is zero volts. The input binary signal V_IN also has a period T and a duty cycle D. The duty cycle is defined as the duration of the logic '1' pulse, denoted by T_H, divided by the period of the binary signal V_IN, denoted by T.

A consequence of AC coupling is the loss of the low frequency and the DC components in the input binary signal V_IN. The loss of the DC component can lead to two other effects. First, the loss of the DC component due to AC coupling can change the duty cycle D which results in jitter. Secondly, the AC coupling can also lower the noise margin of the input binary signal V_IN. The effects of AC coupling on the duty cycle and noise margin will be considered with reference to the AC coupled binary signal shown in Figure 2(b).

In Figure 2(b), AC coupling of the input binary signal V_IN introduces a DC offset voltage V_OS. The DC offset voltage V_OS is the difference between the threshold voltage V_TH of the input binary signal V_IN and the mid-way point of the AC coupled binary signal V_AC. Furthermore, as a result of the DC offset voltage, the logic '1' level for the AC coupled binary signal is defined by a voltage level which is the sum of +V₁ and V_OS. Similarly, the logic '0' level for the AC coupled binary signal is defined by a voltage level which is the sum of -V₁ and V_OS. As shown in Figure 2(b), the DC offset voltage V_OS also changes the duty cycle of the AC coupled binary signal by altering the duration T_H of the logic '1' pulse.

The effect of AC coupling and the resultant DC offset voltage V_OS will be illustrated by considering the steady state condition. In the steady state condition, the net current flowing into the coupling capacitor (not shown) must be zero. This condition can also be expressed by saying that the integral of the AC coupled binary signal V_AC (Figure 2(b)) over one cycle is zero. Using this property of the steady state condition, an expression (1) for determining the off-set voltage V_OS as a function of the duty cycle D can be derived. The off-set voltage V_OS is the difference between the original threshold voltage V_TH (i.e. zero volts in this case) and the threshold voltage of the AC coupled binary signal V_AC of Figure 2(b). (Taken as the mid-point between the logic '1' and logic '0' levels.)<maths id="math0001" num="(1)"><math display="block"><mrow><msub><mrow><mtext>V</mtext></mrow><mrow><mtext>OS</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> * (1 - 2*D)</mtext></mrow></math><img file="EP0611059B1_D0001.tif" /></maths> In the above expression, the AC coupled binary signal V_AC is expressed as a function of the duty-cycle D. As is known, it is desirable to eliminate the off-set voltage V_OS because it can lower the noise margin. Furthermore, in practical systems where there are finite rise and fall times, the off-set voltage V_OS changes the duty-cycle of the input binary signal V_IN which results in jitter.

The jitter problem can be illustrated by considering the duty-cycle D of the original input binary signal V_IN and the AC coupled binary signal V_AC shown in Figures 2(a) and 2(b) respectively. Assuming that the input binary signal V_IN has equal rise and fall times, denoted by T_S, then the following expression (2) for the duty-cycle D' of the AC coupled binary signal V_AC can be derived.<maths id="math0002" num="(2)"><math display="block"><mrow><msub><mrow><mtext>D' = D + (V</mtext></mrow><mrow><mtext>OS</mtext></mrow></msub><msub><mrow><mtext>/V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>) * (T</mtext></mrow><mrow><mtext>S</mtext></mrow></msub><mtext>/T)</mtext></mrow></math><img file="EP0611059B1_D0002.tif" /></maths> Substituting expression (1) for the off-set voltage V_OS derived above, the duty-cycle D' for the AC coupled binary signal V_AC can be rewritten as:<maths id="math0003" num="(3)"><math display="block"><mrow><msub><mrow><mtext>D' = D + (1 - 2*D) * (T</mtext></mrow><mrow><mtext>S</mtext></mrow></msub><mtext>/T)</mtext></mrow></math><img file="EP0611059B1_D0003.tif" /></maths> It can be seen from the above expressions (2) and (3) that there will be zero jitter (i.e. duty-cycle D = duty-cycle D'), if either the rise-time T_S is zero, or the duty-cycle D of the input binary signal V_IN is 0.5. It will therefore be appreciated that a small rise-time T_S in the input binary signal V_IN can help reduce the jitter caused by AC coupling. However, a small rise-time T_S has no effect on the diminished noise margin which is another by-product of the off-set voltage V_OS.

<u>The Quantized Feedback Method (Prior Art)</u>

The Quantized Feedback (QFB) method is one known technique which is used for DC restoration of serially transmitted binary signals. The QFB achieves DC restoration by reducing the offset voltage V_OS to as small a voltage as practically possible. Figure 3 shows a typical known Quantized Feedback (QFB) system indicated by reference 20. The QFB system 20 restores the DC component in the AC coupled binary signal V_AC to produce a DC restored output signal V_Q. The following discussion will demonstrate that while the QFB system of Figure 3 reduces the offset voltage V_OS, it can contribute to jitter in the restored output signal V_Q, and the jitter is proportional to both the error between the amplitude of the input binary signal V₁ and the amplitude of the comparator output signal V₂, and the rise time T_S of the input signal.

The Quantized Feedback system 20 shown in Figure 3 comprises a voltage comparator 22, an input RC network 24, a feedback loop RC network 26, and a summation unit 28. The input RC network 24, provides one of the inputs to the summation unit 28 and couples the binary signal V_IN to the QFB system 20 through a coupling capacitor 30. The other input for the summation unit 28 is derived from the feedback loop RC network 26, which in turn is coupled to the output of the voltage comparator 22. In known manner, the voltage comparator 22 produces an output voltage signal V_C. The feedback loop RC network 26 then filters the output voltage V_C to produce a feedback voltage signal V_FB which provides the other input to the summation unit 28. The summation unit 28 adds the voltage feedback signal V_FB to the AC coupled signal V_AC that is derived from the input binary signal V_IN (i.e. the input binary signal V_IN has been integrated using the input RC network 24). The output of the summation unit 28 is the restored voltage signal V_Q which is the sum of the AC coupled voltage signal V_AC and the feedback voltage signal V_FB. Therefore, the function of the prior art QFB system shown in Figure 3 is to reduce the off-set voltage V_OS by adding the voltage feedback signal V_FB to the AC coupled binary signal V_AC.

The following discussion will demonstrate that the known Quantized Feedback system 20 shown in Figure 3 introduces jitter. The jitter is proportional to both the error between the amplitude of the input binary signal V_IN and the comparator output signal V_C, and the rise time T_S of the input binary signal V_IN.

In the Quantized Feedback system 20 shown in Figure 3, the input RC network 24 has the same time constant as the feedback loop RC network 26 (which provides a low pass filter function). To simplify the following analysis, the time constant for the input RC network 24 and the feedback loop RC network 26 are assumed to be large so that the feedback voltage signal V_FB can be considered to be a DC quantity. In known manner, the feedback voltage signal V_FB can be expressed in terms of the output voltage V_C of the comparator 22 and the duty-cycle D_Q of the DC restored output signal V_Q from the summation unit 28 as follows:<maths id="math0004" num="(4)"><math display="block"><mrow><msub><mrow><mtext>V</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>C</mtext></mrow></msub><msub><mrow><mtext> * (2 * D</mtext></mrow><mrow><mtext>Q</mtext></mrow></msub><mtext> -1)</mtext></mrow></math><img file="EP0611059B1_D0004.tif" /></maths>    where D_Q is the duty-cycle of the DC restored output signal V_Q. As shown previously, the steady state AC coupled binary signal V_AC can be expressed as the sum of the original binary signal V_IN and the offset voltage V_OS, and using this property the following expression for the DC restored output signal V_Q can be written:<maths id="math0005" num="(5)"><math display="block"><mrow><msub><mrow><mtext>V</mtext></mrow><mrow><mtext>Q</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>IN</mtext></mrow></msub><msub><mrow><mtext> + V</mtext></mrow><mrow><mtext>OS</mtext></mrow></msub><msub><mrow><mtext> + V</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><mspace linebreak="newline" /><msub><mrow><mtext> (i.e. V</mtext></mrow><mrow><mtext>AC</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>IN</mtext></mrow></msub><msub><mrow><mtext> + V</mtext></mrow><mrow><mtext>OS</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0611059B1_D0005.tif" /></maths> and the duty-cycle D_Q of the DC restored output signal V_Q can also be expressed as follows: (where V₁ is the amplitude of V_IN; V₂ is the amplitude of V_C)<maths id="math0006" num="(6)"><math display="block"><mrow><msub><mrow><mtext>D</mtext></mrow><mrow><mtext>Q</mtext></mrow></msub><msub><mrow><mtext> = D + ((V</mtext></mrow><mrow><mtext>OS</mtext></mrow></msub><msub><mrow><mtext> + V</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><msub><mrow><mtext>)/V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>) * (T</mtext></mrow><mrow><mtext>S</mtext></mrow></msub><mtext>/T)</mtext></mrow></math><img file="EP0611059B1_D0006.tif" /></maths> Substituting expression (1) for the offset voltage V_OS and expression (4) for the feedback voltage V_FB into expression (6) above, expression (7) can be derived for the duty-cycle D_Q of the DC restored output signal V_Q:<maths id="math0007" num="(7)"><math display="block"><mrow><msub><mrow><mtext>D</mtext></mrow><mrow><mtext>Q</mtext></mrow></msub><mtext> = </mtext><mfrac><mrow><msub><mrow><mtext>D * (1-2*T</mtext></mrow><mrow><mtext>S</mtext></mrow></msub><msub><mrow><mtext>/T) + (1-V</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>/V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>) * T</mtext></mrow><mrow><mtext>S</mtext></mrow></msub><mtext>/T</mtext></mrow><mrow><msub><mrow><mtext>(1-(V</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>/V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>) * (2*T</mtext></mrow><mrow><mtext>S</mtext></mrow></msub><mtext>/T))</mtext></mrow></mfrac></mrow></math><img file="EP0611059B1_D0007.tif" /></maths> From the two above expressions for duty-cycle D_Q, i.e. (6) and (7), it can be seen that the condition for zero jitter, i.e. D_Q = D , is either the requirement that the amplitude V₁ of the input binary signal V_IN is equal to the amplitude V₂ of the comparator output signal V_C, or that the rise time T_S of the input binary signal V_IN is zero. It follows that minimum jitter and maximum noise margin in the DC restored output signal V_Q will result when the offset voltage V_OS is cancelled exactly by the feedback voltage V_FB. This corresponds to the condition of the amplitude V₁ of the input binary signal V_IN being equal to the amplitude V₂ of the DC restored voltage signal V_Q. Conversely, if equal amplitudes (i.e. V₁ = V₂) cannot be maintained, the above expression shows that the Quantized Feedback system 20 (shown in Figure 3) will introduce jitter into the DC restored output signal V_Q and the jitter will be proportional to both the error between the amplitudes of the input binary signal V_IN (i.e. V₁) and the comparator output signal V_C (i.e. V₂) and the rise time of the input binary signal V_IN (i.e. T_S).

<u>A HYSTERETIC BIPOLAR CLAMP DC RESTORER (THE PRESENT INVENTION)</u>

Reference is now made to Figure 4 which shows in block form the elements of a hysteretic bipolar clamp DC restorer 30 according to the present invention. The clamp DC restorer 30 comprises a clamping circuit 32, a voltage comparator 34, and a feedback network 36. The input binary signal V_IN is coupled to the DC restorer 30 through a coupling capacitor 38. One terminal of the coupling capacitor 38 is connected to a summing node 40. The summing node 40 is formed from the input terminal of the clamping circuit 32, the positive input terminal of the voltage comparator 34 and the output terminal of the feedback network 36.

Reference is next made to Figure 5 which shows in detail the circuit elements that comprise the DC restorer 30. The voltage comparator 34 provides a digital data output 42 for a DC restored output signal V_DATA. The output 42 of the voltage comparator 34 also feeds into the positive terminal of a differential buffer 44. The differential buffer 44 produces a feedback output current I_FB which flows into the summing node 40.

Referring still to Figure 5, the clamping circuit 32 comprises first and second diodes D₁ and D₂. The anode of the first diode D₁ is connected to the cathode of the second diode D₂ and to the summing node 40. The cathode of diode D₁ is connected to the positive terminal of a first clamping voltage reference U ₁. The negative terminal of the clamping voltage reference U₁ is connected to signal ground and to the positive terminal of a second clamping voltage reference U₂. The negative terminal of the second voltage reference U₂ is connected to the anode of the second diode D₂ to complete the clamping circuit 32.

The function of the first voltage reference U₁ is to set the clamping voltage for the first diode D₁, that is, the voltage level at which diode D₁ will turn-on in response to a signal being present at node 40. In other words, diode D₁ clamps the positive peak of the AC coupled binary signal V_AC when the peak voltage value exceeds the value of the first voltage reference U₁. In a similar fashion, the second voltage reference U₂ sets the voltage value for clamping the negative peak of the AC coupled binary signal V_AC at the node 40. Accordingly, the clamp circuit 32 clamps both the positive and negative peaks of the AC coupled binary signal V_AC.

As shown in Figure 5, the voltage comparator 34, the feedback network 36 and the summing node 40 form a positive feedback loop. The function of this feedback network 36 is two-fold. First, the feedback network 36 uses the voltage comparator 34 to "latch" the logic state of the AC coupled binary signal V_AC following the last transition of the signal V_AC. The output of the comparator 34 remains latched in this state until there is another transition in the AC coupled binary signal V_AC. The output of the comparator 34 is tapped to provide the output terminal 42 for the DC restored output signal V_DATA. It will be appreciated that the voltage comparator 34 converts the AC coupled binary signal V_AC (analog format) into a digital format data output signal, i.e. the positive peak of the DC restored output signal V_DATA corresponds to a logic HIGH and the negative peak corresponds to a logic LOW value as determined by the supply settings of the comparator 34.

The second function of the feedback network 36 is to produce the feedback current I_FB for restoring the AC coupled binary signal V_AC at the summing node 40. The feedback current I_FB is generated by the buffer 44 which takes the output from the voltage comparator 34 as its positive input. The output of the buffer 44 is connected to the summing node 40 thereby completing the positive feedback loop for the feedback current I_FB. At the summing node 40, the feedback current I_FB is added to the AC coupled binary signal V_AC.

As was discussed above, the DC restorer circuit 30 according to the present invention reduces "jitter" in the AC coupled binary signal V_AC. The implementation of this function will be explained by referring to both Figures 5 and 6. Figure 6(a) shows the input binary signal V_IN which is coupled to the DC restorer circuit 30 by the coupling capacitor 38. The input binary signal V_IN as shown in Figure 6(a) exhibits jitter as a result of unequal rise and fall times, which are denoted by the rising and falling slopes S_R and S_F respectively. The amplitude of the input binary signal V_IN is 2V₁ (i.e. +V₁ to -V₁) peak-to-peak.

One way to achieve zero jitter in the input binary signal V_IN is by making the rise time equal to the fall time, i.e. slope S_R = slope S_F . This property can be illustrated by considering the characteristics of the input binary signal V_IN shown in Figure 6(a). In Figure 6(a), the bit-width of the input binary signal V_IN (as transmitted) is denoted by T_H. The bit-width T_H is the interval between the starting points of the low to high and high to low transitions. The effective or actual bit-width T_H' which is the interval between the points where the transitions (i.e. rising slope S_R and falling slope S_F) cross the threshold voltage V_TH (i.e. mid-level voltage value). Referring to Figure 6(a) the effective bit-width T_H' of the input binary signal V_IN can be expressed in terms of the bit-width T_H and respective delays (denoted by T_DR and T_DF in Figure 6(a)) between the start of the rising and the falling edges S_R, S_F and the points where the input binary signal V_IN crosses the logic threshold V_TH. Using simple addition, the effective bit-width T_H' is:<maths id="math0008" num="(8)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>H'</mtext></mrow></msub><msub><mrow><mtext>= T</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext> + T</mtext></mrow><mrow><mtext>DF</mtext></mrow></msub><msub><mrow><mtext> - T</mtext></mrow><mrow><mtext>DR</mtext></mrow></msub></mrow></math><img file="EP0611059B1_D0008.tif" /></maths> The rise and fall delay times (i.e. T_DR and T_DF) can be expressed in terms of the rising and falling slopes S_R and S_F and the amplitude V₁ of the input binary signal V_IN, as follows:<maths id="math0009" num="(9)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>DF</mtext></mrow></msub><msub><mrow><mtext> = -V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>/S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub></mrow></math><img file="EP0611059B1_D0009.tif" /></maths><maths id="math0010" num="(10)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>DR</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>/S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub></mrow></math><img file="EP0611059B1_D0010.tif" /></maths> Substituting the above expressions (9) and (10) for the rise and fall time delays T_DR and T_DF into expression (8) yields the following result for the effective bit-width T_H':<maths id="math0011" num="(11)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>H'</mtext></mrow></msub><msub><mrow><mtext> = T</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext> - V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>/S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub><msub><mrow><mtext> - V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>/S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub><mspace linebreak="newline" /><msub><mrow><mtext> = T</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext> - V</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext> * (1/S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub><msub><mrow><mtext> + 1/S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP0611059B1_D0011.tif" /></maths> Therefore according to expressions (8) and (11), there will be zero jitter (i.e. T_H' = T_H) if the rise delay time T_DR equals the fall delay time T_DF in expression (8), and this requires that the rising slope equal the falling slope, i.e. S_R = S_F.

Reference is next made to Figure 6(b) which shows the AC coupled binary signal V_AC restored according to the present invention to produce a DC restored binary (i.e. analog) signal denoted by the reference V_DC. The DC restored binary signal V_DC is produced at the summation node 40 by the operation of the clamping circuit 32 and the feedback current I_FB. The DC restored binary signal V_DC is produced by clamping the AC coupled binary signal V_AC and using the feedback current I_FB to control the rise and fall times.

Referring to Figure 6(b), the positive peak of the DC restored binary signal V_DC is given by the voltage +V_CLAMP. The voltage value +V_CLAMP corresponds to the peak value of the AC coupled binary signal V_AC which is clamped by diode D₁ and voltage reference U₁. Similarly, the negative value of the DC restored binary signal V_DC is given by the voltage -V_CLAMP, which corresponds to the negative peak of the AC coupled binary signal V_AC which is clamped by diode D₂ and voltage reference U₂. When the AC coupled binary signal V_AC is clamped, the feedback current I_FB flows into the respective diode, i.e. either D₁ or D₂. For the purposes of the following analysis, the diodes D₁ and D₂ are considered to be ideal, i.e. the forward voltage-drop is negligible. Another property of the clamping circuit 32 for this analysis is the very high input impedance for voltages within the range +V_CLAMP to -V_CLAMP. This high input impedance forces virtually all of the feedback current IFB to flow into the coupling capacitor 38 when the AC coupled binary signal V_AC is within the clamping voltage range, i.e. the diode D₁ or D₂ is not conducting.

The operation of the clamping circuit 32 can be demonstrated by considering the rising edge S_R of the DC restored binary signal V_DC. The polarity of the feedback current I_FB is negative as long as the input binary signal V_IN is less then zero volts. The polarity of the feedback current I_FB is controlled by the voltage comparator 34 and buffer 44 (Figure 5). At the start of the transition period indicated by reference 46 in Figure 6(b), diode D₂ is turned off which causes the feedback current I_FB to flow into the coupling capacitor 38. Since by design the feedback current I_FB has a constant value, the effect on the voltage V_C of the capacitor 38 is a linear charging with a rate of I_FB/C, where C is the capacitance of capacitor 38. However, this change in the voltage V_C of the coupling capacitor 38 will be opposed by the change in the input binary signal V_IN as long as the AC coupled binary signal V_AC is negative (i.e. the AC coupled binary voltage V_AC controls the polarity of the feedback current I_FB). It follows that the DC restored binary signal V_DC will have a slope that is the difference between the transition rate of the input binary signal V_IN and the rate of change of the voltage V_C of the coupling capacitor 38. This is shown in Figure 6(b), where the DC restored binary signal V_DC has rising and falling slopes denoted by S_RA and S_FA respectively. The rising slope for the DC restored signal V_DC can be expressed as:<maths id="math0012" num="(12)"><math display="block"><mrow><msub><mrow><mtext>S</mtext></mrow><mrow><mtext>RA</mtext></mrow></msub><msub><mrow><mtext> = S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><mtext>/C</mtext></mrow></math><img file="EP0611059B1_D0012.tif" /></maths> where S_R is the rising slope of the input binary signal V_IN and the second term is the charging capacitor voltage V_C resulting from the feedback current I_FB. Similarly, the falling slope for the DC restored binary signal V_DC can be expressed as follows:<maths id="math0013" num="(13)"><math display="block"><mrow><msub><mrow><mtext>S</mtext></mrow><mrow><mtext>FA</mtext></mrow></msub><msub><mrow><mtext> = -(S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub><msub><mrow><mtext> + I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><mtext>/C)</mtext></mrow></math><img file="EP0611059B1_D0013.tif" /></maths> where S_F is the falling slope of the input binary signal V_IN (Figure 6(a)) and the second term is charging rate of the coupling capacitor 38 by the feedback current I_FB.

The rising and falling slopes, S_RA and S_FA, for the DC restored binary signal V_DC can be converted to corresponding rising and falling edge delays, T_DRA and T_DFA, by using the clamped voltage values +V_CLAMP and -V_CLAMP of the references U₁ and U₂ for the peak amplitudes of the DC restored binary signal V_DC, as follows:<maths id="math0014" num="(14)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>DRA</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>CLAMP</mtext></mrow></msub><msub><mrow><mtext>/S</mtext></mrow><mrow><mtext>RA</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>CLAMP</mtext></mrow></msub><msub><mrow><mtext>/ (S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub><msub><mrow><mtext> - I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><mtext>/C)</mtext></mrow></math><img file="EP0611059B1_D0014.tif" /></maths><maths id="math0015" num="(15)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>DFA</mtext></mrow></msub><msub><mrow><mtext> = -V</mtext></mrow><mrow><mtext>CLAMP</mtext></mrow></msub><msub><mrow><mtext>/ - S</mtext></mrow><mrow><mtext>FA</mtext></mrow></msub><msub><mrow><mtext> = V</mtext></mrow><mrow><mtext>CLAMP</mtext></mrow></msub><msub><mrow><mtext>/(S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub><msub><mrow><mtext>+I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><mtext>/C)</mtext></mrow></math><img file="EP0611059B1_D0015.tif" /></maths>

Referring still to Figure 6(b), the DC restored binary signal V_DC has a bit-width T_HA which can be expressed in terms of the bit-width T_H of the input binary signal V_IN and the rise and fall time delays T_DRA and T_DFA as follows:<maths id="math0016" num="(16)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>HA</mtext></mrow></msub><msub><mrow><mtext> = T</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext> + T</mtext></mrow><mrow><mtext>DFA</mtext></mrow></msub><msub><mrow><mtext> - T</mtext></mrow><mrow><mtext>DRA</mtext></mrow></msub></mrow></math><img file="EP0611059B1_D0016.tif" /></maths> Substituting the above expressions (14) and (15) for T_DRA and T_DFA into expression (16) yields the bit-width of the DC restored binary signal V_DC in terms of the voltage value V_CLAMP of the reference U₁ and U₂, the feedback current I_FB and the rising and falling slopes i.e. S_R and S_F:<maths id="math0017" num="(17)"><math display="block"><mrow><msub><mrow><mtext>T</mtext></mrow><mrow><mtext>HA</mtext></mrow></msub><msub><mrow><mtext> = T</mtext></mrow><mrow><mtext>H</mtext></mrow></msub><msub><mrow><mtext> - V</mtext></mrow><mrow><mtext>CLAMP</mtext></mrow></msub><msub><mrow><mtext> * (1/(S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub><msub><mrow><mtext>-I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><msub><mrow><mtext>/C) + 1/(S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub><msub><mrow><mtext>+I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub><mtext>/C))</mtext></mrow></math><img file="EP0611059B1_D0017.tif" /></maths><maths id="math0018" num="(18)"><math display="block"><mrow><msub><mrow><mtext>S</mtext></mrow><mrow><mtext>R</mtext></mrow></msub><msub><mrow><mtext> * C (or -S</mtext></mrow><mrow><mtext>F</mtext></mrow></msub><msub><mrow><mtext> * C) &gt;&gt; I</mtext></mrow><mrow><mtext>FB</mtext></mrow></msub></mrow></math><img file="EP0611059B1_D0018.tif" /></maths> It then follows from expression (17) above that the rising and falling slopes, S_RA and. S_FA, of the DC restored binary signal V_DC are only slightly less steep then those of the input binary signal V_IN, i.e. S_R = S_RA and S_F ≈ S_FA because the feedback current I_FB is small. By comparing the expressions (11) and (17) for T_H' and T_HA respectively, it can be seen that any jitter error in the input binary signal V_IN is reduced in the DC restored binary signal V_DC by the amount approaching the ratio V₁/V_CLAMP. This follows from the clamping of the AC coupled binary signal V_AC to +V_CLAMP and -V_CLAMP as discussed above for Figure 6(b). In the preferred embodiment of the invention, this ratio is typically four or more which produces a reduction in jitter of at least two or three times. It will be appreciated by one skilled in the art that noise margin considerations will limit the jitter reduction achievable by reducing the clamping voltages values +V_CLAMP and -V_CLAMP for the references U₁ and U₂.

Referring next to Figure 6(c), the "latching" function of the voltage comparator 34 will be considered. The "latching" function of the comparator 34 converts the DC restored binary signal V_DC to a DC restored digital output signal indicated by reference V_DATA. The DC restored digital output signal V_DATA has logic level "1" and logic level "0" which are set by the voltage comparator 34 output characteristics (i.e. positive and negative voltage rails for comparator 34). The threshold voltage level for converting the DC restored analog signal V_DC to the restored digital signal V_DATA is determined by the reference voltage level connected to the negative terminal of the voltage comparator 34, which in this case is set to zero volts. Therefore, the output of the voltage comparator 34 will remain high (i.e. logic "1") until the DC restored binary signal V_DC makes a transition which is less than the reference voltage level on the negative terminal of the comparator 34. The input characteristics (e.g. high open loop gain) of the voltage comparator 34 can also be used to detect weak AC coupled binary signals V_AC, for example signals which have been attenuated as a result of being transmitted over long distances over coaxial transmission lines.

<u>AUTOMATIC GAIN ADJUSTMENT FOR HIGH FREQUENCY EQUALIZATION</u>

As discussed for the known system shown in Figure 1, the binary signal V_IN which is received from the co-axial cable 6 will have experienced attenuation or amplitude losses. For accurate data reproduction, the AC coupled binary signal V_AC must undergo both high frequency equalization and low frequency equalization (i.e. DC restoration). To compensate for these losses, the cable equalizer 7 includes the DC restorer 8 and the high frequency equalizer 9 (as shown in Figure 1). As discussed in detail above, the DC restorer 8, according to the present invention, restores the DC and low frequency components of the AC coupled binary signal V_AC. The high frequency equalizer 9, on the other hand, restores or equalizes the high frequency component of the AC coupled binary signal V_AC. In a second embodiment of the present invention, the DC restorer 8 described above has been modified and integrated with an automatic gain controller for controlling the operation of the high frequency equalizer. As will be discussed below, the automatic gain controller allows optimum operation of both the modified DC restorer and the high frequency equalizer 9.

Reference is next made to Figure 7 which shows in block form the cable equalizer 7 incorporating a modified DC restorer 50 and an automatic gain controller 52 according to the second embodiment of the present invention. The automatic gain controller 52 is coupled between the modified DC restorer 50 and the high frequency equalizer 9. As will be discussed in detail below, the automatic gain controller 52 produces a voltage control signal V_AGC which is a function of the difference between a reference current I_REF and a signal current I_SIG. The signal current I_SIG is proportional to the amplitude of the AC coupled binary signal V_AC.

Reference is next made to Figure 8 which shows in detail the DC restorer 50 and the automatic gain controller 52 according to the second embodiment of the present invention. Corresponding reference numerals indicate elements corresponding to those of Figure 5. The automatic gain controller 52 (indicated by the broken outline) comprises a current source 54 which produces the reference current I_REF, an integrating capacitor C_AGC and a voltage output line 56. The automatic gain controller 52 is coupled to the DC restorer 50 through a current input line 58 which is connected to the current source 54 at node 60. The magnitude of the reference current I_REF should be chosen such that the equalized output of the high frequency equalizer 9 (Figure 7) stabilizes at a level which represents optimal high frequency equalization as will be within the understanding of one skilled in the art. For a typical high frequency equalizer 9, the reference current I_REF should be in the range 200-300 µA.

The automatic gain controller 52 produces a control current I_AGC which flows into the integrating capacitor C_AGC. The capacitor C_AGC integrates the control current I_AGC to produce a voltage control signal V_AGC which is fed to the high frequency equalizer via line 56. The gain control current I_AGC is the difference between the reference current I_REF and the signal current I_SIG taken at node 60. The signal current I_SIG is a current component which flows into the DC restorer 50 via line 58. The signal current I_SIG is produced from the difference between the feedback current I_FB and a clamping current I_CLAMP, where the clamping current I_CLAMP is a current flowing in the conducting clamping diode D₁ or D₂. In Figure 8, the clamping current I_CLAMP corresponds to current I_D1 if diode D₁ is conducting and current I_D2 if diode D₂ is conducting. Recall that diode D₁ conducts if the coupled binary signal V_AC is positive and diode D₂ conducts if the coupled binary signal V_AC is negative. In other words, the automatic gain controller 52 compares the reference current I_REF to the difference between the clamped current I_D1 or I_D2 and the feedback current I_FB (i.e. I_SIG=I_D1(or I_D2)-I_FB). The difference between the reference current I_REF and the signal current I_SIG is the current I_AGC which is integrated by the capacitor C_AGC to produce the voltage control signal V_AGC. The voltage control signal V_AGC is then applied as negative feedback to control the gain of the high frequency equalizer 9. Since the current flowing in the clamping diodes D₁ or D₂ is proportional to the amplitude of the binary signal V_AC, the DC restorer 52 provides an elegant implementation for automatic gain control as will become clear from the following explanation.

In the second embodiment of the DC restorer 50 shown in Figure 8, the clamping diodes D₁ and D₂ (of Figure 5) have been replaced by respective transistors Q₁ and Q₂. The transistors Q₁ and Q₂ permit the clamping circuit 32 to be integrated with a current sensor 62 as shown in Figure 8. The current sensor 62 senses the current flowing in the diode-connected transistor Q₁ when it is conducting, i.e. the AC coupled binary signal V_AC is positive. When the AC coupled binary signal V_AC is negative the diode current I_D2 is a direct component of the signal current I_SIG.

The current sensor 62 comprises the combination of diode-connected transistor Q₁ (i.e. diode D₁) and a transistor Q_1A. The base of transistor Q_1A is connected to the base of diode-connected transistor Q₁ to form a current mirror as will be recognized by one skilled in the art. The current sensor 62 is coupled to the current output line 58 from the automatic gain controller 52. The clamping current I_CLAMP is represented as either current I_D1 or current I_D2, depending on which transistor Q₁ or Q₂ is conducting. The current I_D2 flows as collector current through transistor Q₂ when it is forward-biased or conducting. The other diode current I_D1 flows through diode-connected transistor Q₁ when it is forward-biased by the AC coupled binary signal V_AC present at the summing node 40. The sensing transistor Q_1A has a collector current which is denoted by I_C1A. By the operation of the current mirror comprising diode-connected transistor Q₁ and sensing Q_1A, the collector current I_C1A of the sensing transistor Q_1A will be equal to the diode current I_D1 (i.e. the clamping current I_CLAMP) which flows in the diode-connected transistor Q₁ when it is forward-biased. When diode-connected transistor Q₁ is reverse biased or not conducting, the clamping current I_CLAMP comprises current I_D2 which flows into the collector of transistor Q₂ which is forward-biased or conducting because the AC coupled binary signal V_AC at the summing node 40 is negative.

Referring still to Figure 8, the clamping current I_CLAMP (i.e. current I_D1 or current I_D2) flows into the summing node 40. The clamping current I_CLAMP which is in excess of the feedback current I_FB is due to the clamping of the input binary signal V_IN by the clamping circuit 32. Furthermore, the clamping current I_CLAMP (i.e. current I_D1 or current I_D2) is a measure of the amplitude and rise time of the input binary signal V_IN. Therefore, the signal current I_SIG is the current which results from a voltage change on the coupling capacitor 38. The magnitude or pulse height of the signal current I_SIG is proportional to the rate of rise of the input binary signal V_IN. The duration (i.e. pulse width) of the signal current I_SIG, on the other hand, is proportional to the amount by which the input binary signal V_IN exceeds the clamping level (i.e. voltage reference U₁ or U₂), and inversely proportional to the rate of rise of the input signal V_IN. Accordingly, the average of the signal current I_SIG, (i.e. pulse height x pulse width), provides an approximate measure of the amplitude of the input binary signal V_IN which is independent of the rise time. These relationships are clearly shown in Figure 9.

Figure 9 shows the waveforms for the currents I_D1 and I_D2 which flow in the collectors of transistors Q₁ and Q₂ as a result of the input binary signal V_IN being clamped at the summing node 40. The feedback current I_FB is the positive feedback current which flows into the clamping circuit 32 (Figures 5 and 8). For the input binary signal V_IN shown in Figure 9(a), consider the rising edge S_R. The positive rising edge S_R of the input signal V_IN coupled at node 40 causes diode-connected transistor Q₁ to conduct, i.e. current I_D1 will flow in diode D₁ along with the feedback current I_FB. The net current flowing in diode-connected transistor Q₁ (i.e. I_D1-I_FB) is proportional to the amplitude and rise time of input binary signal V_IN. The current I_D1 can be calculated from the product of the coupling capacitor 39 capacitance C times the rate of change for the input signal, i.e. I_D1 = CxdV_IN/dt. The signal amplitude current I_SIG which flows when diode-connected transistor Q₁ is forward-biased is equal to the current I_D1 (i.e. I_CLAMP) minus the feedback current I_FB. Since the signal amplitude current I_SIG results from the voltage change (i.e. d V_IN/dt) across the coupling capacitor 38, the amplitude of the signal amplitude current I_SIG is proportional to the rise time of the input binary signal V_IN (i.e. rate of change). On the other hand, the width of the pulse for the signal amplitude current I_SIG shown in Figure 9(c) is proportional to the amount by which the input binary signal V_IN exceeds the voltage reference U₁, and inversely proportional to the rate of rise S_R of the input signal V_IN. The second property follows because the faster the rise of a signal, the larger the magnitude which means the narrower the pulse. Therefore, the average of the signal amplitude current I_SIG, i.e. pulse height x pulse width, provides an approximate measure of the amplitude of the input binary signal V_IN. A similar analysis follows for the falling edge (denoted by reference S_F in Figure 9(a)) for the input binary signal V_IN.

As will be appreciated by one skilled in the art, the second embodiment of the present invention provides a DC restorer 50 which can be merged with the automatic gain controller 52 to elegantly couple with the high frequency equalizer 9. The negative feedback (i.e. V_AGC) control of the high frequency equalizer 9, in turn, relaxes the requirement for precision matching and performance in the equalizer 9.

Although various preferred embodiments of the present invention have been described in detail, it will be appreciated by those skilled in the art, that variations may be made to the present invention without departing from the scope of the appended claims.