Method of manufacturing a multilayer wiring board

A method is provided for manufacturing a multilayer wiring board comprising interlayer connection between a first electric circuit pattern and a second electric circuit pattern, both electric circuit patterns being formed on a substrate, the method being characterised by the steps of: applying a first metal layer onto the substrate and a second metal layer onto the first metal layer; selectively etching the second metal layer to partially expose regions of the first metal layer not required to form the first electric circuit pattern; etching the exposed regions of the first metal layer to expose corresponding regions of the substrate and to form the first electric circuit pattern; etching the second metal layer so that the remaining second metal layer forms a via bump, the via bump being located in a position where the interlayer connection is required; applying an insulation layer to cover the first electric circuit pattern while leaving one end of the via bump exposed; and applying a third metal layer onto the insulation layer and the exposed end of the via bump, and etching the third metal layer to form the second electric circuit pattern, the via bump thereby providing interlayer connection between the first and second electric circuit patterns. The above method makes it possible to increase the electric circuit forming density in interlayer connections of multilayer wiring boards by producing via bumps of smaller diameter than previously achievable, and also allows the number of manufacturing steps to be reduced.