ATM switch with copy capability

The invention relates to a copyable ATM switch for switching ATM cells according to the preamble of claim 1st

Such ATM switch is known from WO 87/00372. Next is also known one exchange with a succession of copy switch, Verteilkoppelfeld and target switching matrix.

Real operation, a mixture of Point-to-point connections, Point-to-multipoint connections with few branches and point-to-multipoint connections with many Branches. The total traffic and the individual Shares are constantly changing. The known structures are each on one side only to a specific type of traffic optimized.

The invention is based on the object, a specify copyable ATM switch, the various, also changing modes is equally matched.

The object is achieved by an ATM switch according to the teaching of the main claim. advantageous Embodiments of the invention are the claims to remove.

The solution is based on the idea that Coupling elements of a switching network, which for Point-to-point connections is optimized, additionally with the ability to provide, a few to copy inputs to any number of outputs, whereby a very high total for a few input signals Copy number is reached. This group switch is supplemented by a copy switch, the only the creation of a limited number of copies of each is used for a large number of input signals, which are then in the group switch as point-to-point connections mediated.

The use of a separate copy switch field is related to a one-step group switch, already known from IEEE INFOCOM 88 March 1988, New Orleans, US, pages 29-34, K. Eng et al .: "Multicast and Broadcast Services in a Knockout Packet Switch ".

The use of output units in which the original to the Order is sorted, is already in the non-prepublished EP-Al-0435046 described.

Point-to-point connections in the group switch as "Connectionless connections" means self-control the coupling elements operate. It is ensured that these connections to the outside as virtual connections Act. Point-to-multipoint connections are also in the Group switch as virtual connections (Connection-oriented) by means of connection tables operated.

As "connectionless connections" are those Viewed compounds in which the individual cells a compound not go the same way, but on all possible paths are divided. This occurs fairly even a burden; on traffic measurements can be dispensed with, which it otherwise required Devices are not required. However, there is the need, on the correct sequence of to make cells because here overtaking is not excluded are.

"Connectionless compounds" put coupling elements advance that contained by the way information Address can be directly controlled. The preparation of Copies for point-to-multi-point connections by means of such addressing very difficult. Examples of such coupling elements are known.

Also known are coupling elements by indirect Addressing be controlled. Suitable routes Information this compound numbers in question, which in each evaluated coupling element based on connection tables will. If a connection number Connection table of a coupling element for several contain outputs, then to each of these outputs a Copy a cell with this compound number output.

Especially when point-to-multipoint connections may by constant change of the participants in an uneven Exposure of the group switch come. Since the Group switch but primarily for "connectionless Compounds "is designed, it must at its outputs comprise means to secure the proper Order of the cells by any overtaking serve. It is therefore easily possible, existing reorder virtual connections. Here short occurring overtaking is like the "Connectionless connections" corrected.

The use of compound numbers for forcing point-to-multipoint connections in the group switch take specific precautions when Connection number to be used repeatedly. On Anyway, the total number of the group switch possible point-to-multipoint connections limited. Therefore but could in such a Point-to-multi-point connection in principle all the Group switch leaving lines be involved.

More point-to-multipoint connections at the same time to allow a separate copy switch provided. must from each input of the exchange an input of the copy switch to be accessible. It is not necessarily mean that each input of the copy switch is reachable from every input of the switching center. Preferably an access via the group switch, wherein each input of the exchange with an input of the group switch and each input of the Copy switch with an output of the group switch connected is.

The copy switch has only the task of the each create required number of copies. The Placement of these copies is done in group switch in each case in the manner of a point-to-point connection. Not each output of the copy switch network has its of each Inputs to be accessible. The number of stages depends only on the copying ability of the individual coupling elements (ie, on the number of outputs of the coupling elements) and the maximum required starting copy number. Usually enough a copy switch with just a few steps (eg, two to three stages in 16X16-Kopp elements). Each Connection number can be used several times here; the number of concurrent connections in Copy switch is thus far hardly restrictions subjected.

A switch thus constructed, any kind of Edit traffic. Local internal blockages can either do not occur (point-to-point connections) be resolved or without disturbance at any time (Point-to-multi-point connections). Also between the both possibilities of the point-to-multipoint connections may at any time be switched without interference to the utilization adapt to the current situation. In order to may total a very uniform utilization of Group switch can be achieved. A partial Blocking by fully loaded trunk lines but a total or excessive load can not be prevented.

The disadvantage can be considered that the Group switch special coupling elements are required are, the various two Addressing options can work. These However, coupling elements may also be used where one of the two addressing options not is used, for example, in the copy switch. Such coupling elements can therefore be used as Universal coupling elements are used.

In the following, the invention is based on a Exemplary embodiment with reference to the accompanying Drawings explained further.<dl tsize="6"><dt>Fig. 1</dt><dd>shows a preferred embodiment of a ATM switch according to the invention. </dd><dt>FIG. 2</dt><dd>shows a block diagram of an output unit for the inventive switch.</dd><dt>Fig. 3</dt><dd>shows a possible implementation for the in the output unit of FIG. 2 contained Buffer memory.</dd></dl>

The ATM switch of FIG. 1 has inputs I1, I2, ..., Ii, outputs O1, O2, ..., Ol, a Group switch 10, a copy switch 20, three groups of input units 31, 32 and 33 and three groups of Output units 41, 42 and 43. The Group 31 includes i input units 311, 312, ..., 31i; the Group 32 includes j input units 321, 322, ..., 32j; the group 33 includes k input units 331, 332, ..., 33k; the group includes 41 l output units 411, 412, ..., 41l; the group includes 42 k output units 421, 422, ..., 42k; the group includes 43 j output units 431, 432, ..., 43j.

Each of the inputs I1, I2, ..., Ii the exchange is connected to input one of the input units 311, 312, ..., 31i of the group 31, the outputs of each are connected to an input of the group switch 10th Each of the outputs O1, O2, ..., Ol the switch is connected to the output of the output units 411, 412, ..., 41l the group 41, whose inputs are respectively are connected to an output of the group switch tenth

The inputs of the output units 421, 422, ..., 42k of Group 42 are connected to further outputs of The group switch 10. The outputs of the Output units 421, 422, ..., 42k are the group 42 respectively to the input of one of the input units 331, 332, ..., 33k of group 33, whose outputs Inputs of the copy switch 20 are connected.

The inputs of the output units 431, 432, ..., 43j of Group 43 are each provided with an output of the copy switch 20. The outputs of the output units 431, 432, ..., 43j of the group 43 are connected to the input one of the input units 321, 322, ..., 32j of the group 32, the outputs of the other inputs with The group switch 10 are connected.

For the present invention, it is irrelevant whether The inputs I1, I2, ..., Ii and the outputs O1, O2, ..., Ol with end stations, PBXs, Front-end equipment or other Switching centers are connected. In general, the Number of inputs, i, equal to the number of outputs, l, be, ie i = l.

The main switching matrix 10 includes a plurality of in several stages arranged coupling elements. It is so constructed so that connections between each input and each output are possible. Examples of such Switching networks to any person skilled in the art.

The individual coupling elements are constructed so that they switchable by information contained in the cell header between a first addressing mode, in which the Cell because of non-used is an externally influenced algorithm evaluated routing information is passed, and a second addressing mode, wherein the cell is one using a result of the Connection table evaluated routing information is forwarded. It is provided that in the second addressing a cell also copied and on multiple paths can be forwarded.

ATM switching elements with an addressing means working from the outside can not be influenced algorithm are the skilled man as well known as those with Addressing via connection table work.

As algorithm for example, takes a Assignment rule in question as from "SYSTEM 12, Digital switching network ", Electrical Communication, Volume 56, no. 2/3, 1981, pages 148-160 for known time division switching systems. There it is possible to a very specific, by the Routing information directly predetermined output line to address. There is also the possibility of the select routing information to any output line allow. The given there possibility within a Output line also a particular channel select, is neither possible nor necessary at ATM. A useful way the possibility of the Routing information to any output line from a predetermined group of select output lines. can When selecting an arbitrary output line For example, the current utilization be used. It is also possible to carry the Routing information contained in a coupling element addressing means, for example, to the for the second addressing required to change connection table.

The time required for the second addressing Connection table, a RAM with M address bits and N his bits. The address will be used for this coupling element valid bits of routing information formed, the data bits that give output line on, is to be issued on the. If multiple data bits set simultaneously, so the cell is on multiple output output lines, thereby easily copying of cells is reached. Instead of single RAM may also assigned to each output a RAM be provided with M address bits and a data bit, For example, a 128 x 1 - RAM for M =. 7

The coupling elements must be so constructed that they on Two different types of work. For this is suitable in principle a construction as the reference Figures 3 and 5 of DE-A1 37 42 939.6 described. The described there part-coupling elements 22 and 24 will have here replaced by a part-coupling element for the first addressing and part-coupling element for the second addressing mode.

The group switch 10 is Point-to-point connections optimized. For this it is so constructed and operated such that in the first half each cell takes any way, so that therefore the Traffic will be divided equally. In the second Half is then each cell directly to your desired Output passed. Each coupling element of the middle stage must therefore from each input of the group switch from be accessible and each output of can reach the group switch.

is preferably used as group switch, a reverse switching network. Each coupling element of the first stage is simultaneously the final stage coupling element. A part of its inputs is connected to inputs of the group switch, another part of its inputs to outputs of Coupling elements of the penultimate stage switch connected. On Part of its outputs with inputs from Coupling elements of the second switching stage connected to a Another part of its outputs with the outputs Group switch connected. Each coupling element of second stage is the same coupling element of penultimate stage, etc. The number of stages is odd. Such reverse-switching networks are of the Time division multiplexing been known, for example from the mentioned article "SYSTEM 12, digital switching network". they have the advantage that the middle stages not have to be used necessarily for each connection.

The copy switch 20 can be made of the same Coupling elements be constructed here but only one the addressing modes used. In contrast to Group switch 10 must here but not everyone starting from each input to be accessible. It is sufficient if each of Input from a predetermined number of outputs is achievable. It must also not necessarily of any Input from the same number of outputs to be accessible. The copy switch 20 can therefore in one piece exist in the input of each of 128 outlets are attainable and from another part, in which by each input of 32 outputs can be achieved. It must are of course taken into account that the entire Traffic load from the input of the copy switch to whose output toward depending on the average Copy Ratio increases.

Although due to the increase of traffic through the Copy the number of output units in the group 42, equal to the number of input units in the group 33 is smaller than the number of output units in the group 43, which equals the number of input units is in the group 32, it is still possible to each fixed input unit of the group 32 of an output unit the group 42 and each output unit determines the group 43 an input unit of the group 33 assigned. Instead of an allocation of units of the group 43 to units Group 33 is a summary of the Output units of group 43 with the corresponding Input units of the Group 32 and a summary the output units of the group 42 with the corresponding input units of the Group 33 possible. The assignment or summary should, at least the allow exchange of control data.

as together with the formation of the group switch 10 Reverse switching network is thus created the opportunity that all parts of the exchange (input and Output units, coupling elements) on the normal Connection paths to easily control data exchange. About additional inputs and outputs of the Main switching matrix 10 to various Auxiliary equipment to be connected, in the same Way with all other parts of the central office can exchange control data. Control, diagnostics and but vote are not the subject of the present Invention.

The input and output units can be initially Note that all exchanges any kinds having input and output units. here is only describes what the invention is specific.

Each input unit's first task is to get everyone mediating cell accompanied by a path information. Reference is made to pages 6 to 9 of an article by W. Schmidt in "The telecommunications engineer =", Issue 9, September 1987 referenced. There is the basic Mediation Process described. In the top of each cell Cell must necessarily a connection-specific Labeling to be included. From this is in the Input unit due to table a determines routing information for subsequent switching network and attached to the cell. It takes between two types of addressing do not distinguish to be, as the data format to be necessarily equal have to be.

In the said article are at page 7, penultimate Section, also "systems that work with timestamps" called. These "must the arrival of a packet determined and the packet information at the input of the node be added ". If these timestamps sufficient dissolve fine, then they can also be used to the order of cells to be labeled. Although at no timestamps are used, can be equally be moved way to the order to mark. It is also possible in each used input unit independent modulo-N counter are to these brands, to below as brands the first type referred to forgive. Since the correct Ranked only between the cells of each must be guaranteed connection, can the Compound numbers, where they exist, as Elimination criteria are used, they are hereinafter referred to as markers of the second type. The Brands first type, both for the cells of each each compound separately and for the cells all available through an input unit links be awarded jointly.

viewed Inasmuch as under input unit only is what the invention specifically known to ATM switch is added, is only a Input unit used when coming from the outside Cells not already the order characteristic contains brand, or if this is not readily is recyclable.

With reference to FIGS. 2 and 3, an embodiment for an output unit described. All output units are basically identical to each other. they differ substantially by the predetermined Delay Time.

The basic idea of ​​this embodiment is that, each cell at the output as long to stop until it is ensured that no older cell more road may be cached. Before passing the Cell is tested whether under the later at the output arrived cells nor a cell is the pre- issue is.

This is preferably realized in that output side, a buffer memory is present, the is operated at least partially shift register like and thereby causing a predetermined delay. In front Output of a cell is the least shift register-like driven part of the buffer then investigated whether a later enrolled Cell is output earlier. If so, the two Cells reversed.

is In this embodiment, an output unit assumed a data stream on cell width is parallelized, ie one in which all bits of a cell passed simultaneously on parallel lines will. This is usually given nor particularly advantageous. But the one hand, it is always possible, by series-parallel converter, Parallel-to-serial converter and buffer such produce data stream, on the other hand it is in the range skill of the art, the present Embodiment of a concrete given Data format, as for example in the interior of ATM switch is used to adapt. there It will then also be advantageous or even necessary, to store not the cells themselves in the buffer memory, but only the information required to reorder and to Retrieving the separate in a memory stored cells are necessary. Dealing with indirect addressing is familiar to any expert. You can also in the example shown, readily are used, then instead of the data in each case the address is stored under which the data are actually stored.

The output unit shown in FIG. 2 has a Buffer memory 1, a memory management unit 2, two Multiplexer 3 and 4, two latches 5a and 5b, two comparators 6 and 7, a further buffer memory 8 and a counter 9.

The buffer 1 has p memory locations. Each Space is for receiving a full Cell provided. For the present output of unit Importance and therefore particularly shown in Fig. 1 is per cell is a brand of the first type, sequence number, a Mark of the second kind, VCI (= Virtuel Circuit Identifier) ​​and the rest of the cell data. are the representation in FIG. 2 the actual memory requirements for each Parts not correctly again.

Preferred is for assigning the labels of a first kind uses modulo-N counter, where N is the size to choose, that within a predetermined time less than N / 2 Numbers are allocated as labels of a first kind. Because of the periodic occurrence of all numbers must after two Directions exist at a suitable distance to to obtain uniqueness. With the specified choice of N can all the cells clearly in their original Order to reconstruct that the when awarding Numbers not more than the said predetermined time apart. This time must then expediently be set so that, apart from the approved Error rate, it is ensured that each cell within this time, the last memories of the r Buffer 1 passes. As a rough guide for the be predetermined time can double the difference between maximum and minimum duration between Allocation of marks of the first type and the arrival in the Output unit are accepted.

The second type brand, VCI, identifies the A cell belonging to a specific virtual Connection.

Instead of the rest of the cell data, can in buffer 1 and the address, are stored under which this Remainder is stored in another memory.

The buffer memory 1 is divided into three parts, namely a shift register-like portion, Shift Register, to the locations 1 to d and a Type of FIFO memory operated part, FIFO again divided into two parts with the locations d + 1 to r and r + 1 composed by p. At least on the Memory locations 1 to r must thereby individually so can be accessed that its contents be read can or that enrolled a new content in it can be.

The dimensioning of the buffer memory, ie the choice the numerical values ​​for d, r and p, must in concrete Application done. must be taken into account especially the allowable error rate, the minimum and maximum duration of a cell since the first Branching point, the number of a same Output unit approved compounds for a Compound approved minimum and maximum number of Cells per unit time and their permissible Fluctuation. For a typical application, gave a simulation values ​​of d = 10, r = 34 and p = 330 for the case that only one passage through the Group switch is compensate 10th For Point-to-multipoint connections, the first of the Group switch 10, then the copy switch 20 and then again through the group switch 10, are the values ​​above approximately by a factor of 2 ... 2.5 to multiply, at least when in only the output the group 41, the order is restored. The but these values ​​are only rough guidelines. The Choice of the value range for the brands of the first kind, Sequence Number is dependent on it. For the above mentioned numerical values ​​and the connection-specific Awarding these brands can N = 512 as a reference point be valid.

At the entrance of the output unit incoming cells, "Cells in ", are first examined to see if it at the output outputted cells or those described in the Output unit end. These are on the one hand empty cells, on the other hand such that control signals for the Output unit (or usually associated Input unit which is otherwise unreachable) contain. The cells are dispensed into the Buffer memory 1 is input in such a manner that they initially operated in the manner of a FIFO memory Part up to the lowest free space "fall through". Whenever the output a cell is output, back in the buffer memory to all cells a space down. If the last Memory location of the FIFO memory, d + 1 is assigned, then the cell contained therein in the first memory of the shift register, d, adopted. Is the Space d + 1 empty, has an empty cell in the Space are enrolled d. The Duration of each cell may thus, at least relative to each other cell, from its position in Buffer 1 are derived. The output from the Buffer memory 1 will be described below.

The memory management unit 2 is shown in FIG. 2 only very shown schematically. She first task the normal operation of the previously described Buffer 1 to ensure. This is done by Creating addresses, address, write commands W, and Read commands, R. In addition, in Fig. 2 not shown, information on the presence or Absence of a cell to be written required. Further, the memory management unit has 2 the task, the content of the addressed by the counter 9 Space, Address, against the content of the to swap the buffer 5b, if this is a command, Swap, will be given.

The multiplexer 3 can selectively the content one of the locations 2 through r of the buffer memory 1 accessed and passed into the latch 5a will. The selection of the storage space is made by the Counter 9, Address.

The multiplexer 4 is the beginning of a Output cycle, the contents of the memory location 1 of the Buffer memory 1 transferred to the buffer memory 5b. This is the case if the counter 9 is reset, "= 0". Through a special command, swap, by means the multiplexer 4, the contents of the buffer 5a in the latch 5b taken. That means the same Instruction, swap is written in the buffer memory 5b is read out and because of this, there is nothing unusual and can by the skilled artisan by conventional means be considered.

The comparator 6 are the marks of the second kind, VCI, those two cells are compared, the currently stored in the latches 5a and 5b are. Only in case of equality of the two brands of the second kind, ie if the two cells of the same connection belong, the subsequent comparator is activated.

The comparator 7 compares the labels of a first kind, Sequence Number, the two in the latches 5a and 5b cells contained. Displays the comparator 6 to, that both cells of the same connection members and will found that the included latches 5a Cell is older than in the latch 5b contained such an instruction, Swap, submitted by the older the cell in the buffer memory 5b and the younger cell at the space in the buffer memory 1 be adopted. The result is that the two Cells reversed.

The counter 9 provides for the right timing. It counts with a predetermined cycle T, periodically of 2 to r. If the counter 9 when the count r reset "= 0", then an output cycle completed and the next started. The contents of the Buffer 5b as in the previous cycle the oldest z u a particular compound associated cell was detected, is taken into the latch 8 and stands on its output, Cells out, for issue Available. At the same time the contents of the Space 1 of the buffer 1 via the Multiplexer 4 taken in the buffer memory 5b. Then the series after the memory locations 2 to r on older cells (labels of a first kind) of the same Compound (trademarks of the second kind) was investigated. For this purpose the Content respectively via the multiplexer 3 in the transferred between the memory 5a and by means of the Comparator 6 and 7 compared. By the above described exchange actions, Swap is ensured that in fact the count r of the counter 9 oldest cell of the subject compound in Latch 5b is stored and that all younger Cells of this compound still or again in Buffer 1 are included.

The selected in FIG. 2 showing the output unit mainly shows the operation of the output unit. The construction and management of the buffer with one operated in the manner of a FIFO memory part and a shift register-like driven part comes clearly in the illustration chosen in FIG. 3 for Expression. The distribution of clocks, including the Read and write commands is not shown here.

The buffer memory is formed by a read-write memory (RAM), 1 ', realized. The arriving cells are an input memory 21 to a data bus, Data, optionally, in which also the read-write memory 1 ' connected. A Einschreibsteuerung 22 is from Input memory 21 is activated, Busy when a to be written cell rests. About the Einschreibzähler 23 is an address PW via an address, address, at the read-write memory 1 'and applied in the cell enrolled this. Subsequently, the Einschreibezähler 23 of 22 from Einschreibsteuerung incremented. A read controller 24 are a Elite counter 25 the address, PR, to which the Storage 1 corresponds. After each issue a Cell is the elite counter 25 of the read-out control incremented 24 from. The difference between the content PW of Einschreibzählers 23 and the content of the PR Readout counter 25 must always be at least equal to d. This will be monitored by the Einschreibsteuerung 22 and where appropriate, empty FIFO, the read controller 24 reported, then, to the data bus, data, an empty cell Empty Cell, investing and writing in by the causes Einschreibzähler 23 specified location and then the Einschreibzähler 23 increments.

The rest of the output unit is here by a Access, comparator and output unit 100 shown.

Examples of possible further modifications of Output units are:

When searching for the oldest cell of a connection must not during the search operation several times a relatively older cell to actually dispensable Cell are reversed. It is sufficient, the whole designated storage area to browse and preview only Location and age of the oldest cell found to remember and then at the end of the search to only once exchange.

It is also possible, not only to exchange and the oldest cell found preferable in the output.

The shift register-like driven part of the Buffer does not necessarily constitute the end. He may also be at the beginning or in the middle of the buffer memory lie.

Finally are still examples of possible further specified modifications of the entire exchange will:

It is not mandatory that the copy switch 20 only is accessible via the group switch tenth As an an example an exchange with several sub-arrays Reference is made here to DE 38 16 747 A1. In the therein Fig. 5, the incoming and outgoing traffic in input and output units 17 and 18 on multiple divided sub-arrays. Also compounds of Sub-arrays with each other are represented there. Also, the digital switching network of SYSTEM 12 is, as For example, Figure 3a of the already mentioned article shows, divided into different switching networks, the Traffic divided by a separate access switching network becomes. However, the local switching networks ( "Levels") are identical.

It is not imperative that the original order the cells at the output of each switching matrix is restored. In itself, it is sufficient so before Leaving the switching center, ie, in the group 41, perform. There, however, come to one and the same Output line, so also in one and the same Output unit connections before that once the Group switch 10 have undergone, as well as those the main switching matrix 10 twice and additionally the Copy switch 20 have undergone. It must therefore either the minimum delay time for all Compounds are chosen very large, which also connected correspondingly large memory requirements, or has the minimum delay time for individual connections be reversible. This could include the output units in two parallel partial output units different minimum delay time to be divided.

The dimensioning, and therefore the memory requirements depend, not only the structure of the switching center and the predetermined allowable error rates, but also by the operation from.

Since copies of both the group switch 10 and in Copy switch 20 are possible, can Point-to-multipoint connections of both over a short distance, Only through the group switch 10, as well as on long Way twice through the group switch 10 and additionally are passed through the copy switch 20. Now is but at any time between the given possibilities can be switched to the current in to adapt load. This would an extreme value to auszugleichendem skew mean. This can be avoided if all Point-to-multipoint connections over the copy switch managed 20th In the main switching matrix 10 to be copied Cells should this be considered point-to-point connection via the group switch 10 and the copy switch 20 reach and only at the second passage through the Group switch copies 10th Since a total of only very few such connections are possible, would be the extra load without problems. The two Buffers in the output units of the Group 41 possible savings would however considerably.

Typical examples of point-to-multipoint connections are conferencing and audio or Television broadcasts. The associated cells represent a continuous signal stream. they occur at the transmitter at constant intervals and are at the receiver not only in the correct order, but also back to the original constant Intervals required.

The regular restoration of constant spacing is not only technically complex, it is also a different treatment of different cells Origin advance. It is easier for all cells a to strive for the same delay. Output units ensure the same delay for all the cells, put in the same compound cells forcibly also the correct order safely.

Even though an exactly equal delay of all cells in ATM in principle can not be guaranteed, so is it nevertheless possible to the output units, the cells it sort timestamps contained, and then the outputting sequentially when because of the timestamp proposed delay is reached. This implies a according to precise time distribution to all input and Output units ahead.

For ATM, it is basically advantageous same to strive maturities for all cells of a connection, ie, the "delay jitter" compensate. If this is how just indicated, with the restoration of the correct sequence combined, then the this effort required to be entirely appropriate. Currently at this case it is advantageous if, after each passage through a switch fabric immediately, ie, also in the groups 42 and 43, compensation is provided. The respective Memory overhead is minimized. As the number of Output units of the groups 42 and 43 against the Group 41 is small and straight at the output units the group 41 can be saved, resulting here total savings.

Next it must be remembered that there be meaningful can, as few different components or having to use components, which then but slightly are more expensive that it can be just as useful but, allow greater diversity of types, if for the individual modules are constructed more simply.

In view of the foregoing, may different variants make sense. The Output units of the Group 42 and Group 43 can ever be present on their own or not. Also if already in one of the groups 42 or 43, the original sequence is restored, it can be useful, in the next output unit the latest in the group 41, again the same result to use characterizing marks. Therefore also the input units of the Group 33 and Group 32 ever be present on their own or not. The Group 33 but then may not be present when the group 42 is absent; the group 32 may not exist be if the group 43 does not exist.