ATM switch with copy capability.

The invention relates to a copyable ATM switch for switching ATM cells.

one part is known the succession of copy switch, Verteilkoppelfeld and target switching matrix, on the other hand a switching matrix, can be copied to the in each stage.

Real operation, a mixture of Point-to-point connections, Point-to-multipoint connections with few branches and point-to-multipoint connections with many branches. The total traffic and the individual components are constantly changing. The known structures are each optimized one side only to a specific type of traffic.

The invention addresses the problem of specifying a copyable ATM switch, the various, also changing modes is equally matched.

The object is achieved by an ATM switch according to the teaching of the main claim. Advantageous embodiments of the invention are disclosed in the dependent claims.

The solution is based on the fundamental idea on which coupling elements of a switching network, which is optimized for point-to-point connections, in addition to bearing the ability to copy a few inputs for any number of outputs, whereby a very high total for a few input signals copy number is reached. This group switch is accompanied by a copy switch that serves exclusively the creation of a limited number of copies of each of a large number of input signals, which are then conveyed in the group switch as point-to-point connections.

Point-to-point connections in verden group switch as "connectionless connections" driven by self-control of the coupling elements. It is ensured that these compounds act outwardly as virtual connections. Point-to-multipoint connections are also in the group switch as virtual circuits (connection-oriented) operated by means of connection tables.

As "connectionless connections" are considered those compounds in which the individual cells of a connection does not go the same route, but are divided on all possible paths. This occurs quite uniform loading; on traffic measurements can be dispensed with, which it otherwise necessary devices are not required. However, there is the need to ensure the correct order of the cells veil are overtaking not excluded here.

"Connectionless connections" presuppose coupling elements, which are controlled directly by an address contained in the routing information. The copies for all point-to-multipoint connections is very difficult by means of such addressing. Examples of such coupling elements are known.

Also known are coupling elements, which are controlled by indirect addressing. As routing information this link numbers come into consideration, which are evaluated in each switching element based on connection tables. If a connection point in the connection table of a coupling element for a plurality of outputs comprise, as a copy of a cell is output with this connection number to each of these outputs.

Especially with point-to-multipoint connections can cause uneven loading of the group switch by constant change of the participants. Since the group switch but is designed primarily for "connectionless connections", it must have at its outputs devices serve to secure the correct order of the cells by any overtaking. It is therefore easily possible, rearrange existing virtual connections. This occurring at short notice overtaking is corrected as in the "connectionless connections".

The use of link numbers for point-to-multipoint connections in the group switch necessitates special precautions when a connection number to be used repeatedly. In any case, the total number of possible in the group switch point-to-multipoint connections is limited. but this purpose could be involved in such a point-to-multipoint connection in principle, all the group switch leaving lines.

More point-to-multipoint connections to allow simultaneous, separate copy switch is provided. Each input of the switch, an input of the copy switch must be accessible. It is not mandatory that each input of the copy switch from each input of the switch can be achieved. Preferably, an access via the main switching matrix, each input of the switch is connected to an input of the group switch and each input of the copy switch to an output of the group switch.

The copy switch has only the task of preparing the respective required number of copies. The placement of these copies is done in the group switch in each case like a point-to-point connection. Not every output of the copy switch network must be accessible from each of its inputs. The number of stages depends only on the copy ability of the individual coupling elements (ie, the number of outputs of the coupling elements) and the maximum required number of copies. Typically, a copy switch ranges with few steps (eg, two or three steps at 16X16-Kopp elements). Each connection point can be used here on several occasions; the number of simultaneous connections in the copy switch is thus far hardly subject to restrictions.

A switch thus constructed can handle any type of traffic. Local Internal blocking either can not occur (point-to-point connections) or be dissolved without disturbance at any time (point-to-multipoint connections). Also between the two possibilities of the point-to-multipoint connections can at any time be switched without interference to adjust the load on the current situation. This whole can be achieved in a very uniform utilization of the group switch. However, a partial blockage by fully loaded trunk lines or an overall excessive load can not be prevented.

The disadvantage can be considered that special coupling elements are required in the group switch that can operate with two different addressing options. These coupling elements may also be used where one of the two addressing options is not used, for example, in the copy switch. Such coupling elements can therefore be used as a universal coupling elements.

In the following the invention with reference to an exemplary embodiment with reference to the accompanying drawings, will be explained.<dl id="dl0001"><dt>Fig. 1</dt><dd>shows a preferred embodiment of an ATM switch according to the invention. </dd><dt>FIG. 2</dt><dd>shows a block diagram of an output unit for the exchange of the invention.</dd><dt>Fig. 3</dt><dd>shows a possible implementation for the buffer memory contained in the output unit of FIG. 2.</dd></dl>

The ATM switch of FIG. 1 has inputs I1, I2, ..., Ii, outputs O1, O2, ..., Ol, a main switching matrix 10, a copy switch 20, three sets of input units 31, 32 and 33 and three groups of output units 41, 42 and 43rd The group 31 includes i input units 311, 312, ..., 31i; the Group 32 includes j input units 321, 322, ..., 32j; the group 33 includes k input units 331, 332, ..., 33k; the group includes 41 l output units 411, 412, ..., 41l; the group includes 42 k output units 421, 422, ..., 42k; the group includes 43 j output units 431, 432, ..., 43j.

Each of the inputs I1, I2, ..., Ii of the switch is connected to input one of the input units 311, 312, ..., 31i of the group 31 is connected, the outputs of which are respectively connected to an input of the group switch 10th Each of the outputs O1, O2, ..., Ol the switch is connected to the output of the output units 411, 412, ..., 41l the group 41, whose inputs are respectively connected to an output of the group switch tenth

The inputs of the output units 421, 422, ..., 42k of the group 42 are connected to further outputs of the group switch tenth The outputs of the output units 421, 422, ..., 42k of the group 42 are connected to the input of the input units 331, 332, ..., 33k of group 33, whose outputs are connected to inputs of the copy switch 20th

The inputs of the output units 431, 432, ..., 43j of the group 43 are each connected to an output of the copy switch 20th The outputs of the output units 431, 432, ..., 43j of the group 43 are connected to the input of the input units 321, 322, ..., 32j of the group 32, whose outputs are connected to other inputs of the group switch tenth

For the present invention, it is irrelevant whether the inputs I1, I2, ..., Ii and the outputs O1, O2, ..., Ol with end stations, PBXs, remote equipment or only with other exchanges are connected. In general, the number of inputs, i, equal to the number of outputs, l, be, ie i = l.

The main switching matrix 10 includes a plurality of stages arranged in several coupling elements. It is constructed so that connections between each input and each output are possible. Examples of such coupling fields each expert.

The individual coupling elements are constructed so that they can be switched by an information contained in the cell header, between a first addressing mode, in which the cell is forwarded based on a analyzed by means of a not influenced externally algorithm routing information, and a second addressing mode, in which the cell due to the evaluated using a connection table, routing information is forwarded. It is provided that in the second type of addressing a cell can also be copied and forwarded in several ways.

ATM switching elements operating with addressing means of a not influenced externally algorithm, those skilled as well known as those which operate by means of connecting with table addressing.

As algorithm example is an assignment rule in question, as it is known for time division switching systems from "SYSTEM 12, digital switching network", Electrical Communication, Vol. 56, No. 2/3, 1981, pages 148-160. There is the possibility to address a very specific, directly predetermined by the way information output line. There is also the possibility to select the way information any output line. The given there possibility nor select a specific channel of an output line is neither possible nor necessary at ATM. A useful way the possibility to select the way information any output line from a given group of output lines. When selecting an arbitrary output line may be consulted for example the current utilization. It is also possible to address the routing information means included in the coupling element, for example to change required for addressing the second connection table.

The time required for the second addressing mode connection table may be data bits RAM with M address bits and N. The address formed by the force of this coupling element bits of the routing information, the data bits indicate that output line is output to the. If several bits are set simultaneously, the cell is output on multiple output lines, which is achieved in a simple way, a copy of cells. Instead of a single RAM and each output can be assigned a RAM with M address bits and one data be provided, for example, a 128 x 1 - RAM for M =. 7

The coupling elements must be so constructed that they can work in two different ways. This is in principle a suitable structure, such as is described with reference to Figures 3 and 5 of DE-A1 37 42 939.6. The described there part-coupling elements 22 and 24 must be replaced by a part-coupling element for the first addressing and part-coupling element for the second addressing here.

The group switch 10 is Point-to-point connections optimized. For this purpose, it is constructed and is operated so that in the first half of each cell takes any path, so that so that the traffic is divided equally. In the second half of each cell is then passed directly to your desired output. Each coupling element of the middle stage must therefore be accessible from each input of the group switch and also can reach each output of the group switch.

is preferably used as group switch, a reverse switching network. Each coupling element of the first stage is at the same coupling element of the last stage. A portion of its inputs is connected to inputs of the group switch, another part of its inputs is connected to outputs of switching elements of the last but one switching stage. Part of its outputs connected to inputs of coupling elements of the second switching stage, another part of its outputs connected to outputs of the group switch. Each coupling element of the second stage is the same coupling element of the penultimate stage, etc. The number of stages is odd. Such reverse-switching networks are known from the time division multiplexing techniques, for example from the mentioned article "SYSTEM 12, digital switching network". They have the advantage that the intermediate stages do not have to be used necessarily for each connection.

The copy switch 20 may be constructed of the same coupling elements, in which case only one of the addressing modes used. In contrast to the group switch 10 but must be accessible here not each output from each input. It is sufficient if each of input of a predetermined number of outputs can be achieved. It must also not necessarily be accessible from any input from the same number of outputs. The copy switch 20 can therefore consist of a part in which are accessible from any input from 128 and outputs from another part in which are accessible from any input from 32 outputs. Of course, it must be considered that the total volume of traffic increases from the average copy ratio from the input of the copy switch to its output through a function.

Although due to the increase of traffic, by copying the number of output units in the group 42, which is equal to the number of input units in the group 33 is smaller than the number of output units in the group 43, which equals the number of input units in the group is 32, so it's possible 32 firmly assigned to each input unit of the group of an output unit of the group 42 and each output unit of the group 43 of an input unit of the group 33rd Instead of assigning units of Group 43 to Group units 33 and a summary of the output units of group 43 to the corresponding input units of the Group 32 and a summary of the output units of group 42 to the corresponding input units of the group 33 is possible. The assignment or summary should at least allow the exchange of tax information.

Along with the formation of the group switch 10 as the reverse switching network thus created the possibility that all parts of the exchange (input and output units, coupling elements) on the normal lines of communication in a simple way to exchange control data. About additional inputs and outputs of the main switching matrix 10 different auxiliary equipment can be connected, which can exchange with all other parts of the exchange control data in the same way. However, control, diagnostics and scoring are not the subject of the present invention.

The input and output units should first be noted that all exchanges having any kinds of input and output units. Here is the only describes what is specific to the invention.

Each input unit's first task, each accompanied by instructional cell a path information. To this end, "The telecommunications engineer =", No. 9, September 1987, see pages 6 to 9 of an article by W. Schmidt in. There the basic switching sequence is described. In the cell header of each cell must necessarily a connection-specific labeling be included. From this information a way for the subsequent switching network is determined and added to the cell in the input unit on the basis of a table. It needs not to distinguish between the two types of addressing, as the data format must be the same necessarily.

In the said article are at page 7, penultimate paragraph, and "systems that work with timestamps" called. These must "determine the arrival time of a packet and the packet information to be added at the entrance of the node". If these time stamps dissolve sufficiently fine, then they can also be used to indicate the order of the cells. Although no timestamps are used per se, can be treated in the same manner to indicate the order. However, it can also be used in each input unit independent modulo N counter to, also referred to as labels of a first kind to forgive these brands. Since the correct sequence must be ensured only between the cells of each connection, can connect numbers, where they exist, are used as a criterion with excretion, they are referred to as marks of the second kind. The marks of the first type can be allocated in common for both the cells of each connection separately and for the cells of all guided through an input unit links.

Inasmuch as under input unit only is considered, which adds specific to the invention to a known ATM switch, an input unit is only needed if coming from the outside cells not already contains the sequence mark designating or if this is usable without further ado.

With reference to FIGS. 2 and 3 an embodiment of an output unit will be described. All output units are generally identical to one another. They differ mainly by the predetermined delay time.

The basic idea of ​​this embodiment resides in each cell at the output as long to stop until it is ensured that no older cell can be cached on the go longer. Before passing the cell checks whether among later arrived at the output cells is still a cell that is to be issued in advance.

This is preferably realized in that the output side, a buffer memory is provided, which is operated at least partially shift register-like, thereby causing a predetermined delay. Before issuing a cell at least the shift register-like driven part of the buffer is examined to determine whether a later registered cell is output earlier. If so, the two cells are exchanged.

In this embodiment, an output unit, a data stream is considered that is parallelized on cell width, in which therefore all the bits of a cell are passed simultaneously on parallel lines. This is not usually given more particularly advantageous. On the one hand, it is always possible to produce by serial-parallel converter, parallel-to-serial converter and cache such a data stream, on the other hand, it is within the scope of expert action, the present embodiment of a specific predetermined data format, as for example in the interior of an ATM -Vermittlungsstelle is used to adapt. It will then also be advantageous or even necessary to store not the cells themselves in the buffer memory, but only the information that is necessary to reorder and retrieval of information stored in a separate memory cells. Dealing with indirect addressing is familiar to any expert. It can be used also in the example shown, readily, in which case instead of the data in each case stores the address at which the data is actually stored.

The output unit shown in FIG. 2 includes a buffer memory 1, a memory management unit 2, two multiplexer 3 and 4, two latches 5a and 5b, two comparators 6 and 7, a further buffer memory 8 and a counter 9.

The buffer 1 has p memory locations. Each storage location is intended to contain a complete cell. For the present output unit of meaning and therefore particularly shown in Fig. 1 is a trademark per cell of the first type, sequence number, a label of a second kind, VCI (= Virtuel Circuit Identifier) ​​and the rest of the cell data. The illustration in FIG. 2 are the actual storage requirements for the individual parts not properly again.

Preferably, a modulo-N counter is used for assigning the labels of a first kind, where N is the size to choose, that less than N / 2 numbers are allocated as labels of a first kind within a predetermined time. Due to the periodic occurrence of all numbers must consist in both directions at a suitable distance to obtain uniqueness. With the specified choice of N all the cells can be clearly reconstructed in their original order, which does not further apart than said predetermined time in the allocation of numbers. This time must then be suitably set so that, apart from the authorized margin of error, ensuring that each cell within this time passes through the last r memory locations of the buffer memory. 1 As a rough guide for be predetermined time twice the difference between maximum and minimum transit time between the award of the marks of the first type and the arrival in the output unit can be assumed.

The second type brand, VCI, identifies the affiliation of a cell to a specific virtual connection.

Instead the remainder of the cell data, in the buffer memory 1 and the address can be stored under this radical is stored in another memory.

The buffer memory 1 is divided into three parts, namely a shift register-like portion, Shift Register, the locations 1 to d and operated in the manner of a FIFO memory part, FIFO again d of two parts with the storage spaces + 1 to r and composed r + 1 to p. At least the memory locations 1 to r must thereby can be accessed individually so that their contents can be read or that in it a new content can be enrolled.

The dimensioning of the buffer memory, ie the choice of the numerical values ​​for d, r and p must be carried out in a specific application. must be taken into consideration above all the allowable error rate, the minimum and maximum duration of a cell since the first branch point, the number of simultaneously authorized via an output unit compounds approved for connection minimum and maximum number of cells per unit time and an allowable fluctuation range. For a typical application, a simulation yielded values ​​of d = 10, r = 34 and p = 330 for the case that only one pass through the group switch 10 is to compensate. For point-to-multipoint connections, the first then again through the group switch 10, then the copy switch 20 and the group switch 10, the values ​​above approximately by a factor of 2 are ... to multiply 2.5, at least if only the order will be restored at the exit in the group 41st However, the mentioned values ​​are rough guidelines. The choice of the value range for the brands of the first type, sequence number is dependent on it. For the above-mentioned numerical values ​​and the connection-specific assignment of such marks N = 512 can be considered a clue.

At the entrance of the output unit incoming cells, "Cells in", are first examined it, if there are to be output at the output cells or those that terminate in the output unit. These are on the one hand empty cells, on the other hand those which control signals for the output unit (or usually associated input unit, which is not available elsewhere) included. The dispensed cells are input to the buffer memory 1 in such a way that they first "fall through" in the operated in the manner of a FIFO memory part up to the lowest free space. Whenever the output a cell is output, back in the buffer memory all the cells to a space down. If the last memory of the FIFO memory, d + 1, occupied, then the cell contained therein is incorporated in the first memory location of the shift register d. If the memory is d + 1 empty, then an empty cell must be enrolled d in the space. The duration of each cell may thus, at least relative to every other cell, derived from their position in the buffer memory. 1 The output from the buffer memory 1 will be described below.

The memory management unit 2 is shown only very schematically in Fig. 2. She's first task is to ensure the normal operation of the buffer memory 1 already described. This is done by applying addresses, Address, write commands, W, and read commands, R. In addition, not shown in Fig. 2, an information about the presence or absence of a cell to be written is required. Further, the memory management unit has 2 task is to replace the contents of the addressed by the counter 9 space, Address, to the contents of the buffer 5b, if this is a command, swap, is given.

The multiplexer 3 can be selectively accessed the contents of the memory locations 2 to r of the buffer memory 1 and passed into the buffer 5a. The selection of the memory space is performed by the counter 9, Address.

By the multiplexer 4, the content of the memory location 1 of the buffer memory 1 is transferred to the buffer memory 5b at the beginning of an issue cycle. This is the case if the counter 9 is reset, "= 0". Through a special command, swap the contents of the buffer 5a is transferred to the latch 5b by means of the multiplexer. 4 That is, inscribed by the same command, swap in the buffer memory 5b and read from this is not unusual and can be considered by the skilled person by conventional means.

By the comparator 6, the marks of the second type, VCI, of those two cells are compared with each other, which are currently stored in the buffer memories 5a and 5b. Only in case of equality of the two marks of the second type, that is, when the two cells of the same connecting members, the subsequent comparator is activated.

The comparator 7 compares the labels of a first kind, Sequence Number, the two cells contained in the latches 5a and 5b. Shows the comparator 6 indicates that both cells of the same connecting members, and it is determined that the in the buffer memory 5a cell included is older than the present in the buffer 5b, then a command, swap discharged through which the older cell into the buffer 5b and the younger cell will be reflected in their space in the buffer memory. 1 The result is that the two cells are exchanged.

The counter 9 provides for the right timing. It counts with a predetermined cycle T, periodically from 2 to r. If the counter 9 when the count r reset "= 0", an output cycle is completed and the next began. The contents of the buffer 5b, which was detected in the previous cycle as the oldest belonging to a particular compound cell is transferred to the buffer 8 and is at the output, Cells Out, available for issue. Simultaneously, the content of the memory location 1 of the buffer memory 1 is transferred via the multiplexer 4 to the buffer memory 5b. Then, the series of the same compound (marks the second type) are examined by the locations 2 through r on older cells (labels of a first kind). For this, the content is accepted in each case via the multiplexer 3 in the buffer memory 5a, and compared by the comparator 6 and 7. FIG. By the above-described exchange actions, Swap, it is ensured that when the count r of the counter 9 is actually the oldest cell of the considered link is stored in the cache 5b and that all younger cells of this compound are still or again in the buffer memory. 1

The selected in FIG. 2 showing the output unit is primarily the function of the output unit. The construction and management of the buffer with one operated in the manner of a FIFO memory part and a shift register-like driven part is clearly in the illustration chosen in FIG. 3 expressed. The distribution of clocks, including the read and write commands is not shown here.

The buffer memory is formed by a read-write memory (RAM), 1 ', realized. The incoming cells are an input memory 21 to a data bus, data, optionally, in which also the read-write memory 1 'Schlos is sen. A Einschreibsteuerung 22 is activated by the input memory 21, Busy, when a cell to be written is present. About the Einschreibzähler 23 is an address PW via an address bus, address applied to the read-write memory 1 'and the cell is written in these. Then the Einschreibezähler 23 increments of 22 from Einschreibsteuerung. A read controller 24 gives a read-out counter 25 the address, PR, to which corresponds to the space. 1 After each issue of a cell of the readout counter 25 is incremented by the read controller 24 from. The difference between the contents of the PW Einschreibzählers 23 and the content of the PR readout counter 25 must always be at least equal to d. This is monitored by the Einschreibsteuerung 22 and, optionally, FIFO empty, reported to the read controller 24 then to the data bus, data, an empty cell, Empty Cell, applying and causes the writing into the memory location indicated by the Einschreibzähler 23 and then the Einschreibzähler 23 increments.

The rest of the output unit is represented here by an access, comparator and output unit 100th

Examples of possible further modifications of the output units are:

When searching for the oldest cell of a connection does not have to repeatedly relatively older cell be exchanged for the actually dispensable cell during the search process. Suffice it to search the whole storage area provided and remember only location and age of the oldest cell found and then at the end of the search process only once to swap.

It is also possible not to swap and preferable only the oldest cell found in the output.

The shift register-like driven part of the buffer does not necessarily constitute the end. He may also be at the beginning or in the middle of the buffer memory.

Finally are still examples of possible further modifications of conciliation may be indicated:

It is not mandatory that the copy switch 20 is only accessible via the group switch tenth As an example of a switch with multiple sub-arrays is made here to DE 38 16 747 A1. In the local Fig. 5 of the incoming and outgoing traffic in the input and output units 17 and 18 is split into several sub-arrays. Also compounds of the sub-arrays with each other are represented there. Also, the digital switching network of SYSTEM 12 is, for example, Figure 3a of the already mentioned article shows, divided into different switching networks, the traffic is divided by a separate access switching network. However, the local switching networks ( "levels") are equal to each other.

It is not imperative that the original order of the cells is restored at the output of each switching network. In itself, it is sufficient to carry this out before leaving the exchange, so in the group 41. There, however, come on the same starting line, so also in one and the same output unit connections before, who only once through the group switch 10, as well as those who have the group switch 10 run twice and also the copy switch 20th So it must be either the minimum delay time for all compounds are chosen to be very large, which is also associated with a correspondingly large memory requirement, or it must be the minimum delay time to be a connection-specific switchable. For this, the output units can be divided into two parallel partial output units with different minimum delay time.

The dimensioning, and therefore the memory requirements, depend not only on the structure of the central office and the predetermined allowable error rates, but also of the operation.

Since copies of both the group switch 10 and the copy switch 20 are possible, point-to-multipoint connections can be both the shortest route, only through the group switch 10, as well as a long way twice through the group switch 10 and additionally by the copy switch 20 are performed. Now, should at any time can be switched between the given possibilities to adapt to the instantaneous load can. This would mean an extreme value at auszugleichendem skew. This can be avoided if all the point-to-multipoint connections are routed via the copy switch 20th In the main switching matrix 10 to copy cells that would then have a point-to-point connection reached via the group switch 10 and the copy switch 20 and are copied by the group switch 10 only at the second passage. Since only a very limited such compounds are possible, the extra burden would be problems. The in the buffers in the output units of the group 41 potential savings would however considerably.

Typical examples of point-to-multipoint connections are conference calling and sound or television broadcasts. The associated cells represent a continuous signal stream. They occur at the transmitter at constant intervals and requires the recipient not only in the correct order, but also back to the original constant intervals.

Regular restore constant intervals is not only technically complex, it is also a difference in treatment of cells of different origins advance. It is easier to pursue a same delay for all cells. Output units which ensure the same delay for all the cells, put in the same compound cells forcibly the correct order safely.

Even though an exactly equal delay of all cells at ATM in principle can not be guaranteed, it is still possible to sort the output units, the cells after they contain timestamps and then sequentially output when due to the timestamp the proposed delay is reached. This requires a correspondingly precise time distribution advance to all input and output units.

For ATM, it is basically advantageous to strive for equal maturities for all cells of a connection, ie, the "delay jitter" compensate. This is, as just indicated, combined with the restoration of the correct order, so the effort required for this purpose may well be appropriate. Especially in this case it is advantageous if, after each pass through a switching network immediately, ie, in the groups 42 and 43, a compensation takes place. The respective memory overhead is minimized. As the number of output units of the groups 42 and 43 to the group 41 is small and can be saved just in the output units of the group 41, here results in an overall saving.

Next it must be considered that it may be useful to have use as few different components or assemblies, but are then somewhat more complicated that it can be just as useful but to allow a greater variety of types, if for the individual modules are constructed more simply.

In view of the foregoing, different variants can be useful. The output units of the Group 42 and Group 43 can each be present on their own or not. Although already the original sequence was recovered in one of the groups 42 or 43, it may be advisable to use in the next output unit, the latest in the group 41, again the same sequence characterizing marks. Therefore, the input units of the Group 33 and Group 32 can each be present on their own or not. The group 33 may then not be present when the group 42 is absent; the group 32 may not be present when the group 43 is not present.