Process for forming semiconductor device isolation regions
Abstract
A process for forming a semiconductor device isolation region which comprises: a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon,b) etching the substrate using a resist pattern to form a trench for providing an isolation region,c) forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall of the trench,d) subsequently forming a first polycrystalline silicon film on the substrate including the trench, leaving the first polycrystalline silicon film only on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench, ande) further forming a second polycrystalline silicon film over the semiconductor substrate including the trench, leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining second polycrystalline silicon film to thereby form an oxide film.

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Every citation, both ways
| Document | Relation | Office | Category | Cited during |
|---|---|---|---|---|
| EP0278159A2 | Cites | European Patent Office (EPO) | – | Search report |
| EP0296754A2 | Cites | European Patent Office (EPO) | X | Search report |
| US4666556A | Cites | United States of America | – | Search report |
| IBM Technical Disclosure Bulletin, Vol. 28, No. 6, November 1985, pages 2583-2584; "Trench filling process", whole article. | Non-patent | – | – | Search report |
| Journal of the Electrochemical Society, Vol. 136, No. 12, December 1989, pages 3815-3820, Manchester, NH, US; R.L. GULDI et al.: "Characterization of poly-buffered LOCOS in manufacturing environment", Figure 1. | Non-patent | – | – | Search report |
| IBM Technical Disclosure Bulletin, Vol. 29, No. 3, August 1986, pages 1240-1242, New York, US; "Process for trench planarization", page 1241, paragraph 2. | Non-patent | – | – | Search report |
9 members in 5 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 4339390 | Japan | – | |
| 4339390 | Japan | A |
Members9
| Document | Office | Kind | |
|---|---|---|---|
| EP0444836A2 | European Patent Office (EPO) | A2 | |
| JPH03245553A | Japan | A | |
| EP0444836A3This record | European Patent Office (EPO) | A3 | |
| US5116779A | United States of America | A | |
| KR950000102B1 | Republic of Korea | B1 | |
| JP2597022B2 | Japan | B2 | |
| EP0444836B1 | European Patent Office (EPO) | B1 | |
| DE69132118D1 | Germany | D1 | |
| DE69132118T2 | Germany | T2 |
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Numbers
- Publication
- 0444836
- Application
- 913014577
Titles3
- German
- Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen
- English
- Process for forming semiconductor device isolation regions
- French
- Procédé pour former des régions d'isolation pour dispositifs semi-conducteurs
Classification
- CPC, 5
- H10W10/041
- H10W10/40
- H10P14/61
- H10W10/012
- H10W10/13
- IPC, 6
- H01L21 32
- H01L21 762
- H01L21 76
- H01L21 763
- H10B12 00
- H10D84 00
Designated states1
- Contracting states, 1
- United Kingdom