Method of manufacturing a semiconductor device having a trench isolation region, and device manufactured by this method.

0001This invention concerns a method of manufacturing a semiconductor device and a device so manufactured. More particularly, this invention relates to a method of forming an improved trench region for the purpose of isolation of semiconductor elements formed in a semiconductor substrate.

0002Conventionally, a trench method using trenches filled with a dielectric material and a polycrystalline silicon layer is used for the separation of semiconductor elements. Fig. 1 shows an example of a conventional trench method. At first, an insulating layer 3 of sufficient thickness to serve as a mask layer for a following etching process is formed on the surface of the epitaxial growth layer 2 of P type (or N type) formed on the semiconductor substrate 1 of N type (or P type). The insulating layer 3, e.g., a silicon oxide layer, is selectively removed by conventional photo-etching techniques to expose the surface of the layer 2 where a trench region is to be formed, as shown in Fig 1A. Next, an etching process is carried out to form trench regions 5 using the insulating layer 3 as the mask. The depth of the trench regions 5 is chosen approximately equal to the depth of an isolation region to be formed. In this condition, an ion-implantation process, using dopant of the same conductivity type to the substrate 1, is carried out to form a channel stopper region (not illustrated) beneath the trench region to reduce a parasitic MOS effect. Next, an oxidation treatment is carried out to form an insulating layer <b>4</b>, e.g., a silicon oxide layer, for the purpose of protection and partial filling of the trench regions 5. Next, a polycrystalline layer is formed to fill and cover the trench regions <b>5</b>, completely. Next, an etching process is carried out to remove any excess polycrystalline layer above the top of the trench regions <b>5(FIG 1C)</b>. Then, an oxidation treatment is carried out to form an insulating layer 7 on the top surface of the polycrystalline layer 6 to get a flat surface as shown in <b>FIG 1D</b>. In this way, insulated island regions <b>201</b>, <b>202</b> and <b>203</b> are achieved. In this conventional process, at the formation of the thick insulation film <b>4</b>, e.g., between 8,000Å and 10,000Å, great stress is applied to the corner of the trench region<b> 5</b>. In particular, since the corners are sharp, stress concentration occurs at the corners. This stress causes crystal defects 19 in the island regions <b>201</b>, <b>202</b> and the substrate <b>1</b>, as shown in <b>FIG 1E</b>. To reduce the stress during the formation of the thick insulating layer, another process using a thin insulating film has been used. <b>FIG 2</b> shows an example using a thin insulating film <b>12</b>, e.g., less than 2000Å.<b>FIG 2A</b> shows a state after the formation of insulated island regions <b>11</b> and <b>14</b>. However, in the case where a thick insulating layer <b>16</b>, such as a field oxide layer, is successively formed, wedge-shaped insulating regions are formed at the corners of the island regions <b>11</b> and <b>14</b>, as illustrated by numeral <b>17(FIG 2B)</b>. Thus, stress is applied to the corners of the epitaxial layers <b>11</b> and <b>14</b>, and crystal defects also are created. <b>FIG 3</b> shows an improved conventional process to reduce the stress concentration at the corners of the trench region by rounding the corners thereof. After forming the trench region in a semiconductor substrate <b>20</b> as illustrated in <b>FIG 3A</b>, an insulating layer <b>21</b> is formed, as illustrated in <b>FIG 3B</b>. Next, the insulating layer <b>21</b> is removed, as illustrated in <b>FIG 3C</b>. As the insulating layer <b>21</b> is formed by the reaction of oxygen diffused into the substrate <b>20</b> with the material, e.g., silicon, of the substrate <b>20</b>, the boundary between the insulating layer <b>21</b> and the substrate <b>20</b> are determined by the profile of the diffused oxygen. As the constant density line of the diffused oxygen at the corners is round, the formation of a rounded corner would be expected. However, at the formation of the insulating layer <b>21</b>, stress is also applied to the substrate. The more the stress is applied, slower the growth rate of the insulating layer becomes. As the stress concentration occurs at the corners, the growth rate of the insulating layer at the edge of the corners is slower than that at other portions. As a result, a sharp portion is formed at the corner of the trench region, as illustrated in <b>FIG 3D</b>. This process is also insufficient to round the corner. In the case where a trench capacitor( not illustrated) is formed in the trench region, the sharp portion causes a concentration of the electric field.

0003Accordingly, an object of this invention is to provide a method for effectively rounding the corners of the trench region. In accordance with one aspect of the invention, the corners of the trench region are effectively rounded by, preparing a semiconductor substrate having a first surface; forming a trench region in the first surface of the substrate, having corners at the intersections of the trench region with the first surface; forming a first polycrystalline layer over the first surface covering the corners of, and only partially filling the trench region, and oxidizing the first polycrystalline layer, thereby rounding the corners of the trench region and only partially filling the trench region.

0004In accordance with this invention, as the corners of the trench region are rounded, a thick insulating film can be formed without causing stress concentrations towards the corners of the trench region. Furthermore, the rounded corners reduce the electric concentration when a trench capacitor is formed at the trench region. Thus, the break down voltage of the trench capacitor is increased.

0005Embodiments of the invention will now be described in more detail and by way of example only with reference to the accompanying drawings, In which :- <ul id="ul0001" list-style="none"><li>Figs. 1A to 1D are cross-sectional views sequentially illustrating the steps of the one conventional process, and Fig 1E is a partial enlarged cross-sectional view of Fig. 1D.</li><li>Figs 2A and 2B are cross-sectional views sequentially illustrating the steps of another conventional process.</li><li>Figs 3A to 3C are cross-sectional views illustrating the steps of another conventional process, and <b>FIG 3D</b> is an enlarged cross-sectional view illustrating the corners of the trench region.</li><li><b>FIGS 4A to 4F</b> are cross-sectional views sequentially illustrating the steps of one embodiment of the invention.</li><li><b>FIGS 5A to 5H</b> are cross-sectional views sequentially illustrating the steps of another embodiment of the invention, and <b>FIG 5I</b> is a cross-sectional view of the trench region.</li></ul>

0006One embodiment of this invention is illustrated in <b>FIGS 4A</b> to <b>4F</b>. At first, a semiconductor substrate <b>24</b> of a first conductivity type, e.g., P type or N type is prepared. On the semiconductor substrate <b>24</b>, an epitaxial layer <b>23</b> of a second conductivity type, e.g., N type or P type, is formed. The thickness of the epitaxial layer is chosen, e.g., between 1 to 2 µm. Next, an insulating oxide layer 22 is formed by conventional oxidation treatment. The insulating layer <b>22</b> is partially removed to selectively expose the surface of the epitaxial layer <b>22</b>, as illustrated in <b>FIG 4A</b>, using a photo-etching process. Next, an etching process is carried out to form trench regions <b>25</b>, as shown in <b>FIG 4B</b>. The depth of the trench region is chosen approximately equal to the depth of an isolation region to be formed. In this etching process, it is preferable to use a dry etching process such as reactive ion etching (RIE) using the remaining insulating layer <b>22</b> as a mask, rather than a wet etching process using, e.g., HF and HNO₃, so as to prevent side etching. Next, the remaining insulating layer <b>22</b> is removed. Then a polycrystalline layer <b>27</b> is deposited over the surface by chemical vapor deposition (CVD). In this case, because of the property of the polycrystalline layer of covering the corner roundly, the corner of the trench region after the formation of the polycrystalline layer <b>27</b> becomes round. To get a good coverage of the polycrystalline layer at the corners of the trench region <b>25</b>, a low pressure CVD(LPCVD), e.g., under a reduced pressure of about 150m Torr, is preferable. The thickness of the polycrystalline layer <b>27</b> should be chosen considering the width of the trench region <b>25</b>. For example, when the width of the trench region <b>25</b> is between 1 and 1.5 µm, the thickness of the polycrystalline layer <b>27</b> is selected between a few hundred Å and 3,000 Å. Next, an oxidation treatment is carried out to convert the polycrystalline layer <b>27</b> into an insulating oxide layer <b>28</b> to fill partially the trench regions <b>25</b>, as shown in <b>FIG 4D</b>. In the case where the insulating oxide layer <b>28</b> fills the trench regions <b>25</b> completely, great stress occurs within the trench regions <b>25</b>. Therefore, great stress is applied to the epitaxial layer <b>23</b> from the side thereof. Thus, it is preferable to fill the trench regions <b>25</b> partially with the insulating oxide layers <b>28</b>. In this step, a part of the substrate <b>24</b> and the epitaxial layer <b>23</b> is also oxidized. As the corners of the trench region are covered roundly with the polycrystalline layer <b>27</b>, the stress concentrations at the corners during the formation of the insulating oxide layer <b>28</b> are reduced. Thus, the oxidation of the corners of epitaxial layer <b>23</b>, during the oxidation process of the polycrystalline layer <b>27</b>, is done substantially according to the oxygen profile diffused into the epitaxial layer <b>23</b>. As the oxygen profile at the corners of the epitaxial layer <b>23</b> is round, the corners of the epitaxial layer after the oxidation become round. Then, the insulating oxide layer <b>28</b> is removed by an etching process, e.g., wet etching using HF etchant, as shown in <b>FIG 4E</b>. As the corners of the epitaxial layer <b>23</b> are oxidized roundly, the shape of the corners after the removal of the insulating oxide layer <b>28</b> is round. Next, oxidation treatment is carried out to form an insulating oxide layer <b>29</b> serving as a protection layer of the trench region <b>25</b> and as a field oxide layer. In this oxidation treatment, as the corners of the epitaxial layer <b>23</b> are round, the stress towards the corners at the oxidation treatment is reduced. Thus, the corners are oxidized roundly in accordance with the profile of the oxigen diffused into the epitaxial layer <b>23</b> without causing stress concentrations at the corners. The thickness of the insulation layer <b>29</b> is chosen between 8,000 and 10,000 Å, for example. Next, a polycrystalline layer of sufficient thickness to fill the trench region is deposited by a CVD process. It is preferable to choose a thickness of the polycrystalline layer of more than 1.2 to 1.5 times the width of the trench region after the formation of the insulating oxide layer <b>29</b> to obtain a flat surface. Next, an etching process, e.g., a plasma etching process, is performed to remove the excess polycrystalline layer over the insulating layer <b>29</b>. Next, an oxidation treatment is carried out to form an insulating oxide layer <b>31</b> at the surface of the polycrystalline layer <b>30</b>, as shown in <b>FIG 4H</b>. In this way, epitaxial island regions <b>301</b>, <b>302</b> and <b>303</b> are achieved. Successively, circuit elements are formed in these island regions (not illustrated).

0007<b>FIGS 5A</b> to <b>5I</b> shows another embodiment of this invention. At first, a semiconductor wafer <b>51</b> of about 450 to 625 µm of a first conductivity type, e.g.,P type or N type, is prepared. Then, an oxidation treatment at a temperature of about 1100°C is carried out to form an insulating oxide film <b>52</b> of about 1 µm thickness over the surface of the semiconductor wafter <b>51</b>, as shown in <b>FIG 5A</b>. Then, a second semiconductor wafer <b>53</b>, having a mirror face, of P type or N type is positioned on the insulating layer <b>52</b> so as to face the mirror face to the insulating layer <b>52</b>. Then an annealing process of about 2 hours at a temperature of 1100°C in nitrogen atmosphere is carried out to provide a combination structure of two wafers <b>51</b>, 53 and an insulating oxide layer <b>52</b>, as shown in <b>FIG 5B</b>. Next, an etching process, including a lapping process, is applied to the wafer <b>53</b> to produce a semiconductor layer <b>54</b> of about 20µm thickness. Next, an anisotropic etching process such as RIE, is carried out to form trench regions <b>55</b> of about 1 µm width as shown in <b>FIG 5D</b>. Then, an oxidation treatment at a temperature of about 1,000°C is carried out to form a thin oxide layer <b>56</b> of about 200 Å thickness at the surface of the semiconductor substrate <b>54</b>, as shown in <b>FIG 5E</b>. As the oxide layer <b>56</b> is thin, the stress towards the corners of the trench region <b>55</b> is small. Next, a polycrystalline layer <b>57</b> of about 2,000Å thickness is formed over the entire surface, as shown in <b>FIG 5F</b>. In this case, because of the property of the polycrystalline layer of covering the corner roundly, the corners of the trench region after the formation of the polycrystalline layer <b>57</b> become round. In this forming process of the polycrystalline layer <b>57</b>, it is preferable to use LPCVD, of about 150 m Torr, to improve the coverage of the polycrystalline layer at the corners of the trench region. The structure is then subjected to an oxidation treatment at a temperature of about 1,100°C to convert the polycrystalline layer <b>57</b> into an insulating oxide layer. In <b>FIG 5G</b>, the numeral <b>58</b> designates the total insulating oxide layer of the insulating layer <b>56</b>, the converted insulating oxide layer of the polycrystalline layer <b>57</b> and the oxide layer of the semiconductor layer <b>54</b> formed during the oxidation process of the polycrystalline layer <b>57</b>. As the corners of the trench region are covered roundly with the polycrystalline layer <b>57</b>, the stress concentration at the corners during the formation of the insulating oxide layer <b>58</b> is reduced. Thus, the oxidation at the corners of semiconductor layer <b>54</b>, during the oxidation process of the polycrystalline layer <b>57</b>, is done substantially according to the oxygen profile diffused into the semiconductor region <b>54</b>. As the oxygen profile at the corners of the semiconductor region <b>54</b> is round, the corners of the semiconductor region after the oxidation of the semiconductor region <b>54</b> become round. Then, a polycrystalline layer is formed over the surface. It is preferable to choose a thickness of the polycrystalline layer of more than 1.2 to 1.5 times the width of the trench region after the formation of the insulating oxide layer <b>58</b>. Then, an etching process is carried out to remove the excess polycrystalline layer over the insulating layer <b>58</b> to produce a flat surface. Next, the construction is subjected to an oxidation treatment to form an insulating oxide layer at the surface of the polycrystalline layer 59. In this way, island regions 501, 502 and 503 surrounded by insulating material, are achieved, as shown in Fig 5H. In this embodiment, the property of the polycrystalline layer of covering the corners of trench region roundly is used, also. In the actual process, the insulating layer 52 is etched during the etching process for forming the trench regions 55. Thus, an overhanging structure of the island regions 501, 502 at the bottom of the trench region 55 is formed, as shown in Fig. 5I. However, using this invention, the bottom corners of the semiconductor layer 54 also are covered roundly with the polycrystalline layer 57. Thus, the stress concentration during formation of the thick insulating layer 58 at the bottom corners of the semiconductor region 54 is also reduced.

0008The present invention has been described with respect to specific embodiments. However, various modifications based on the principles of the present invention should be obvious to those ordinarily skilled in the art. Such modifications are intended to be covered by the claims.