Digital ic device arrangement

A digital IC device arrangement connected to a communication network line for receiving a message from a central controller also connected to said network line, the received message including a plurality of address bits and instruction bits characterized by a set of error checking bits the logic value of which is determined by the preceding bits of the received message, a serial shift register in said device for storing the received message its preceding said error checking bits, error code computing means included in said device for computing a new set of error checking bits based on the logic values of the received message bits preceding said error checking bits as said preceding message bits are stored in said serial shift register, means in said device for comparing said new set of error checking bits with a set of error checking bits of the received message on a bit by bit basis and developing an output signal if all bits of the two sets compare equally, means in said device for shifting out to said network line at least certain of the bits stored in said register to form a portion of a transmitted message, means in said device for supplying said certain bits to said error code computing means as they are shifted out of said register so that a set of transmission error checking bits is computed by said error code computer means based on the logic values of said certain bits, and means for supplying said set of transmission error checking bits to said network line as another portion of said transmitted message.