Process and device for addressing processing units

p0001The invention relates to a method for addressing processor units, as indicated in the preamble of patent claim 1, and to a circuit arrangement for carrying out the method.

p0002Such processes are already known from DE-OS No. 28 23 925. In the known methods, the addresses are set by means of coding switches, or are fixed by a special rack wiring.

p0003A method for the in-operation monitoring of a message transmission device, in which useful signals are transmitted via an electro-optical transmission path and telemetry signals via an auxiliary channel, is already known from Ewald Braun and Erhard Steiner: "Monitoring and additional services of the digital transmission systems for optical fibers", telcom report 10 1987) Special "Multiplex- und Leitungeinrichtungen", pages 109 to 114 are known.

p0004The known method uses address-free telemetry telegrams so that the processor units provided in the line terminals and intermediate regenerators of a transmission section do not need to be addressed. However, the method is not readily applicable to message transmission devices having a star or tree structure. If, in a message transmission network with a star or tree structure in the telegram transmission network of the associated telemetry device, processor units are provided which are called address controlled by a locating unit in cyclic sequence, a structure corresponding to the useful signal network can also be provided for the telegram transmission network of the telemetry device. However, the problem arises that the processor units must each be set to a specific address, not only when the telemetry device is started up, but also whenever the message transmission device changes, which necessitates a new addressing of the processor units.

p0005This problem also occurs, for example, when branching devices for distributing electrical energy or the like are to be monitored by means of a remote control device.

p0006It is therefore an object of the invention to specify a method and a circuit arrangement for carrying out the method which allow the processor units to be automatically addressed. In particular, it should be possible to automatically address devices with processor units for an in-operation monitoring of message, preferably digital signal transmission paths.

p0007In particular, a method for in-operation monitoring according to the calling method, which offers the possibility of central monitoring of digital signal transmission networks with a line, branch and / or star structure, additionally offers the advantages of self-addressing the entire network so that an elaborate and error- Manual presetting of addresses is omitted.

p0008The method according to the invention provides the method steps indicated in the characterizing part of patent claim 1 for solving this problem. A suitable circuit arrangement for carrying out the method is specified in claim 8.

p0009The method according to the invention and the circuit arrangement for carrying out the method advantageously make it possible to adjust processor units, which are connected to one another via a star-shaped or tree-shaped telegram transmission network, in a particularly simple manner automatically to different addresses. In this case, a transmission section is formed, in particular, by a digital signal base line section.

p0010Advantageous further developments of the invention are apparent from the dependent patent claims.

p0011Starting from the methods indicated in claims 1-5, one can provide that the addressing units send out a new addressing frame each time an addressing frame is received. On the other hand, the process steps indicated in claim 6 result in a particularly rapid sequence of the addressing process.

p0012The invention is explained in more detail with reference to the exemplary embodiments shown in the figures.

p0013Show it<dl id="dl0001"><dt>FIG</dt><dd>A digital signal base line section,</dd><dt>FIG</dt><dd>A line network consisting of three digital signal base line sections,</dd><dt>FIG</dt><dd>A star network containing a plurality of parallel lines,</dd><dt>FIG</dt><dd>A branched star network,</dd><dt>FIG</dt><dd>A telegram transmission network having a cascade circuit,</dd><dt>FIG</dt><dd>A telegram transmission network having a plurality of cascade circuits,</dd><dt>FIG</dt><dd>A block diagram of a versatile processor unit,</dd><dt>FIG</dt><dd>A block circuit diagram of a processor unit with a bus connection,</dd><dt>FIG</dt><dd>8 a processor unit constructed according to FIG. 8, but without a bus connection and FIG</dd><dt>FIG</dt><dd>A line network with a table for the self-addressing of processor units.</dd></dl>

p00141 is a circuit diagram of a digital signal transmission circuit according to the present invention; FIG. 2 is a circuit diagram of the digital signal transmission circuit of FIG. 1; Monitoring processor units, hereinafter referred to as processor units 6, can be controlled.

p0015The location module can be dispensed with if the processor units 6 are designed such that they can be switched as master or slave. A processor unit 6 must then be switched as a master and the tasks of the location module must be accepted and the remaining processor units must be switched as slaves.

p0016The smallest unit of a digital signal transmission path is a digital signal base line section, hereinafter referred to as line section 4. In the transmission device according to FIG. 1, the line section consists of two line terminals 1 and one or more intermediate regenerators 2, which are inserted into the line if required.

p0017A processor unit 6 is inserted into each line terminal 1 and into each intermediate regenerator 2, each of which receives the monitoring data from the main system to be monitored via an internal bus.

p0018Depending on the requirements, the location area can consist of the following structures:<ul><li>From a line which, according to FIG. 1 or FIG. 2, consists of one or more chain-connected line sections,</li><li>Corresponding to FIG. 3, from a network with several parallel lines,</li><li>According to FIG. 4 from a star network provided with branches.</li></ul>

p0019Each processor unit 6 is controlled by a microprocessor and is constructed according to FIGS. 7 to 9. It has a connection K2 in the line terminal 1 and, in the intermediate regenerator 2, two connections K1 and K2, one each for both directions, for coupling in and out into a auxiliary channel superimposed on the useful signal. In addition, a connection K3 or K3a for a network node or two connections K3, K4 or K3a, K4a for a cascade connection can be provided.

p0020Depending on the application, the connection K3a or the connections K3a, K4a is used with two unidirectional connections or the connection K3 or the connections K3, K4 with a bidirectional interface.

p0021The data of the processor units 6 are each coupled out within a line section 4 via the connections K1, K2 and are transmitted in an auxiliary channel, which is preferably superimposed on the useful signal.

p0022Within a line, the data of the processor units 6 from line terminal 1 to line terminal 1 are coupled into the auxiliary channel via the four-wire connections K 1, K 2 and, if necessary, transmitted from one line section 4 a to the next line section 4 b via the connections K 3 and K 3 a.

p0023In the arrangement shown in FIG. 2, the line sections 4a... 4c are connected in a chain. The locating module 7 is connected to the processor unit 6 of the line terminal 1 in one of the two end points of the chain circuit. A personal computer 8 is connected to this location module 7. Further personal computers 8 are connected directly to the processor unit 6 of the first line terminal 1 and to two of the intermediate regenerators 2n.

p0024Within the line sections 4a... 4c, useful signals are transmitted from line terminal 1 to line terminal 1. The data of the processor units 6 are respectively connected to the RS 485 interface via an ISM bus (in-service monitoring bus) 9 within the line sections 4a... 4c via an auxiliary channel and between the line sections 4a... 4c K3 of the processor unit 6).

p0025All the processor units 6 additionally have a connection 90, in particular with the interface RS 232 C, to which a personal computer 8 can be connected. This possibility is used in a line terminal and two intermediate regenerators.

p0026FIG. 3 shows two of a plurality of lines terminating at the network node N (branch).

p0027At the network node N, the processor units of the line terminals 1 and the location module 7 are connected to one another via the ISM bus 9 (connection K3 of the processor unit 6).

p0028According to FIG. 4, the locations A to G are connected to one another via a branched star network. Between the locations A and B are a line section 4AB without an intermediate regenerator, two line sections 4BC1, 4BC2 with an intermediate regenerator 2 between the location B and the location D, and between the locations D and F and D between the locations B and C And G is provided with a line section 4DF and 4DG, respectively. In addition, the location E is connected to the intermediate regenerator 2 of the line section 4BC2 via a line section 4E.

p0029At locations A and C, a personal computer 8 is connected to the processor unit of the line terminal 1, respectively. The personal computer 8 can optionally be connected to the ISM bus 9 with the RS 485 interface or to an additional connection of the processor unit with the RS 232 C interface. Connected to the ISM bus 9 at the location B is, in addition to the line terminals 1 of the line sections terminating there, the location module 7, which is provided with a device for polling control. The location module 7 additionally has a terminal 70 for the connection of a signal collecting device, via which the monitoring data of the star network can be retrieved from the location module 7 by the signal collecting device.

p0030In the case of a branch, the data of the processor unit 6 are transmitted between the line terminals 1 via the terminals K3 and K4, respectively, and via a network node.

p0031In the networks according to FIGS. 1 to 4, a device for sequence control, in particular a locating module 7 and / or a personal computer 8, is connected to one of the network nodes or at one of the processor units. The locating module 7 or a personal computer 8 calls the individual processor units 6 one after the other by means of a call telegram with their addresses, receives their monitoring data by means of a response telegram and evaluates this.

p0032In the following procedure for in-service monitoring, the positioning telegrams are transmitted asynchronously with a standard protocol according to IEC TC 57. Other protocols are also possible for the transmission of the telegrams, eg CCITT X25 (HDLC format). The location module queries the processing units of the entire network in the master function.

p0033The addressing of the devices is hierarchical. One byte is provided for the addressing of line sections, one byte for the addressing of the units, formed by line terminals and intermediate regenerators within a line section. The first octet of the address field contains the address of the line section, and the second octet is the device address, ie the address of the line terminal or intermediate regenerator.

p0034All addresses are given in decimal form in the following and are coded in the telegram binary.

p0035The line terminal of a line section near the location module receives the function of a so-called addressing line terminal.

p0036The task of the addressing line terminal is to initiate the self-addressing process within the associated line section. The addressing line terminal receives the request to start the self-addressing method either by sending out a start addressing frame<ul><li>The locating module during commissioning of the entire network, </li><li>A device (a line terminal or an intermediate regenerator), for example after the exchange of a unit and the associated loss of the address concerned, or</li><li>By a personal computer connected to a device within the line section.</li></ul>

p0037The start addressing frame occupies the two address bytes with address 255, which according to IEC TC 57 has the meaning of a broadcast to all of them. The command itself is contained in a so-called organization byte.

p0038In response to the start addressing frame, the addressing line terminals go into a mode which causes an intermediate storage of all telegrams coming from the interface with other digital signal base line sections. In normal operation, the telegrams are transmitted transparently on the in-service monitoring channel. The individual devices listen in parallel and only switch on when transmitting their own telegrams.

p0039In the further course of the method, a distinction is made between pure line and star or branch networks. Line networks are shown in FIGS. 1 and 2. Star nets are shown in FIGS. 3 and 4.

p0040First, the method for a line network is to be described. In this case, automatic self-addressing is possible without any manual address setting.

p0041As already mentioned, the addressing line terminals are transferred to the memory mode upon receipt of the start addressing frame. The further activities of the addressing line terminals depend on the origin of the start addressing frame. If the start addressing telegram is sent by the locating module, the addressing line terminals wait for the arrival of so-called addressing frames. The locating module, after the start addressing frame, transmits an addressing frame, which is constructed as follows, in a second step. Address fields: line section 255 (circular to all) Line terminal / intermediate regenerator 255 (broadcast to all) Organization byte: ID for addressing frame Data byte D1: 1 (consecutive address of the line section) Data byte D2: 1 (consecutive address of the line terminal / intermediate regenerator) In response to this addressing frame, all the line terminals or intermediate regenerators inherit the contents of D1 into their address memory for the line section and the contents of D2 into the address memory for the line terminals or intermediate regenerators. Furthermore, the content of D2 is incremented by each line terminal or intermediate regenerator, and a new addressing frame with the new D2 content is sent out. This second addressing frame receives all the line terminals or intermediate regenerators, with the exception of the first line terminal. They take the content of D1 (= 1) as their line section address and the content of D2 (= 2) as their device address, then increment D2 and send a new addressing frame with the new D2 content. This is passed to all the line terminals or intermediate regenerators, with the exception of the first line terminal and the first intermediate regenerator.

p0042The described cycle continues as shown in the table of FIG. 10 until the remote line terminal of the first section is reached. In this line terminal, the content of D1, ie the address of the line section, is incremented and the content of D2, ie the address of the line terminal or intermediate regenerator is reset to 1.

p0043The near line terminal, ie, the addressing line terminal of the second section, now takes 2 as a line section address and 1 as a line terminal address.

p0044The cycle continues until the remote line terminal of the last section is reached.

p0045After exchanging devices, the new units do not have any valid addresses. In this case, self-addressing is to be carried out, which can be restricted to the relevant line section.

p0046The exchanged device sends out a start addressing message during commissioning. The addressing line terminal assigned to the line section recognizes from the direction of the incoming telegram, in the example in question of the line, that it is to initiate a self-addressing operation.

p0047It sends out an addressing frame which contains an identifier in the organization byte which states that the address is to be re-addressed only within the digital signal base line section. The address of the relevant line section, which is known to the addressing line terminal, is located in byte D1 of this addressing frame. The device address is incremented by the addressing line terminal in each case according to the method already described until the remote line terminal is reached. The addressing line terminal of the following line section recognizes from the content of the organization byte that it can not forward this addressing frame.

p0048If the addressing relating to the line section is dispensed with when exchanging devices, and in this case a new addressing of the complete (line) network is performed, the addressing frames in the addressing line terminals do not have to be buffered.

p0049In the case of a star-branch structure, in the case of parallel branching of the monitoring network, presetting of the digital signal base line section addresses in the addressing line terminals is necessary, for example via switches, coding pins, soldering bridges or by input via a personal computer.

p0050Upon receipt of a start addressing frame, the addressing line terminals send addressing frames, regardless of the origin of the start addressing frame, which contain 255 as in the case of the line structure in both address fields. The corresponding line section address is located in byte D1 of the data field. The byte D2 in turn contains the continuous addresses for line terminals or intermediate regenerators. According to the method already described in the line structure, the devices of a line section are addressed to me of the fixed line section address and the continuous line terminal resp. Intermediate regenerator address.

p0051In this operating mode, the addressing line terminals do not pass on the addressing frames arriving via the interface ISM bus 9.

p0052A prerequisite for the proper functioning of the self-addressing method is that the addressing frames are always fed only in the forward direction of a line - outgoing from the addressing line terminal.

p0053In the following, the addressing operation of a digital signal base line section after replacement of a line terminal or intermediate regenerator will be described.

p0054It is advantageous to re-address all the processor units of a single line section after exchanging a line terminal or intermediate regenerator and after pulling a processor module out of the insert because of the associated address loss. The start of the address assignment within a line section is effected after the plugging in of a processor unit into the use of the new line section to be addressed and after a controlled or automatic release by the location module or the personal computer in a time slot after an interrogation cycle.

p0055The processor module inserted into the insert sends a control telegram via the connections K1 to K4 to all the processor units in the location area. The control telegram is a long telegram with the address 255 (all line sections) in the address field, with address 255 (all processor units) in the address extension and with the command "Transition to the control mode" in the organization byte of the data field.

p0056All processor units in normal operation transmit a control telegram without intermediate storage to the downstream processor units. In addition, they control the address field and address extension of the telegram and switch to the control mode after the organization byte has been evaluated.

p0057The processor unit now sends a start addressing frame to all the processor units of its line section. The start addressing frame is a long telegram with the address 255 (all digital signal base sections) in the address field, with the address 255 dec. (all processor units) in the address extension and with the command "own addressing line terminal for digital signal start section start addressing" in the organization byte of the data field.

p0058An addressing line terminal for addressing a line section carries out the command "separate addressing line terminal for addressing line addressing" only when it receives this command in a telegram via terminal K1 or K2. If this command is received in a telegram via terminal K3 or K4, this telegram is discarded.

p0059The addressing line terminals for addressing a line section generate an addressing frame with 255 in the address field, 255 in the address extension, the number of the line section in the third byte of the data field (own line section address), and 001 in the fourth byte of the data field (own processor unit -Address). Then they send this telegram to the downstream processor units.

p0060The downstream processing units in the intermediate regenerators and in the receiving line terminals at the end of each line section receive the addressing frame via one of the connections K1, K2. They directly transfer the third data byte of the addressing frame as a separate line segment address, increase the fourth data byte by 1, and then take it as a separate processor unit address. Subsequently, the content of the own address memory is inserted into the third and fourth data byte of a new addressing frame, and this is forwarded in the same or next line section via the connections K2 of the intermediate generator or K3 of the line terminal to the processor subassembly.

p0061The processor modules in the addressing line terminals for addressing a line section receive the addressing frames of an adjacent line section via the terminal K3. You reject these telegrams and do not send them further.

p0062For the proper functioning of the method, the addressing frames are only forwarded to the next processor unit but are not returned.

p0063In the case of manual addressing of the addressing line terminals 1, the addresses in the location section are set as follows.

p0064The addresses of the processor unit are composed of two bytes:<ul><li>An address byte for the number of the line section in which the processor unit is installed. </li><li>An address byte for the number of the processor unit 6 within this line section.</li></ul> In a call telegram with the transmission protocol according to eg IEC TC57, the address field contains the number of the line section 4 and the first data byte (address extension) in the data field the number of the processor unit 6 to be called within this line section.

p0065To start up the track means one of the two line terminals 1 receives at the beginning or end of each line, the function of Adr essier-line terminal for addressing phase. This function and a freely selectable line section address are assigned to the addressing line terminal 1 either by means of a coding switch or DIP-FIX switch on the processor unit 6, via coding pins in use via the connector strip of the module or via its own PC port.

p0066In order for the number of the line section 4 and the number of the processor unit in the automatic addressing of a location section to be uniformly assigned to the processor units as addresses in ascending order, it is advantageous to use the line terminal of each line which is closer to the locating module or the personal computer as addressing points Line terminal.

p0067The processor unit can be switched between two modes for the transmission of the telegrams.<ul><li>1. Normal operation: All telegrams arriving at the interfaces are immediately forwarded to the next line devices and checked by the microprocessor for their contents.</li><li>2. Memory operation: All telegrams arriving at the interfaces are only checked by the microprocessor for their contents before they are passed on to the next devices.</li></ul>

p0068The addressing process during commissioning of a line with manual addressing of the addressing line terminals proceeds as follows: The automatic address assignment is started for all processor units of a location area either by the location module, eg by means of a key, or by a personal computer 8 via its keyboard. The location module 7 or the personal computer 8 sends a start addressing frame to all the processing units of the location area.

p0069All processor units are in normal operation. The start addressing frame is a long telegram with the address 255 (all line sections 4) in the address field, with address 255 (all processor units) in the address extension and with the commands "transition to memory operation" and "addressing line terminal addressing start" in the organization byte of the data field .

p0070All processor units 6 forward the start addressing frame without intermediate storage to the downstream processor units 6. In addition, they control the address field and address extension of the telegram and switch to the memory mode after checking the organization byte.

p0071The addressing line terminals generate an addressing frame with 255 in the address field, 255 in the address extension, the number of the line sections 4 in the 3rd byte of the data field (own line section address, hereinafter referred to as L address), and 001 in FIG. Byte of the data field (own processor address, hereinafter referred to as P-address). Then they send this telegram to the downstream processor unit.

p0072The downstream processing units in the intermediate regenerators and in the receiving line terminals at the end of each line section 4 receive the addressing frame via one of the connections K1, K2. You take the 3rd data byte of the address telegram directly as your own L address, increase the 4th data byte by one, and then transfer it as your own P address. Subsequently, the content of the own address memory is inserted into the 3rd and 4th data byte of a new addressing frame, and this is forwarded to the processor unit in the next line section 4 via the connections K1 or K2 at the intermediate regenerator or K3 at the line terminal.

p0073The processor units in the transmitting line terminals receive the addressing frames via the terminal K3 (beginning of a line section). You increase the 3rd data byte by one (your own L address), overwrite the 4th data byte with 001 (your own P address) and then transfer it to the address memory. Subsequently, the content of the own address memory is inserted into the 3rd and 4th data byte of a new addressing frame and this is forwarded to the next processor unit.

p0074The processor unit in the addressing line terminals receives the addressing frames of an adjacent line section 4 via the terminal K3.

p0075You reject these telegrams and do not send them further.

p0076For the proper functioning of the method, the addressing frames are only passed on to the next processor unit 6, but are not sent back.

p0077The addressing process of a line after exchange of a line terminal or intermediate regenerator with manual addressing of the addressing line terminals proceeds as follows: After exchange of an addressing line terminal, the device receives its L address either with the aid of a coding switch or DIP-FIX switch on the processor unit , Via coding pins in use via the connector strip of the module or via a dedicated PC port.

p0078It is advantageous, after replacement of a receiving line terminal or intermediate regenerator or after pulling a processor unit belonging to these devices out of the use - because of the associated address loss - only to re-address all the processor units of a line. The start of the address assignment within a line is made after the insertion of a processor unit into the use of the new line to be addressed and after automatic release by the locating module or the personal computer in a time slot after a call cycle.

p0079The processor module plugged into the insert sends in this time slot a control telegram via the connections K1, K2 and K3 to all processor units and to the location module or the personal computer in the location area. The control telegram is a long telegram with the address 255 (all line sections 4) in the address field, with the address 255 (all processor units) in the address extension and with the command "Transition to memory operation" in the organization byte of the data field.

p0080All processor units in normal operation transmit a control telegram without intermediate storage to the downstream processor units. In addition, they control the address field and address extension of the telegram and switch to the memory mode after evaluation of the organization byte.

p0081Upon reception of the control telegram, the location module / personal computer releases a sufficient time slot for the addressing process.

p0082The processor unit now sends a start addressing frame to the processor units of its line section. The start addressing frame is a long telegram with the address 255 (all line sections 4) in the address field, with address 255 (all processor units) in the address extension and with the command "own addressing line addressing addressing" in the organization byte of the data field.

p0083An addressing line terminal carries out the command "Own addressing line terminal addressing" only if it receives this command in a telegram via the terminal K1, K2. If this command is received in a telegram via terminal K3, this telegram is discarded.

p0084The addressing line terminals generate an addressing frame with 255 in the address field, 255 in the address extension, the number of the line sections in the 3rd byte of the data field (own L address), and 001 in the 4th byte of the data field (own P address ). They then send this telegram to the downstream processor unit.

p0085The downstream processing units in the intermediate regenerators and in the receiving line terminals at the end of each line section receive the addressing frame via one of the connections K1, K2. You take the 3rd data byte of the address telegram directly as your own L address, increase the 4th data byte by one, and then transfer it as your own P address. Subsequently, the content of the own address memory is inserted into the 3rd and 4th data byte of a new addressing frame, and this is forwarded to the processor module in the next line section 4 via the connections K1, K2 in the intermediate regenerator or K3 at the line terminal.

p0086The processor units in the transmitting line terminals receive the addressing frames via the terminal K3 (beginning of a line section 4). You increase the 3rd data byte by one (your own L address), overwrite the 4th data byte with 001 (your own P address) and then transfer it to the address memory. Subsequently, the content of the own address memory is inserted into the 3rd and 4th data byte of a new addressing frame and this is forwarded to the next processor unit.

p0087The processor units in the addressing line terminals receive the addressing frames of an adjacent line section 4 via the terminal K3. You reject these telegrams and do not send them further.

p0088For the proper functioning of the method, the addressing frames are only forwarded to the next processor unit but are not returned.

p0089In the case of the previously described method, the address of the addressing line terminal must be set by means of coding pins or by input by a personal computer in the case of a branch or network node. An automatic setting of the L-address is also possible if a cascade circuit for the branching devices is used instead of a network node with parallel connection.

p0090FIG. 7 shows the block diagram of a processor module with the two terminals K3 and K4 and K3a and K4a for the cascade connection of a branch. Bidirectional buses are connected to the two terminals K3 and K4 and / or four-wire buses to the terminals K3a and K4a.

p0091FIGS. 5 and 6 show examples of the cascade circuit using the terminals K3 and K4. A network with parallel lines is shown in FIG. 5 and a network with tree structure is shown in FIG.

p0092The first device at each branch is, during addressing, an addressing line terminal with its own L address. Each processor unit of a master section 4 has the same L address and its own P address.

p0093The following procedure is provided for the sequence of addressing: Enter the network structure via the personal computer 8 into the location module 7. The network structure - number of network nodes, number of branches with one addressing line terminal at each network node, number of processor units in each line section 4 - are entered via an interactive process on the screen of the personal computer.

p0094The automatic address assignment is started for all processors of a locating area either by means of a button on the locating module, or by a personal computer via its keyboard. All processor units are in normal operation.

p0095The locating module or the personal computer sends a control telegram to all the processing units of the locating area. The control telegram is a long telegram with the address 255 (all line sections 4) in the address field, with the address 255 (all processor units) in the address extension and with the command "Transition to memory operation" in the organization byte of the data field.

p0096All processor units transmit the control telegram without intermediate storage to the downstream processor units. In addition, they control the address field and address extension of the telegram and switch to the memory mode after checking the organization byte.

p0097The location module or the personal computer now sends a start addressing frame to the first transmitting line terminal via the terminal K3 of the first network node. The start addressing frame is a long telegram with 255 in the address field, 255 in the address extension, number of the line section in the 3rd byte of the data field (assigned L address), 001 in the 4th data byte of the data field (P address) and the command "addressing line terminal Addressing "in the organization byte of the data field. By means of this telegram, this line terminal becomes an addressing line terminal. The addressing line terminal accepts the 3rd data byte and the fourth data byte into its address memory and sends the start addressing frame with an increased content of the third data byte to the next transmitting line terminal via the terminal K2 of the network node, etc.

p0098The addressing line terminals on the first network node generate an addressing frame with 255 in the address field, 255 in the address extension, the number of the line section in the 3rd byte of the data field (own L address), and 001 in the 4th byte of the data field Own P-address). They then send this telegram via the connections K1, K2 to the downstream processor unit.

p0099The downstream processing units in the intermediate regenerators and in the receiving line terminals at the end of each line section 4 receive the addressing frame via one of the connections K1, K2. You take the 3rd data byte of the address telegram directly as your own L address, increase the 4th data byte by one, and then transfer it as your own P address.

p0100The receiving line terminal does not transmit addressing frames via its terminals K1, K2.

p0101The locating module or the personal computer now calls in sequence the now addressed receiving line terminals with their address which are connected at their terminal K4 to a further line section 4 and causes them to send a start addressing frame with the predefined L address to their first transmitting line terminal.

p0102The addressing of the transmitting line terminals and of the processor units in the line sections of the next network node is performed analogously to the addressing of the first network node.

p0103For the proper functioning of the method, the addressing frames are only forwarded to the next processor unit, but are not sent back.

p0104The addressing process of a line section 4 after exchange of a line terminal or intermediate regenerator with automatic addressing of the addressing line terminals proceeds as follows: After replacing an addressing line terminal, the L addresses are re-addressed. The address assignment is started after the new insert has been inserted and after automatic release by the location module or the personal computer in a time slot after a call cycle.

p0105The processor module of the new insert sends a prompting telegram to the locating module or the personal computer in this time slot.

p0106The request telegram is a long telegram with the address 255 (all line sections) in the address field, with address 255 (all processor units) in the address extension and with the command "new addressing of the line sections" in the organization byte of the data field.

p0107After reception of this telegram by the locating module or the personal computer, the re-addressing of the power section is started.

p0108The locating module or the personal computer sends a control telegram to all the processing units of the locating area. The control telegram is a long telegram with the address 255 (all line sections) in the address field, with the address 255 (all processor units) in the address extension and with the command "Transition to memory operation" in the organization byte of the data field.

p0109All processor units transmit the control telegram without intermediate storage to the downstream processor units. In addition, they control the address field and address extension of the telegram and switch to the memory mode after checking the organization byte.

p0110The location module or the personal computer now sends a start addressing frame to the first transmitting line terminal (terminal K3) of the first network node. The start addressing program is a long telegram with 255 in the address field, 255 in the address extension, number of the line section in the 3rd byte of the data field (assigned L address), 001 in the 4th data byte of the data field (P address) and the command "addressing line terminal Addressing "in the organization byte of the data field. By means of this telegram, this line terminal becomes an addressing line terminal.

p0111The addressing line terminal accepts the 3rd data byte and the fourth data byte into its address memory and sends the start addressing frame by one increased content of the third data byte via its terminal K4 to the next addressing line end terminal (terminal K3) of the network node, etc.

p0112It is advantageous, after replacement of a receiving line terminal or intermediate regenerator or after pulling a processor module belonging to these devices out of the insert because of the associated address loss, to re-address only all processor units of a line section.

p0113The start of the address assignment within a line section is effected after the plugging in of a processor unit into the use of the new line section to be addressed and after automatic release by the location module or the personal computer in a time slot after a call cycle.

p0114The processor module inserted into the insert sends a control telegram via the connections K1, K2, K3 and K4 to all the processor units and the location module or the personal computer in the location area in this time slot. The control telegram is a long telegram with the address 255 (all line sections) in the address field, with the address 255 (all processor units) in the address extension and with the command "Transition to memory operation" in the organization byte of the data field.

p0115All processor units in normal operation transmit a control telegram without intermediate storage to the downstream processor units. In addition, they control the address field and address extension of the telegram and switch to the memory mode after evaluation of the organization byte.

p0116Upon reception of the control telegram, the locating module or the personal computer releases a sufficient time slot for the addressing process.

p0117The processor unit now sends a start addressing frame to the processor units of its line section.

p0118The start addressing frame is a long telegram with the address 255 (all line sections) in the address field, with the address 255 (all processor units) in the address extension and with the command "Own addressing line terminal addressing start" in the organization byte of the data field.

p0119An addressing line terminal carries out the command "Own addressing line terminal addressing" only if it receives this command in a telegram via the terminal K1, K2. If this command is received in a telegram via the terminal K3, K4, this telegram is discarded.

p0120The addressing line terminals generate an addressing frame with 255 in the address field, 255 in the address extension, the number of the line section in the 3rd byte of the data field (own L address), and 001 in the 4th byte of the data field (own P address ). Then they send this telegram to the downstream processor units.

p0121The downstream processing units in the intermediate regenerators and in the receiving line terminals at the end of each power section receive the addressing frame via one of the connections K1, K2. You take the 3rd data byte of the address telegram directly as your own L address, increase the 4th data byte by one, and then transfer it as your own P address. Subsequently, the content of the own address memory is inserted into the 3rd and 4th data byte of a new addressing frame and this is forwarded via the connections K1, K2 to the processor module in the next intermediate regenerator. The addressing process is terminated when the receiving line terminal of this line section is addressed. The addressing frame is only passed on within the line section 4 via the connections K1, K2.

p0122For the proper functioning of the method, the addressing frames are only forwarded to the next processor unit, but are not sent back.

p0123In the described cases, in addition to automatic address generation, manual, local address input is possible via a personal computer connected to the processor unit.

p0124FIGS. 7 to 9 show three types of processor units in principle. The processor unit shown in FIG. 7 has the advantage that it combines these three types in itself.

p0125The processor unit shown in FIG. 7 has two four-wire connections K1, K2 and the two bidirectional bus connections K3, K4 for transmitting telegrams. It can thus be used both in a line terminal 1 and in an intermediate regenerator 2.

p0126The four-wire terminal K1 has an input E1 and an output A1 for connecting a first four-wire data channel, the terminal K2 has an input E2 and an output A2 for a second four-wire data channel, the terminal K3a has an input E3 and an output A3 for connecting a third four- And the terminal K4a has an input E4 and an output A4 for connecting a fourth four-wire data channel.

p0127The transceiver module 10 is located between the four-wire connection pair E3, A3 and the bus connection K3, ie between the terminals K3a and K3, for connecting a first bi-directional bus. The control input of this transmitting and receiving module 10, The driver D serving as a transmitter can be activated is connected to the output of the OR gate 15.

p0128The transceiver module 40 consisting of the driver D and the receiver R is located between the four-wire connection pair E4, A4 and the bus connection K4, ie, between the terminals K4a and K4, for connecting a second bidirectional bus. The control input of this send and receive module 40, via which the driver D can be activated, is connected to the output of the OR circuit 45. The receiver R is constantly activated.

p0129Each of the four outputs A1, A2, A3, A4 can be connected selectively to the output of an OR element 11, 17, 41, 39, via a switch 13, 19, 43 or 37 controllable by the microprocessor 35, Pull-up resistor 12, 18, 42 or 38 or to the output of the parallel-series converter 26. This parallel-serial converter 26 is connected with its parallel input to the port PO of the microprocessor 35.

p0130The microprocessor 35 controls the change-over switch 13 via the two-wire control line St4, the changeover switch 19 via the two-wire control line St1, the change-over switch 43 via the two-wire control line St8 and the changeover switch 37 via the two-

p0131The outputs of the OR gates 11, 17, 41, 39 respectively lead to one of the outputs A1, A2, A3, A4 via the change-over switches 13, 19, 43, 37. Their inputs are respectively connected to the inputs of the three other four-wire connection pairs.

p0132The switch 16 is inserted in the connection line between the input E3 and the inputs of the OR gates 17, 41, 39. The control line of the switch 16 is connected to the output of the OR gate 15.

p0133The switch 46 is inserted in the connection line between the input E4 and the inputs of the OR gates 11, 17, 39. The control line of the switch 46 is connected to the output of the OR gate 45.

p0134The output of the OR circuit 11 is fed to the input of the OR circuit 15 via the edge detection device 14a and the time circuit 14b connected in series. The other input of the OR gate 15 is connected to the control line St3 coming from the microprocessor 35. The control input of the devices 14a, 14b is connected to the control line St5 coming from the microprocessor 35.

p0135The output of the OR circuit 41 is fed to the input of the OR circuit 45 via the edge detection device 44a and the time circuit 44b connected thereto. The other input of the OR element 45 is connected to the control line St10 coming from the microprocessor 35. The control input of the devices 44a, 44b is connected to the control line St9 coming from the microprocessor 35.

p0136The inputs E1, E2, E3, E4 are each connected to an input of one of the series-parallel converters 24, 25, 27, 28. The outputs of the series-parallel converters 24, 25, 27, 28 are connected to the microprocessor 35 via the 8-bit parallel bus 31. The signal collector 20 is also coupled to the bus 31 via the interface module 21 with the series-parallel converter 22 and the parallel-to-serial converter 23.

p0137The serial-parallel converters 22, 24, 25, 27, 28 as well as the parallel-series converters 23, 26 are contained in UART modules and interrupt the program of the microprocessor 35, if necessary, via the interrupt- Block 30. They are connected via the bus 31 to the port PO of the microprocessor 35 and are selected by the microprocessor 35 via the chip select module 29.

p0138The coding switch 51 is also connected to the port PO of the microprocessor 35 via the switch 50, with the aid of which the processor unit can be set to an address and to the function of an addressing LE.

p0139The microprocessor 35 is also connected to the RAM 32 serving as data memory, the EPROM 33 serving as program memory, the EEPROM 34 serving as a non-volatile data memory, and the self-monitoring module 36.

p0140The data transmission in normal operation proceeds as follows: The telegrams from the input E1, E3 or E4 are passed directly via the OR gate 17 and the changeover switch 19 to the output A2. Data from the input E3 also passes through the switch 16, data from the input E4 also passes through the switch 46.

p0141Data arriving at the input E2, E3 or E4 is sent to the output A1 via the OR gate 39 and the changeover switch 37. In the example shown in FIG. Data from the input E3 also passes through the switch 16, data from the input E4 also passes through the switch 46.

p0142Data arriving at the input E1, E2 or E4 are sent via the OR gate 11 and the change-over switch 13 to the driver D of the transceiver module 10 and from this to the bus connection K3. For this purpose, the change-over switch 13 must be in the normal position shown, and the driver D must be activated. The driver D is activated when the device 14a detects a rising edge and the OR element 15 receives a corresponding control potential via the device 14a, 14b and / or via the control line St3 from the microprocessor 35.

p0143If, in normal operation, data are passed to the bus connection K3 via the OR element 11, this data is also fed into the edge detection device 14a.

p0144If the edge detecting device 14a detects the rising edge of the first bit of a telegram, it starts the time circuit 14b. This time circuit outputs an output pulse which is independent of the bit sequence arriving at the input of the edge detection device 14a. The output pulse reaches the transceiver module 10 via the OR element 15 and immediately switches the driver D. Data arriving at one of the inputs E1, E2 or E4 are thus immediately forwarded to the bus connection K3 by the detection of a rising edge. The data transmitted at the bus connection K3 are received by the receiver R but are blocked in the switch 16 opened by the OR element 15.

p0145Data arriving at the input E1, E2 or E3, via the OR gate 41 and the change-over switch 43, reach the driver D of the transceiver module 40 and from this to the bus terminal K4. For this purpose, the change-over switch 43 must be in the normal position shown, and the driver D must be activated. The driver D is activated when the OR element 45 receives a corresponding control potential from the microprocessor 35 via the device 44a, 44b and / or via the control line St10.

p0146If, in normal operation, data are passed to the bus connection K4 via the OR link 41, this data is also fed into the edge detection device 44a. If the edge detection device 44a detects the rising edge of the first bit of a telegram, it starts the time circuit 44b. This time circuit outputs an output pulse which is independent of the bit sequence arriving at the input of the edge detection device 44a. The output pulse reaches the transceiver module 40 via the OR element 45 and immediately switches the driver D. Data arriving at one of the inputs E1, E2 or E3 of the processor unit 6 are thus immediately forwarded to the bus connection K4 by the detection of a rising edge. The data transmitted at the bus connection K4 are received by the receiver R but are blocked in the switch 46 opened by the OR element 45.

p0147All data arriving at the inputs E1, E2, E3, E4 are transmitted to the microprocessor 35 for processing. Data arriving at the input E1 is fed via the series-parallel converter 25, data from the input E2 via the serial-parallel converter 27, data from the input E3 via the serial-parallel converter 24 and data from the input E4 via the serial-parallel converter Serial-parallel converter 28 to the microprocessor 35.

p0148The series-parallel converters 24, 25, 27, 28 receive the data byte-by-byte, and then send an interrupt pulse via the interrupt module 30 to the microprocessor 35 whenever a byte is read in completely, the start, stop And parity conditions, and it can be taken over by the microprocessor 35 via the bus 31 at the port PO.

p0149If the microprocessor 35 determines that the data from the inputs E1, E2 or E4 meet predetermined requirements, then it activates the control line St3. As a result, the microprocessor 35 activates the driver D in the interface or transceiver module 10 via the OR circuit 15 after expiry of the time period predetermined by the time circuit 14b.

p0150If the microprocessor 35 determines that the data from the inputs E1, E2 or E3 meet predetermined requirements, it activates the control line St10. As a result, the microprocessor 35 takes over the activation of the driver D in the interface module 40 via the OR element 45 after expiry of the time interval specified by the time circuit 44b.

p0151In normal operation, data can only be transmitted at the same time via one of the inputs E1, E2, E3, E4, otherwise they are superimposed in the OR elements 11, 17, 41, 39 and thus corrupted.

p0152By means of a command "transition to memory operation" in the control telegram of the personal computer 8, the processor unit can be caused to enter the memory mode.

p0153The control telegram with the command "transition to memory operation" runs through all the processor units in normal operation. In parallel, the microprocessor 35 processes the control telegram in each processor unit and changes to the memory mode after its evaluation.

p0154If the microprocessor 35 determines, when evaluating a telegram, that predetermined requirements have not been fulfilled, it causes the processor unit to enter a memory mode.

p0155In memory mode, the data which are present at the inputs E1, E2, E3, E4 are fed to the microprocessor via the series-parallel converters 24, 25, 27, 28 for processing. After processing, the microprocessor 35 activates one to three of the control lines St1, St4, St7, St8 according to the type of telegram. As a result, the data processed in the microprocessor 35 delivered by the parallel-serial converter 26 reach only one to three of the outputs K1, K2, K3 and K4 via one to three of the change-over switches 13, 19, 43, 47 Outputs of the connections at which the telegram was not received.

p0156Each input E1, E2, E3, E4 is connected to its own series-parallel converter 24, 25, 27, 28. The microprocessor 35 recognizes by means of the interrupt pulses, via which the inputs are fed data.

p0157The control lines St1, St4, St7, St8 are activated by the microprocessor in such a way that, by means of the pulling resistors 12, 18, 42, 48, the switches A1, A2, A3, 19, 43, 47 are set to high potential.

p0158The start addressing telegrams pass through all the processor units in normal operation. In parallel, the microprocessor 35 processes the start addressing frames and goes into the memory mode.

p0159During addressing, the addressing frame may only be passed on by the processor via the parallel-to-serial converter 25 and not sent in both directions at the same time. The data arriving at the input E1 are processed in the series-parallel converter 23, the data arriving at the input E2 is processed in the series-parallel converter 27. The microprocessor 35 thus recognizes the direction from which the data come. In memory mode, therefore, the control lines St1 and the control lines St7 are activated in such a way that the output A1 or A2, which is not sent, is high via the change-over switch 19 or 47 and the pull-up or pull-up resistor 18 or 48 Potential.

p0160The signal collector 20 is connected to the microprocessor 35 via the interface module 21 and the series-parallel converter 22 and the parallel-to-serial converter 23.

p0161The signal collector 20 supplies, via the interface module 21, the monitoring data from the monitored intermediate regenerator or the monitored line terminal to the microprocessor 35 and, if appropriate, receives the control information contained in a call telegram of the locating module for transmission to a signal collecting device (not shown).

p0162Depending on the use of the processor unit in the line terminal or intermediate regenerator, the monitoring data are transmitted from the processor 35 via the parallel-serial converter 26 to three of four outputs A1, A2, A3, A4 via three of four switches 13, 19, 43, Via three of four terminals K1, K2, K3, K4.

p0163If several connections K3 are connected to one network node via a bidirectional bus at a network node, the following procedure results for the switching on and off of a bus driver:

p0164When idle, all drivers are inactive and have a high-impedance output. When data arrives at the terminal K1 or K2, the timing of the start bit initiates the timer 14b which activates the driver for at least two characters. Further holding and switching off then takes place the microprocessor 35, to which the data were fed in parallel.

p0165The processor unit shown in FIG. 8 corresponds substantially to that shown in FIG. Deviatingly, no bus connection K4 is provided. The switching means 40, 41, 42, 43, 44a, 44b, 45, 46 and 28 are missing therefrom. Instead of the triple OR gates 11, 17 and 39 in FIG. 7, the double exclusive OR gates 11a, 17a and 39a.

p0166The output of the exclusive-OR element 11a is fed to the one input of the OR element 15 via the device 14a for edge detection and the device 14b connected in series to this circuit. The other input of the OR gate 15 is connected to the control line St3 coming from the microprocessor 35 together with a control input of the devices 14a and 14b.

p0167The control input of the transmitting and receiving module 10 is connected to the output of the OR circuit 15, as shown in FIG. Deviating from FIG. 7, the driver D or the receiver R can be selectively activated by means of the control signal applied to the control input. The output pulse reaches the transceiver module 10 via the OR gate 15 and immediately turns off the driver D and the receiver R.

p0168In normal operation, the telegrams from the data input E1 are passed directly to the output A2 via the exclusive-OR element 17a and the change-over switch 19. In the return direction, the telegrams reach from the input E2 via the exclusive OR gate 39a and the switch 37 to the output A1.

p0169The exclusive-OR gate 11a, 17a, and 39a ensures that no data is transmitted when data arrives simultaneously at the inputs E1 and E2, and E1 and E3, and E2 and E3, respectively. Since no data may arrive simultaneously at the input E1, E2 and E3 during fault-free operation, data are only blocked by the exclusive OR gates 11a, 49a and 17a in the event of a fault.

p0170The processor unit shown in FIG. 9 is substantially similar to that shown in FIG. Deviatingly, no bus connection K3 is provided. The processor unit is intended for use in an intermediate regenerator and has, apart from the four-wire connections K1 and K2, only one connection for the local signal collector 20. The switching means 10, 11a, 12, 14a, 14b, 15a,