Method for controlling two storage spaces by a data processor.

p0001The invention relates to a method for controlling two storage regions by a data processor, said first memory area is fixed and only associated with the data processor, while the second memory area is expandable and is additionally controlled by other processors.

p0002Data processors of switching systems, if they are designed for maximum loads, be equipped with two storage tanks connected architecturally different. One such memory is the so-called local storage, which contains all the code of the data processor as well as local data and is optimized to provide the fastest possible access to the data processor. In the second memory is a system memory that is connected to a system bus and contains system-related information and is in addition also other processors of the system accessible. Depending on the state of development of the exchange of system memory is different in size. Since the address areas of the local memory and the system memory should not be overlapped, but only extended in the system memory for the remaining processors, the address range, but can not be moved, the demand, depending on the configuration state of the switching system the address range of the local memory results in displaced form.

p0003Object of the present invention is therefore to provide a method of the initially mentioned type which allows displaceability of the address area of ​​the first memory area, without causing by the reaction of the individual addresses to a loss of dynamics.

p0004This object is achieved for a method of the aforementioned kind in that the first memory area with a total capacity of 2ⁿ Bytes from multiple storage blocks, each 2^k Bytes is formed within an Adressierbereiches of 2^{n + i} is slidably addresses that each memory block is driven directly by means of n address bits, and that of the n - a valid bit is formed k + i most significant address, respectively which activates one of the selected memory blocks.

p0005In the method according to the invention dispenses with the control of the individual memory blocks on a transformation of the address. Only the formation of a valid bits, the most significant address are used. This eliminates in addressing the transit time through a transformation circuit so that the control of the individual memory locations can be done quickly. The formation of the valid bits is performed simultaneously for controlling the individual memory locations. The valid bit is used to retrieve a specific piece of information, this release on each memory output.

p0006The method of the invention with reference to drawings will be described in detail.

p0007Show it<ul><li>1 shows the basic construction of the controller of a communication system in which the inventive method is applicable, and </li><li>2 shows the basic control of the individual memory blocks of a memory area according to the inventive method.</li></ul>

p0008Figure 1 shows the basic structure of the control of a communication system. Heart of all controls of a communication system is a switching processor DP with the associated operating system. Such a switch processor has typically a expandable up to 16 Mbytes of memory, or local memory LM. Furthermore, has the control memory modules or system memory CM1 ... CM n containing highly integrated dynamic RAM chips. In general, each system memory has a capacity of 2 Mbytes. The call processor DP and the system memory CM1 ... CM n are connected via a standardized multibus MB. The System Save CM1 ... CM n not only the switching processor DP Access, but in addition this system memory CM1 ... CM n by the interface processors IP1 ... IPn and the processor for signaling control DCL are used. On the functions of the individual processors will not be discussed here, since they are not essential to the invention.

p0009Depending on the state of development of communication system the numbers of individual storage system is different. Since the call processor DB relies both on the local memory LM and to the system memory CM1 ... CM n, the address areas must not be overlapped. As for the other processors which can only rely on the system memory, the address areas of the system memory only be extended but can not be moved, must depend, based on the configuration status of the system, the local memory LM may be formed on the addressing displaced.

p0010In Figure 2, the actuation of movable storage areas is shown by way of example. In the example presented Darge is assumed that a storage area with a capacity of 8 MB, made up of 8 memory blocks PB1 ... SPB8 each 1 Mbyte within a 16 Mbytes-Adressierraumes to be displaced. The displacement is indicated in Figure 2 by showing a memory block JCN. For example, such a shift could take place, that the memory block PB1 is could be located at the memory block JCN associated location.

p0011So it must be implemented in accordance with the address used by the switch processor DP to control the memory. This can be done for example by means of so-called mapper circuits. This results in the disadvantage that the running time is included by the mapper in the addressing time. In conventional microprocessors for the top management class operating clock frequencies of 16 MHz and above, the mapper runtime means that at least a "wait-state" is necessary so that the performance would be reduced by at least 30 percent.

p0012Since it is assumed in the illustrated embodiment of a total storage capacity of 16 MB, are used to address a comprehensive 1-byte storage space 24 address bits A1 ... A24 necessary. Here are the invention the address bits A1 ... A23 individual memory blocks directly supplied. The twenty-fourth address bit A24 initially remains unused. This means in the embodiment shown at 16 possible arrangements for a block of memory that since the most significant bit is not evaluated, each with 2 memory blocks are simultaneously addressed, because the addresses are encoded in Example modulo 8 shown in which at each 8 Mbyte limit a wraparound is performed.

p0013The 4 most significant address bits A21 ... A24 are fed to a mapper M in the example shown, via a branch point V. This mapper M a valid G is depending on the location of the individual to be driven memory blocks formed, the respective one of the two driven Speicherblöc ke activated.

p0014It will be appreciated that the addressing time is not extended by the mapper runtime by the process according to the invention. The addressing of the individual storage spaces and the formation of the valid bits G by the mapper M takes place parallel in time. The valid G is then used to retrieve a specific piece of information - in in this embodiment, for example, two memory blocks - each share a particular memory output.