Computational method and apparatus for finite field multiplication.

Background of the Invention

0001The present invention relates to a method and apparatus for multiplying two elements in the finite field GF(2m_).

0002As explained fully in European application 0080528 from which the following discussion is taken, the finite field GF(2m) is a number system containing 2m elements. Its attractiveness in practical applications results from the ability to represent each element by a vector of m binary digits. The practical application of error-correcting codes makes considerable use of computation in GF(2_m). Both the encoding and decoding devices for the important Reed-Solomon codes must perform computations in GF(2_m). The decoding device for the binary Bose-Chaudhuri-Hocquenghem codes also must perform computation in GF(2_m). The reader is referred to "Error-Correcting Codes" by W.W. Peterson and E.J. Weldon, Jr., 2nd Ed., the M.I.T. Press, 1972, for details of these and other applications of GF(2_m) computation for error-correction.

0003There exist cryptographic systems with encryption and decryption algorithms that require exponentiation operations on large numbers. Several public-key cryptosystems have been proposed that require or may be adapted to use the exponentiation of elements in GF(2_m). Since the process of exponentiation consists of squaring and multiplication operations, it is essential that these operations be performed as quickly and efficiently as possible. The reader is referred to "Cryptography and Data Security" by D. E. Denning, Addison-Wesley, 1983, for desriptions of GF(2_m) arithmetic and exponentiation algorithms, and for examples of public-key cryptosystems utilizing these algorithms. Recent advances in the art of secrecy coding also require the use of computation in GF(2_m). The reader is referred to the letter "Implementing Public Key Scheme", by S. Berkovits, J. Kowalchuk and B. Schanning, IEEE Communications Magazine, Vol. 17, pp. 2-3, May 1979.

0004The finite field GF(2) is the number system in which the only elements are the binary numbers 0 and 1 and in which the rules of addition and multiplication are the following:<maths id="math0001" num=""><img file="EP0337985B1_D0001.tif" /></maths>These rules are commonly called modulo-two arithmetic. Hence all additions specified in logic expressions or by adders in this application are performed modulo two. In addition, multiplication is implemented with logical AND gates to correspond with the rule set out at (1) above. The finite field GF(2_m), where m is an integer greater than 1, is the number system in which there are 2_m elements and in which the rules of addition and multiplication correspond to arithmetic modulo an irreducible polynomial of degree m with coefficients in GF(2). Although in an abstract sense there is for each m only one field GF(2_m), the complexity of the logic circuitry required to perform operations in GF(2_m) depends strongly on the particular way in which the field elements are represented.

0005The conventional approach to the design of logic circuitry to perform operations in GF(2_m) is described in such papers as T. Bartee and D. Schneider, "Computation with Finite Fields", Information and Control, Vol. 6, pp. 79-98, 1963. In this conventional approach, one first chooses a polynomial P(X) of degree m which is irreducible over GF(2), that is P(X) has binary coefficients but cannot be factored into a product of polynomials with binary coefficients each of whose degree is less than m. An element A in GF(2_m) is then defined to be a root of P(X), that is, to satisfy P(A) = 0. The fact that P(X) is irreducible guarantees that the m elements AO = 1, A, A², ..., Am- of GF(2_m) are linearly independent over GF(2), that is, that b_o + b_lA + b₂A² + ... + b_m- ₁A^m-1 vanishes only when the binary digits b_o ,b₁, b₂ ... b_m-₁ are all zeroes. The conventional approach is then to assign the unit vectors of length m with binary components to the elements, 1, A, A², ..., Am-1.

0006As a specific example of the conventional approach, consider the finite field GF(2³) with the choice<maths id="math0002" num=""><img file="EP0337985B1_D0002.tif" /></maths>for the irreducible polynomial of degree 3. The next step is to define A as an element of GF(2³) such that<maths id="math0003" num=""><img file="EP0337985B1_D0003.tif" /></maths>The following assignment of unit vectors is then made:<maths id="math0004" num=""><img file="EP0337985B1_D0004.tif" /></maths>An arbitrary element B of GF(2³) is now represented by the binary vector [b₂, b₁, b_o] with the meaning that<maths id="math0005" num=""><img file="EP0337985B1_D0005.tif" /></maths>Let C = [c₂,c₁,c₀] be a second element of GF(2³). It follows from equations (4) and (5) that<maths id="math0006" num=""><img file="EP0337985B1_D0006.tif" /></maths>Thus, in the conventional approach, addition in GF(2_m) is easily performed by logic circuitry that merely forms the modulo-two sum of the two vectors representing the elements to be summed component-by-component. Multiplication is, however, considerably more complex to implement. Continuing the example, one sees from equation (3) that<maths id="math0007" num=""><img file="EP0337985B1_D0007.tif" /></maths>where use has been made of the fact that -1 = +1 in GF(2). From the equations (4), (5) and (7) it follows that<maths id="math0008" num=""><img file="EP0337985B1_D0008.tif" /></maths>where<maths id="math0009" num=""><img file="EP0337985B1_D0009.tif" /></maths>Complex logic circuitry is required to implement equations (9). Upon taking C = B equation (8), it follows from equation (9) that<maths id="math0010" num=""><img file="EP0337985B1_D0010.tif" /></maths>where<maths id="math0011" num=""><img file="EP0337985B1_D0011.tif" /></maths>and where use has been made of the facts that b² = b and b + b = 0 in GF(2). Whereas the squaring rule of equations (11) is considerably simpler to implement than the multiplication rule of equations (9), it still has the disadvantage that some additions (in the example, only one) must be performed and that the form of the squaring rule varies among the components of the square.

0007By way of summary, one can say that the conventional approach to the design of logic circuitry to perform operations in GF(2_m) leads to simple circuitry for addition, somewhat more complex circuitry for squaring, and very complex circuitry for multiplication.

0008In the European application 0080528 noted above advantage was taken of the following special features of the finite field GF(2_m). There always exists a so-called normal basis for this finite field, that is, one can always find a field element A such that A, A², A⁴, ..., A^2m-1 are a basis for GF(2m in the sense that every field element B can be uniquely written as<maths id="math0012" num=""><img file="EP0337985B1_D0012.tif" /></maths>where b_o, b₁, b₂, ..., b_m-₁ are binary digits. Moreover, squaring in GF(2^m)is a linear operation in the sense that for every pair of elements B and C in GF(2m)<maths id="math0013" num=""><img file="EP0337985B1_D0013.tif" /></maths>Further, it is the case for every element B of GF(2_m) that<maths id="math0014" num=""><img file="EP0337985B1_D0014.tif" /></maths>

0009The inventors in the above application sought to simplify the multiplication procedure by initially choosing a polynomial P(X) of degree m which is irreducible over GF(2) and which has linearly independent roots. This latter condition on P(X) insures that upon defining A as an element of GF(2_m) such that P(A) = 0 then A, A², A4, ... A^2m-1 form a normal basis for GF(2^m).

0010For a discussion of normal bases in finite fields, the reader is referred to "Finite Fields" by Lidi and Nei- dereiter. Then it B = [b_m-₁, ..., b₂, b₁, b_o] and C = [C_m-1 ..., c₂, _C1, c_o] are any two elements of GF(2_m) in said normal basis representation, than the product<maths id="math0015" num=""><img file="EP0337985B1_D0015.tif" /></maths>has the property that the same logic circuitry which when applied to the components or binary digits of the vectors representing B and C produces dm- will sequentially produce the remaining components d_m- ₂, ..., d₂, d₁, do of the product when applied to the components of the successive rotations of the vectors representing B and C.

0011This may be appreciated by considering the binary digits d₂, d₁, do of e.g. equation (9) above where<maths id="math0016" num=""><img file="EP0337985B1_D0016.tif" /></maths>Like ones of one of the binary digits b or c are grouped to obtain grouped terms so that these may be rewritten in the form<maths id="math0017" num=""><img file="EP0337985B1_D0017.tif" /></maths>Where an expression such as b_o(c₁ + c₂) is subsequently referred to as a grouped term. Thus the logic equation for d₁ could be derived from thatford₂ by reducing the suffix of all binary digits b_i, c_i, by 1 (Modulo-3). A practical implementation was achieved by entering the vectors in respective shift registers, establishing connections and implementing digital logic circuitry to generate all terms of the component d₂ simultaneously. Then the shift register contents are rotated one bit position to obtain d₁, and, similarly do. Thus, by rotating the vectors Band C in the two shift registers, the binary digits of the product vector D could be generated by the one logic circuit.

0012However, whilst the above proposal is more efficient than the conventional approach, it suffers the disadvantage that all grouped terms constituting one binary digit of the vector must be added simultaneously at one location. This makes the implementation of the logic complicated, and for large values of m, (e.g. greater than 250), impractical. The above European application also proposes the simultaneous or parallel generation of all m binary digits of the product vector by m identical multiplier logic circuits. However, this simply compounds the difficulty of logic implementation because of the increase in external shift register connections and the large amount of circuitry required.

0013The applicants have recognised that multiplication may be implemented by storing bit vectors B and C in respective shift registers and establishing connections to respective accumulating cells such that a grouped term of each of the expressions d, is generated in respective ones of m accumulating cells. By rotating the bit vectors B and C in the shift registers and by rotating the contents of the accumulating cells each grouped term of a respective binary digit d, is accumulated in successive cells. Thus all of the binary digits of the product vector are generared simultaneously in the accumulating cells after one complete rotation of the bit vectors B and C.

0014Embodiments of the invention as claimed in independent claims 1, 10 and 12 and in dependent claims 2-9, 11, and 13-18 will now be described by way of example only with reference to the accompanying drawings in which <ul id="ul0001" list-style="none"><li>Figure 1 is a block diagram of a multiplier to implement multiplication of two elements in the field GF(2⁵).</li><li>Figure 2 is a block logic diagram of a component used in the multiplier of Figure 1.</li><li>Figure 3 is a block diagram of an alternative form of multiplier to implement multiplication of two elements in the field GF(25).</li><li>Figure 4 is a block diagram of a further embodiment of a multiplier to implement multiplication in the field GF(₂₆)_.</li><li>Figure 5 is a block diagram of the multiplier of Figure 4 with the connections modified for an optimal implementation of a GF(2⁶) multiplier.</li></ul>

0015The principle of operation may best be understood by reference to Figures 1 and 2 that represents the logic implementation for multiplying two elements in the finite field GF(2⁵). Before referring to the figures in detail, it will be useful to consider the form of the product D of two elements B and C.

0016B will be of the form B = (b_o, b₁, b₂, b₃, b₄) in normal basis representation and C will be of the form C = (c_o, C₁, c₂, c₃, c₄) in normal basis representation.

0017The product D will be of the form D = (do, d₁, d₂, d₃, d₄) in normal basis representation. Each of the bit vectors d_i will consist of grouped terms of the binary digits representing B and C and for the case where m = 5<maths id="math0018" num=""><img file="EP0337985B1_D0018.tif" /></maths>

0018In general, all subscripts are added using modulo 5 arithmetic. Thus the binary digits have the form:<maths id="math0019" num=""><img file="EP0337985B1_D0019.tif" /></maths>and

0019<maths id="math0020" num=""><img file="EP0337985B1_D0020.tif" /></maths>

0020It will be appreciated from the above that by establishing logic connections to generate the first grouped term b₄ (c₄ + c₃ + c₁ + c_o) of do, the first grouped term of the binary digits d₄, d₃, d₂, and d₁ will also be generated by these same connections if the bit vectors of B and C are successively rotated one place to the right. The applicants have recognised that if connections are also established to generate the second grouped term of do after the generation of the first grouped term and the bit vectors have been rotated, the connections will in fact generate the second grouped term of d₁ prior to rotation of the bit vectors B and C. Thus by establishing connections to generate successive group terms of the binary digits do in successive clock cycles, it is possible to accumulate in parallel each of the binary digits of the product vector. This simplifies implementation of the logic.

0021Referring therefore to Figure 1, a multiplier 10 includes a pair of shift registers 12, 14 each having m cells 16. Shift registers 12 and 14 are loaded with bit vectors B and C respectively so that each cell 16 contains one of the binary digits b or c_i.

0022The shift registers 12, 14 are connected, in a manner to be described below, to the respective ones of accumulating cells 18 of a term accumulating register 20. The register 20 will have m cells 18 each of which is configured as shown in Figure 2. Referring to Figure 2, each cell 18 receives a pair of inputs 22, 24 that ordinate from the shift registers 12, 14 respectively and an input 26 from the adjacent cell 18 of the register 20. The inputs 22, 24 are connected to inputs of an AND gate 28. The output of gate 28 is added to the input 26 at MOD 2 ADDER 30 whose output is connected to a latch 32. The output of latch 32 forms the input 26 of the next cell 18 and receives a clock signal 34 to store the output of ADDER 30.

0023The nature of inputs 22, 24 is determined by the connections implemented between the cells 16 of shift registers 12, 14 and the cell 18. The connections are arranged such that one grouped term of the binary digits d_i is generated at the output of AND gate 28. Thus for the binary digits do to d₄ shown above, the binary digits b_o to b₄ and c_o to c₄ are stored in shift registers 12, 14 respectively as indicated in Figure 1. A first grouped term of do is to be accumulated in cell 18 indicated as do in Figure 1, i.e. the output of AND gate 28 will represent the grouped term b_o(c₄ + c₃ + c₂). To implement this, a connection is established from the cell 16 of shift register 12 containing the binary digit b_o to form input 22. Connections from cells 16 of shift register 14 containing binary digits c₄, c₃ and c₂ are made to ADDER 36 whose output, representing c₄ + c₃ + c₂, forms the input 24 to AND gate 28. The output of AND gate 28 will thus be b_o(c₄ + c₃⁺ c₂).

0024Connections are made between the shift register 12, 14 and the cell 18 indicated as d₁ to generate the penultimate grouped term of d₁, i.e. the term b₂(c_o + c₄). Thus cells 16 of shift register 14 containing the binary digits c_o and c₄ are connected to adder 38 whose output forms input 24 of the cell 18 designated d₁ and cell 16 of shift register 12 containing binary digit b₂ is connected as the input 22 of cell 18 designated d₁ so that the output of AND gate 28 is b₂(c_o⁺ c₄).

0025Similarly the shift registers 12, 14 are connected to the cell 18 indicated d₂ to generate the third term of binary digit d₂, i.e. b₄(c_o + _C2); to the cell 18 indicated d₃ to provide the second term of binary digit d₃, i.e. b₁(c₂ + c_o + c₄ + _C3); and to the cell 18 indicated d₄ to produce the first term of binary digit d₄, i.e. b₃(c₃ + c₂ + c_o + C₄).

0026In general, tnerefore, the jth cell 18 of accumulating register 20 is connected to the shift registers 12, 14 to produce the jth grouped term of a binary digit d_i with the subscripts of binary digits b and c_i increased by j-1 using modulo m arithmetic. This adjustment of the subscripts of the grouped term is called "offsetting" and ensures that each of the m accumulating cells generates one grouped term of each of the binary digits d_i during each of m successive clock cycles.

0027With the connections established the binary digits do to d₅ can be generated as follows.

0028First, the binary digits b_o to b₅ are loaded into shift register 12 and the binary digits c_o to c₅ are loaded into shift register 14. These may be loaded in parallel or in series as is most appropriate for the particular shift register utilised. The contents of the latches 32 of the cells 18 of accumulating register 20 are cleared by loading zeroes into each. Upon initiation of the multiplication, the grouped terms corresponding to the connections noted above will be generated at the output of each AND gate 28. Because each of the inputs 26 is zero the outputs of the MOD 2 ADDER 30 in each case will correspond to the output of the AND gate 28.

0029On the first rising edge of the clock signal, the output, of each ADDER 30 is entered into the corresponding latch 32 to appear as the input of the adjacent cell 18. Thus, latch 32 of cell 18 designated do will contain the term b_o(c₄ + c₃ + c₂), latch 32 of cell 18 designated d₁ will contain the term b₂(c_o + c₄) etc. The first rising edge of the clock signal causes the simultaneous rotation one position to the right of the contents of registers 12, 14 respectively so that the binary digits b and c are transferred to an adjacent cell. Thus, the inputs to cell 18 designated do will now be b₄ from shift register 12 and (c₁ + c₂ + c₃) from the adder 36. The output of AND gate 28 of cell 18 designated do will thus be b₄(c₁ + c₂ + c₃) . The input 26 of cell 18 (do) will be the contents of latch 32 of cell 18 (d₄), i.e. b₃(c₃ + c₂ + c_o + c₄) and thus the output of the MOD 2 ADDER 30 of cell 18 (do) will be b₄(c_{1 +} c_{2 +} ca) + b₃(c_{3 +} c_{2 +} c₀ + c₄). It will be seen that this corresponds to two grouped terms of the binary digit d₄ set out above. A careful consideration of the output of each ADDER 30 will show that the sum of two grouped terms of each binary digit d_i will appear as the input of respective latches 32.

0030On the next rising edge of the clock signal, the outputs of each ADDER 30 will be entered into respective latches 32 and the binary digits b and c rotated in the shift registers 12, 14 respectively. Thus, the contents of the latch of cell 18 (do), namely b₄(c₁ + c₂ + c₃) + b₃(c₃ + c₂ + c_o + c₄) will be present as input 26 of cell 18 (d₁) and the output of AND gate 28 of cell 18 (d₁) will be b_o(c₂ + c₃), i.e. a third grouped term of the binary digit d₄. It will be appreciated that after five clock cycles, the sum of all grouped terms of the binary digit d₄ will be stored in the latch of cell 18 designated d₃ and similarly the sum of all the grouped terms of binary digits d₃ to do will be stored in respective ones of cells 18. Thus, the bit vector constituting the normal basis representation of product D is available by reading the contents of the accumulating register 20.

0031It will also be noted that the connections from the cells 16 of shift registers 12, and 14 are distributed amongst the cells 18 of accumulating register 20 to reduce the number of inputs of any adder.

0032Whilst the above multiplier constitutes a significant improvement over that described in the European patent application 0080528, the number of connections may be reduced further although the number of clock cycles required to generate the binary digits d₁ is increased. A multiplier for the field GF(2⁵) is shown in figure 3 and is similar to that shown in figure 1. Accordingly the reference numerals used in the description of figure 1 and 2 will be used to identify like components with a prefix 100 added, i.e. reference numeral 12 will become 112. The arrangement shown in figure 3 differs in two important ways, namely the provision for exchanging the contents of shift registers 112 and 114 as indicated by dashed lines 150, 152 and the nature of the connections between the cells 116 and cells 118. It will also be noted that the shift registers 112, 114 are controlled by a separate clock signal, indicated at clock 1, to the accumulating register 120 whose clock signal is indicated at clock 2.

0033The nature of the connections is established from a further manipulation of the terms representing the binary digits d. Thus considering the binary digit d₄ above, this may be written as:<maths id="math0021" num=""><img file="EP0337985B1_D0021.tif" /></maths>and rearranged as

0034<maths id="math0022" num=""><img file="EP0337985B1_D0022.tif" /></maths>

0035It will be observed that the terms within the brackets [] possess a symmetry such that if one product term is of the form b_jc_k, the other product term is obtained by interchanging the suffixes, i.e. b_kc_j. It has been recognised that by implementing the logic to produce one product term of each pair, the other product term may be obtained from a simple interchange of the contents of the shift registers and by a repeated circuit operation each of the product terms of each pair may be obtained. Moreover, the offsetting principle still applies so that the terms of each binary digit will be generated in parallel. The expression for digit d₄ is<maths id="math0023" num=""><img file="EP0337985B1_D0023.tif" /></maths>

0036The product terms in column Yare then selected and like terms grouped as discussed above with reference to figure 1. Thus column Y may be expressed as b₃(c₂ + c₀+ c₄) + b₂(c₁ + c_o + c₄) + b₁c₄. By implementing the logic to generate these terms in successive cells 118 of accumulating register 120, the terms of column Z will also be generated after interchange of the shift registers 112,114 by a second pass through the accumulating cells. The odd term of column X may be generated during one of the two passes through the cells 118 with its generation inhibited during the other pass.

0037It will be noted that the grouped terms of column Y would require 3 inputs to two of the ADDERS whilst only 3 of the accumulating cells 118 are utilised. In order to spread the connections evenly between the cells 118, the expression is modified to select one of each pair of product terms but obtain a different grouping. Thus, in the example above, the third and sixth product terms are selected from column Z rather than Y so that the expression b₃(c₂⁺ c_o) + b₄(c₃ + c₂) + b₂ (_C1 + c_o) + b_lc₄ is to be implemented. This increases the number of cells 118 utilised and reduces the number of connections to some of the ADDERS.

0038Referring therefore to figure 3, the final term b_lc₄ is implemented in the cell 118 designated do (referred to hereafter as 118[d_o]) by connecting cell 116 of shift register 112 containing binary digit b₁ and cell 116 of shift register 114 containing binary digit c₄ to the AND gate 128. The connections to the second of cells 118 is established from a second term with the suffixes of the binary digits increased by 1, Modulo 5 i.e. b₃(c₂ + c₁) and in general the jth cell 118 accumulates 3 jth term of the expression with suffixes increased by j-1 (Modulo m).

0039Connections are also established to implement the odd term b₃c₃ of column X in cell 118 designated d₄. The connections to d₄ are modified to include an AND gate 154 to inhibit the accumulation of the add terms e.g. b₃c₃. The AND gate 154 is located between the cell 116 designated c₃ and ADDER 160 and receives as one input the output of cell 116 and as its other input an inhibit signal 156 derived from the clock signal. When the inhibit signal 156 is logic level 0, the output of AND gate 154 will be zero so that zero will be added by ADDER 130 to the contents of the latch 136 of the previous cell 118 [d_3].

0040With the connections established, the binary digits b_o to b₄ and c_o to c₄ are loaded in respective cells 116 of shift registers 112, 114. The contents of each cell 118 is cleared so that each latch 132 contains 0 and the inhibit signal 156 is held at logic level 0 to force the output of AND gate 154 to also be zero.

0041The contents of the shift registers 112, 114 and the cells 118 are then rotated one bit position rightwards by successive clock cycles so that after m clock cycles one of each part of the paired product terms is accumulated in respective cells 118. The generation of the terms is shown in table 1 below.

0042Thus, it will be seen that the terms in d₄ correspond to the rewritten expression for one of each of the pairs of product terms.

0043After five clock cycles, registers 112, 114 will have undergone a complete rotation so that binary digits b and c_j will be stored in the cells 116 in which they were initially loaded.

0044Now the contents of the shift registers 112 and 114 are exchanged through connections 150, 152. This may be accomplished by shifting the contents of both registers 112,114 forfive clock cycles as a serial, circular exchange or alternately could be achieved by parallel connections between cells 116. Serial exchange is shown in Figure 4 and is easiest to implement for large values of m. During the exchange, clock 1 goes through five cycles while clock 2 is held low to prevent unwanted terms accumulating in register 120. When binary digits d, pass through accumulating cells, both clock signals are identical.

0045After the exchange of binary digits, the inhibit signal 156 is set to logic level 1 so that AND gate 154 passes the input from cell 116 to the input of ADDER 160. The circuit operation then continues as exemplified by the table below for the next five clock cycles. Again, it will be seen that the terms of each of the binary digits d, are accumulated in each of the cells 118 in parallel so that after 2m clock cycles of computation the binary digits of D are available in the cells 118 of accumulating register 120. Because of the need to exchange the contents of the shift registers 112, 114, additional clock cycles are required to complete the computation. However, the number of the connections between the shift registers and the accumulating register in the multiplier of Figure 3 is less than those shown in the multiplier of Figure 1 to compensate for this.

0046The implementation shown in Figure 3 has been used to illustrate the generality of the above principle. However, in practical implementations particularly for large values of m, the connections may be simplified further by selecting the grouped terms in ascending order of the coefficient b or c_i. In this manner a maximum of two connections between each cell of one of the shift registers and the accumulating register is obtained.

0047In order to reduce the time taken to compute the binary digits d, the multiplier of Figure 3 can be further modified as shown in Figure 4. Again like components to those referred to in the description of Figures 1 and 2 will be identified by like reference numerals with a prefix 200 added for clarity. Figure 4 shows a multiplier for generating the binary digits d, in the field GF(2⁶). It will be noted that the shift registers 212 and 214 have been segmented into 3 units, 212a, b, or c and 214 a, b or c respectively, each having two cells 116. Similarly, the accumulating register 220 is segmented into 3 units 220 a, b or c each having two cells. It will be noted that each of the shift register units 212 a, b, and c is connected to a corresponding shift register unit 214 a, b and c by paths 250 a, b, c, and 252 a, b, c respectively. The paths 250,252 are utilised to exchange the contents of the registers 212, 214 between units a, b and c rather than through the entire shift register. In this way the number of clock cycles necessary to transfer the contents of the shift register is reduced from m to the number of cells 216 in each unit.

0048The binary digit d₅ of product D in GF(2⁶) is given by<maths id="math0024" num=""><img file="EP0337985B1_D0024.tif" /></maths>

0049Thus by implementing the expression b_o(c₃ + c₅) + b₁c₂ + b₂(c_o + c₅) + b_ac₁⁺ b₄c₂⁺ b₅(c₄⁺ c₅) the binary digits d_i of the normal basis representation of the product D can be generated. It is believed to be apparent from the above discussion that the initial connections to be established are as follows: <tables id="tabl0001" num="0001"><img file="EP0337985B1_D0025.tif" /></tables>

0050In this case, the odd term is generated initially in cell 218 [d_5] and the input to the adder 236 associated with cell 218 [d_5] that is initially from the cell 216 containing digit c₄ is inhibited after the first pass through the accumulating register 220 by use of an AND gate in a manner similar to that shown in Figure 3.

0051The operation of the multiplier of figure 4 is similar to that described above with reference to figure 3. However, exchange of the contents of the registers 212, 214 occurs over the lines 250, 252 to reduce from 6 to 2 the number of clock cycles necessary to complete the exchange.

0052It is believed the above examples clearly and explicitly explain the operation of GF(2_m) the multiplier. Relatively small values of m have been selected for the sake of simplicity but it will be apparent that the above principles apply for large values of m usually employed in encryption.

0053However, for the larger values of m usually utilised in encryption, the number of product terms in the expression for binary digit d, may increase quadratically with the value of m. This renders the implementation of a multiplier impractical because of the large number of connections necessary. For those values of m listed in Table 3 there does exist an optimal normal basis in the sense that it yields an expression d, that has 2m-1 product terms, the smallest number possible. Each of the integers m has an indication of type for use in the computer program discussed below. The binary digits bc of the binary digit do of the product vector D for the optimal normal basis of a value of m listed in Table 3 may be obtained executing the computer program listed in appendix 1. By running the program for m=6 the following results were obtained:<maths id="math0025" num=""><img file="EP0337985B1_D0026.tif" /></maths>which yields the equation for do as:

0054<maths id="math0026" num=""><img file="EP0337985B1_D0027.tif" /></maths>Figure 5 shows the implementation of this expression for the segmented GF(2⁶) multiplier shown in Figure 4 with appropriate modifications to the connections to implement the above. The rearrangement of do to obtain these connections will be apparent from the above and consideration of Figure 5.

0055An optimal multiplier design exists for every value of m listed in Table 3 such that every accumulating cell 218 has a single input from the same shift register cell 216. Thus, m modulo-two ADDERS are eliminated as compared to the multipliers of Figures 1, 3 and 4 further simplifying the circuitry.

0056In addition, the applicants believe that the maximum number of connections to the output of any shift register cell 216 is three.

0057The above description has utilised block diagram representations of the registers 12, 14, 20 and the adders and logic functions. However, it is believed that the selection and operation of the components to perform the functions discussed above will be apparent to a person skilled in the art of digital logic design and that further particularisation of the components is not necessary.

0058Clearly different offset patterns may be chosen whilst utilising the principle of parallel generation of terms of each of the binary digits of d_i. <tables id="tabl0002" num="0002"><img file="EP0337985B1_D0028.tif" /></tables><tables id="tabl0003" num="0003"><img file="EP0337985B1_D0029.tif" /></tables><tables id="tabl0004" num="0004"><img file="EP0337985B1_D0030.tif" /></tables><tables id="tabl0005" num="0005"><img file="EP0337985B1_D0031.tif" /></tables><tables id="tabl0006" num="0006"><img file="EP0337985B1_D0032.tif" /></tables><tables id="tabl0007" num="0007"><img file="EP0337985B1_D0033.tif" /></tables><img file="EP0337985B1_D0034.tif" /><img file="EP0337985B1_D0035.tif" /><img file="EP0337985B1_D0036.tif" /><img file="EP0337985B1_D0037.tif" /><img file="EP0337985B1_D0038.tif" />