Computational method and apparatus for finite field multiplication.

Description of equivalent WO 8804805 A1

COMPUTATIONAL METHOD AND APPARATUS FOR FINITE FIELD MULTIPLICATION

0002Background of the Invention

0003The present invention relates to a method and apparatus for multiplying two elements in the finite field GF(2 ) .

0004As explained fully in European application 0080528 from which the following discussion is taken, the finite field

0005GF(2 ) is a number system containing 2 elements. Its attractiveness in practical applications results from the ability to represent each element by a vector of m binary digits. The practical application of error-correcting codes makes considerable use of computation in GF(2 ) . Both the encoding and decoding devices for the important Reed-Solomon codes must perform computations in G (2^m) . The decoding device for the binary Bo_.se-Chaudhuri-Hocquenghem codes also must perform computation in- GF(2 ) . The reader is referred to

0006"Error-Correcting Codes" by W. . Peterson and E.J. Weldon, Jr. ,

00072nd Ed., the M.I.T. Press, 1972, for details of these and other applications of GF(2 ) computation for error-co rection.

0008There exist cryptographic systems with encryption and decryption algorithms that require exponenti tion operations on large numbers. Several public-key cryptosyste s have been proposed that require or may be adapted to use the exponentiation of elements in GF(2 ) . Since the process of exponentiation consists of squaring and multiplication operations, it is essential that these operations be performed as quickly and efficiently as possible. The reader is referred to "Cryptography and Data Security" by D . E. Denning, Addison-Wesley, 1983, for desriptions of GF(2 ) arithmetic and exponentiation algorithms, and for examples of public-key cryptosystems utilizing these algorithms.

0009Recent advances in the art of secrecy coding also require the use of computation in GF(2 ) . The reader is referred to the letter "Implementing Public Key Scheme", by S. Berkovits, J. Kowalchuk and B. Schanning , IEEE Communications Magazine, Vol. 17, pp. 2-3, May 1979.

0010The finite field GF(2) is the number system in which the only elements are the binary numbers 0 and 1 and in which the rules of addition and multiplication are the following:

00110 + 0 = 1 + 1 = 0

00120 + 1 = 1 + 0 = 1

00130 x 0 = 1 x 0 = 0 x 1 = 0 (1)

00141 x 1 = 1 These rules are commonly called modulo-two arithmetic. Hence all additions specified in logic expressions or by adders in this application are performed modulo two. In addition, multiplication is implemented with logical AND gates to correspond with the rule set out at (1) above. The finite field GF(2 ) , where m is an integer greater than l_r is the number system in which there are 2 elements and in which the rules of addition and multiplica ion correspond to arithmetic modulo an irreducible polynomial of degree with coefficients in GF(2) . Although in an abstract sense there is for each m only one field GF(2 ) , the complexity of the logic circuitry required to perform operations in GF(2 ) depends strongly on the particular way in which the field elements are represented.

0015The conventional approach to the design of logic circuitry to perform operations in GF^~(2 ) is described in such papers as T. Bartee and D. Schneider, "Computation with Finite Fields", Information and Control, Vol. 6, pp. 79-98, 1963. In this conventional approach, one first chooses a polynomial P(X) of degree m which is irreducible over GF(2) , that is P(X) has binary coefficients but cannot be factored into a product of polynomials with binary coefficients each of whose degree is less than m. An element A in GF(2 ) is then defined to be a root of P(X) , that is, to satisfy P(A) = 0. The fact that P(X)

00160 2 is irreducible guarantees that the m elements A = 1, A, A ,

0017... , A of GF(2 ) are linearly independent over GF(2) , that is, that b_Q + b A + b₂A + ... + b_m__xA vanishes only when the binary digits b_,b ,b ... , b are all zeroes. The conventional approach is then to assign the unit vectors of length m with binary components to the elements,

00181, A, A , ... , A •

0019As a specific example of the conventional approach, consider the finite field GF(2 ) with the choice

0020p (X) = x^J + x + l for the irreducible polynomial of degree 3 The next step is to define A as an element of GF(2^) such that

0021A³ + A + 1 0 (3) The following assignment of unit vectors is then made:

0022A° = 1 = [0, 0, 1]

0023A = [0, 1, 0] A² = [1, 0, 0] (4)

0024An arbitrary element B of GF(2^) is now represented by the binary vector [b2, ]_, bg] with the meaning that

0025B = [b₂,b₁,b₀] = b₂A² + b_χA + b₀ (5)

0026Let C = [C₂,C;L,CgJ be a second element of GF(2³) . It follows from equations (4) and (5) that

0027B + C = [b₂ + c₂rb₁ + CJL^O + c₀]. (6)

0028Thus, in the conventional approach, addition in GF (2 ) is easily performed by logic circuitry that merely forms the modulo-two sum of the two vectors representing the elements to be summed component-by-component. Multiplication is, however, considerably more complex to implement. Continuing the example, one sees from equation (3) that

0029A³ = A + 1

0030A⁴ = A² + A (7) where use has been made of the fact that -1 = +1 in GF (2) . From the equations (4) , (5) and (7) it follows that

0031B x C - [d₂, d_j_, d₀] _. (8) where ^d0 ^=b0^cQ ^{+ b}l^c2 ^{+ b}2^c l

0032<img file="WO8804805A1_D0001.tif" />

0033d₂ = bgc₂ + b C + b_]_C_} + b₂c₂ Complex logic circuitry is required to implement equations (9) . Upon taking C = B equation (8) , it follows from equation (9) th

0034B² = [e₂, e_x, e₀] (10) where eg = bg ex = b₂ (11) e₂ = b_χ + b₂

00352 and where use has been made of the facts that b = b and b + b = 0 in GF (2) . Whereas the squaring rule of equations (11) is considerably simpler to implement than the multiplication rule of equations (9) , it still has the disadvantage that some additions (in the example, only one ) must be performed and tha the form of the squaring rule varies among the components of th square.

0036By way of summary, one can say that the conventional approach to the design of logic circuitry to perform operations in GF(2 ) leads to simple circuitry for addition, somewhat more complex circuitry for squaring, and very complex circuitry for multiplication.

0037In the European application 0080528 noted above advantage was taken of the following special features of the finite field GF(2 ) . There always exists a so-called normal basis for this finite field, that is, one can always find a field element A such that A, A2, A4, . . . , A '?~^l~- are a basis for GF(2^m in the sense that every field element B can be uniquely written as

0038<img file="WO8804805A1_D0002.tif" />

0039^{" [b}m-l' ' ^~2 ' ^bl' ^b0^]

0040where g, b-,, b₂, . . . , ^b_m__τ are binary digits,

0041Moreover, squaring in GF(2^m is a linear operation in the sense that for every pair of elements B and C in GF(2^m)

0042(B + C)² = B² + C² (13)

0043Further, it is the case for every element B of GF(2^m) that

0044_m B = B (14)

0045The inventors in the above application sought to simplify the multiplication procedure by initially choosing a polynomial P(X) of degree m which is irreducible over GF(2) and which has linearly independent roots. This latter condition on P(X) insures that upon defining A as an element of GF(2^m such that P(A) = 0 then A, A 2 , A4, ... A2^m-1 form a normal basis for GF(2^m).

0046For a discussion of normal bases in finite fields, the reader is referred to "Finite Fields" by Lidl and Neidereiter. Then it B = [b and m-1'

0047C = [c , c , c , c ] are any two elements of m-1'

0048,m

0049GF(2 ) in said normal basis representation, then the product

0050D = B X C = [d m-1. , .-., d 2 , d 1 , d_n0] (15)

0051has the property that the same logic circuitry which when applied to the components or binary digits of the vectors representing B and C produces d _, will sequentially produce the remaining components d ., ..., d„ , d. , d_n of the m-2 2 1 0 product when applied to the components of the successive rotations of the vectors representing B and C.

0052This may be appreciated by considering the binary digits d_ , d , d of e.g. equation (9) above where

0053do = b_lCl + bgC! + b^g + b C₂ + b₂Cg ^dl = ^b0^c0 ^{+ b}2^c0 ^{+ b}0^c2 ^{+ b}2^cl ^{+ b}l^c2 d₀ = b₂c₂ -i- b!C₂ + b₂c_χ + b_lC + b_QCl

0054Like ones of one of the binary digits b_j_ or c₁ are grouped to obtain grouped terms so that these may be rewritten in the form d₂ = y (c_j_ + c₂) + c₀ (b_λ + b₂) + <img file="WO8804805A1_D0003.tif" /> d_]_ = b (Cg + C_j_) + C₂ (bg + b_]_) + bgCg d = _χ (C₂ + Cg) + _Cχ (b₂ + bg) + D₂C₂

0055Where an expression such as bg(C_j_ + c ) is subsequently referred to as a grouped term. Thus the logic equation for d_j_ could be derived from that for d₂ by reducing the suffix of all binary digits b., c, by 1 (Modulo-3) . A practical implementation was achieved by entering the vectors in respective shift registers, establishing connections and implementing digital logic circuitry to generate all terms of the component d_ simultaneously. Then the shift register contents are rotated one bit position to obtain d , and, similarly d_n . Thus, by rotating the vectors B and C in the two shift registers, the binary digits of the product vector D could be generated by the one logic circuit.

0056However, whilst the above proposal is more efficient than the conventional approach, it suffers the disadvantage that all grouped terms constituting one binary digit of the vector must be added simultaneously at one location. This-makes the implementation of the logic complicated, and for large values of , (e.g. greater than 250) , impractical. The above European application also proposes the simultaneous or parallel generation of all m binary digits of the product vector by m identical multiplier logic circuits. However, this simply compounds the difficulty of logic implementation because of the increase in external shift register connections and the large amount of circuitry required.

0057The applicants have recognised that multiplication may be implemented by storing bit vectors B and C in respective shift registers and establishing connections to respective accumulating cells such that a grouped term of each of the expressions d. is generated in respective ones of accumulating cells. By rotating the bit vectors B and C in the shift registers and by rotating the contents of the accumulating cells each grouped term of a respective binary digit d. is accumulated in successive cells. Thus all of the binary digits of the product vector are generated simultaneously in the accumulating cells after one complete rotation of the bit vectors B and C.

0058Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which

0059Figure 1 is a block diagram of a multiplier to implement multiplication of two elements in the field GF(2 ) .

0060Figure 2 is a block logic diagram of a component used in the multiplier of Figure 1.

0061Figure 3 is a block diagram of an alternative form of multiplier to implement multiplication of two elements in the field GF(2⁵) .

0062Figure 4 is a block diagram of a further embodiment of a multiplier to implement multiplication in the field GF(2 ) .

0063Figure 5 is a block diagram of the multiplier of Figure 4 with the connections modified for an optimal implementation of a GF(2⁶) multiplier.

0064The principle of operation may best be understood by reference to Figures 1 and 2 that represents the logic implementation for multiplying two elements in the finite field GF(2 ) . Before referring to the figures in detail, it will be useful to consider the form of the product D of two elements B and C . B will be of the form B = (b_Q, b,, b₂, b₃, b. ) in normal basis representation and C will be of the form C = (c_Q, c,, c₂, c₃, c.) in normal basis representation.

0065The product D will be of the form D = (d_Q, d, , d₂, d₃, d- ) in normal basis represen¬ tation. Each of the bit vectors d. will consist of grouped terms of the binary digits representing B and C and for the case where = 5 ^di^=bi+4^(ci+4 ^{+ c}i+3^{+ C}i+1^{+ C}i^{} + b}i+3

0066^(ci+4^{+ C}i+2^{+ C}i+1^{+ C}i^{) + b}i+2^(ci+3^{+ C}i⁾ + -_± + 1 (c_i+4 + c_i+3) <img file="WO8804805A1_D0004.tif" />

0067In general, all subscripts are added using modulo 5 arithmetic. Thus the binary digits have the form: d_Q = b₄(c₄+c₃+c₁+c₀) + b₃(c₄+c₂+c₁+c₀)+ b₂(c₃+c_Q) + b₁(c₄+c₃) + b_Q(c₄+c₃+c₂)

0068^dl ^{= b}0^(c0 ^{+ c}4 ^{+ c}2 ^{+ c}l^{} + b}4^(c0 ^{+ c}3 ⁺^~₂ + _± ) + b₃(c₄ + c_χ) + ₂(c_Q + c₄) + ^bl^(c0 ^{+ c}4 ^{+ c}3⁾₂ = b₁(c₁ + c_Q + c₃ + c₂) + b_Q(c₁ + c₄ + c₃ + c₂) + b₄(c_Q + c₂) + b₃(c₁ + c_Q) + ^b2^(cl ^{+ c}0 ^{+ c}4⁾^d3 ^{= b}2^(c2 ^{+ C}l ^{+ C}4 ^{+ c}3^{) + b}li^c2 ^{+ C}0 ⁺ c₄ ÷ c₃) + h_Q { c_λ + c₃) + b₄(c₂ + c_± ) + b₃(c₂ + c_± + c_Q) and d₄ = b₃(c₃ + c₂ + c_Q + c₄) + b₂(c₃ + c-, + ^c0 ^{+ C}A ^{) + b}l^(c2 ^{+ c}4^{) + b}0^(c3 ^{+ c}2 ^{) +} b₄(G₃ + ~ + Cn ) - li ¬ lt will be appreciated from the above that by establishing logic connections to generate the first grouped term b. (c„ + c, + c, + c_) of d_n , the first grouped 4 4 3 1 0 ϋ term of the binary digits d , d , d , and d will also be generated by these same connections if the bit vectors of B and C are successively rotated one place to the right. The applicants have recognised tha if connections are also established to generate the second grouped term of d after the generation of the first grouped term and the bit vectors have been rotated, the connections will in fact generate the second grouped term of d, prior to rotation of the bit vectors B and C. Thus by establishing connections to generate successive group terms of the binary digits d„ in successive clock cycles, it is possible to accumulate in parallel each of the binary digits of the product vector. This simplifies implementation of the logic.

0069Referring therefore to Figure 1, a multiplier 10 includes a pair of shift registers 12, 14 each having m cells 16. Shift registers 12 and 14 are loaded with bit vectors B and C respectively so that^'each cell 16 contains one of the binary d igi ts b . or c ..

0070^ 1 1

0071The shift registers 12, 14 are connected, in a manner to be described below, to the respective ones of accumulating cells 18 of a term accumulating register 20. The register 20 will have m cells 18 each of which is configured as shown in Figure 2. Referring to Figure 2, each ceil 18 receives a pair of inputs 22, 24 that originate from the shift registers 12, 14 -Ir¬

0072respectively and an input 26 from the adjacent cell 18 of the register 20. The inputs 22, 24 are connected to inputs of an AND gate 28. The output of gate 28 is added to the input 26 at MOD 2 ADDER 30 whose output is connected to a latch 32. The output of latch 32 forms the input 26 of the next cell 18 and receives a clock signal 34 to store the output of ADDER 30.

0073The nature of inputs 22, 24 is determined by the connections implemented between the cells 16 of shift registers 12, 14 and the cell 18. The connections are arranged such that one grouped term of the binary digits d. is generated at the output of AND gate 28. Thus for the binary digits d to ₄ shown above, the binary digits b_Q to b₄ and c to c₄ are stored in shift registers 12, 14 respectively as indicated in Figure 1. A first grouped term of d_Q is to be accumulated in cell 18 indicated as d_Q in Figure 1, i.e. the output of AND gate 42 will represent the grouped term ^b_n(^c4 + c₃ + c₂). To implement this, a connection is established from the cell 16 of shift register 12 containing the binary digit b_Q to form input 22. Connections from cells 16 of shift^' register 14 containing binary digits c₄, c₃ and c₂ are made to ADDER 36 whose output, representing c₄ + c₃ + c₂, forms the input 24 to AND gate 28. The output of AND gate 28 will thus be b_Q(c₄ + c₃ + c₂) .

0074Connections are made between the shift register 12, 14 and the cell 18 indicated as d₁ to generate the penultimate grouped term of d-^, i.e. the term b₂(c_Q + c₄). Thus cells 16 of shift register 14 containing the binary digits c and c. are connected to adder 38 whose output forms input 24 of the cell 18 designated d and cell 16 of shift register 12 containing binary digit b_? is connected as the input 22 of cell 18 designated d. so that the output of AND gate 28 is b₂(c_Q + c₄) .

0075Similarly the shift registers 12, 14 are connected to the cell 18 indicated d₂ to generate the third term of binary digit d„ , i.e. b (c. + c~) ; to the cell 18 indicated d., to provide the second term of binary digit d.. , i.e. b, (c_ + c_n + c + c-.) ; and to the cell 18 indicated 1 2 0 4 3 d. to produce the first term of binary digit d , i.e. b₃(c₃ + c₂ + c_Q + c₄) .

0076In general, therefore, the jth cell 18 of accumulating register 20 is connected to the shift registers 12, 14 to produce the jth grouped term of a binary digit d. with the subscripts of binary digits b. and c, increased by j-1 using modulo arithmetic. This adjustment of the subscripts of the grouped term is called "offsetting" and ensures that each of the m accumulating cells generates one grouped term of each of the binary digits d. during each of m successive clock cycles.

0077With the connections established the binary digits d_n to d_ς can be generated as follows.

0078First, the binary digits b_ to b are loaded into shift register 12 and the binary digits c_n to c_c are loaded

00790 5 into shift register 14. These may be loaded in parallel or in series as is most appropriate for the particular shift register utilised. The contents of the latches 32 of the cells 18 of accumulating register 20 are cleared by loading zeroes into each. Upon initation of the multiplication, the grouped terms corresponding to the connections noted above will be generated at the output of each AND gate 28. Because each of the inputs 26 is zero the outputs of the MOD 2 ADDER 30 in each case will correspond to the output of the AND gate 28.

0080On the first rising edge of the clock signal, the output, of each ADDER 30 is entered into the corresponding latch 32 to appear as the input of the adjacent cell 18. Thus, latch 32 of cell 18 designated d« will contain the term b„ (c . + c₃ + c₂) , latch 32 of cell 18 designated d, will contain the term b~ (c_fl + c.) etc. The first rising edge of the clock, signal causes the simultaneous rotation one position to the right of the contents of registers 12, 14 respectively so that the binary ^J dig ~its b1. and c1. are transferred to an adjacent cell. Thus, the inputs to cell 18 designated d_n will now be b. from shift register 12 and (c, + c„ + c-.) from the adder 36. The output of AND gate 28 of cell 18 designated d_Q will thus be (c. + c₂ + c^ ) . The input 26 of cell 18 (d_Q) will be the contents of latch 32 of cell 18 (d₄) , i.e. b₃ (c₃ + c₂ + c_Q + c₄) and thus the output of the MOD 2 ADDER 30 of cell 18 (d_Q) will be ₄(_C;L + c₂ + c₃) + b₃(c₃ + c₂ + c_Q + c₄) . It will be seen that this corresponds to two grouped terms of the binary digit d. set out above. A careful consideration of the output of each ADDER 30 will show that the sum of two grouped terms of each binary digit d. will appear as the input of respective latches 32.

0081On the next rising edge of the clock signal, the outputs of each ADDER 30 will be entered into respective latches 32 and the binary digits b. and c. rotated in the shift registers 12, 14 respectively. Thus, the contents of the latch of cell 18 (d_Q) , namely b₄ (c_χ + c₂ + c₃) + b₃ (c₃ + c , + c + c.) will be present as input 26 of cell 18 (d ) and the output of AND gate 28 of cell 18 (d,) will be b_n (c + c-. ) , i.e. a third grouped term of the binary digit d₄. It will be appreciated that after five clock cycles, the sum of all grouped terms of the binary digit d. will be stored in the latch of cell 18 designated d-, and similarly the sum of all the grouped terms of binary digits d-. to d„ will be stored in respective ones of cells 18. Thus, the bit vector constituting the normal basis representation of product D is available by reading the :ontents of the accumulating register 20.

0082It will also be noted the connections from the cells 16 of shift registers 12, and 14 are distributed amongst the cells 18 of accumulating register 20 to reduce the number of inputs of any adder.

0083Whilst the above multiplier constitutes a significant improvement over tha described in the European patent application 0080528, the number of connections may be reduced further although the number of clock cycles required to generate the binary digits d, is increased. A multiplier for the

0084- 5 field GF(2 ) is shown in figure 3 and is similar to that shown in figure 1. Accordingly the reference numerals used in the description of figure 1 and 2 will be used to identify like components with a prefix 100 added, i.e. reference numeral 12 will become 112. The arrangement shown in figure 3 differs in two important ways, namely the provision for exchang¬ ing the contents of shift registers 112 and 114 as indicated by dashed lines 150, 152 and the nature of the connections between the cells 116 and cells 118. It will also be noted that the shift registers 112, 114 are controlled by a separate clock signal, indicated at clock 1, to the accumulating register 120 whose clock signal is indicated at clock 2.

0085The nature of the connections is established from a further manipulation of the terms representing the binary digits d.. Thus considering the binary digit d₄ above, this may be written as: b₃c₃+b₃c₂+b₃c₀+b₃c₄+b₂c₃+b₂c₁+b₂Cg+ b₂c₄+b₁c₂+b₁c₄+b₀c₃+b₄c₃+b₄c₂+b₄c₁ and rearranged as b₃c₃+[b₃c₂+b₂c₃] + [b₃c₀+b_Qc₃] + [b₃c₄ + b₄c₃] + [b₂c₁ + b₁c₂] + b₂c₄ + b₄c₂]

0086^[bl^c4 ^{+ b}4^cl^] It will be observed tha the terms within the brackets

0087[] possess a symmetry such that if one product term is of the form b.c, , the other product term is obtained by j k interchanging the suffixes, i.e. b.c.. It has been

0088K j recognised that by implementing the logic to produce one product term of each pair, the other product term may be obtained from a simple interchange of the contents of th^~e shift registers and by a repeated circuit operation each of the product terms of each pair may be obtained. Moreover, the offsetting principle still applies so that the terms of each binary digit will be generated in parallel. The expression for digit d. is

0089b₃c₃ + ^bb33^CC22 D₂C₃

0090+ + ^b3^C0 ^b0^C3

0091+ + ^b3^C4 *4^C3

0092+ + 2^Cl ^bl^C2

0093+ + ^b2^C0 ^b0^C2

0094+ +

0095^D2^C4 ^b4^C2 <img file="WO8804805A1_D0005.tif" />

0096The product terms in column Y are then selected and like terms grouped as discussed above with reference to figure

00971. Thus column Y may be expressed as b,. (c_ + c. + c ) + b 2_(c1_η + c0- + c4.) + b.1c4,,. By implementing the logic to generate these terms in successive cells 118 of accumulating register 120, the terms of column Z will also be generated after interchange of the shift registers 112, 114 by a second pass through the accumulating cells. The odd term of column X may be generated during one of the two passes through the cells 118 with its generation inhibited during the other pass.

0098It will be noted that the grouped terms of column Y would require 3 inputs to two of the ADDERS whilst only 3 of the accumulating cells 118 are utilised. In order to spread the connections evenly between the cells 118, the expression is modified to select one of each pair of product terras but obtain a different grouping. Thus, in the example above, the third and sixth product terms are selected from column Z rather than Y so that the expression b-, (c₂ + c_Q) + b (c., + c₂) + b₂ (c, + c_fi) + b,c, is to "be implemented. This increases the number of cells 118 utilised and reduces the number of connections to some of the ADDERS.

0099Referring therefore to figure 3, the final term b,c. is implemented in the cell 118 designated d 1 4 o

0100(referred to hereafter as 118 [d ] } by connecting cell 116 of shift register 112 containing binary digit b, and cell 116 of shift register 114 containing binary digit c, to the AND gate 128. The connections to the second of cells 118 is established from a second term with the suffixes of the binary digits increased by 1, Modulo 5 i.e. b, (c^ + c, ) and in general the jth cell 118 accumulates a jth term of the expression with suffixes increased by j-1 (Modulo m) .

0101Connections are also established to implement the odd term b~c of col .ax X in cell 118 designated d . The connections to d are modified to include an AND gate 154 to inhibit the accumulation of the add terms e.g. b-.c . The

0102AND gate 154 is located between the cell 116 designated c, and

0103ADDER 160 and receives as one input the output of cell 116 and as its other input an inhibit signal 156 derived from the clock signal. When the inhibit signal 156 is logic level 0, the output of AND gate 154 will be zero so that zero will be added by ADDER 130 to the contents of the latch 136 of the previous cell 118 [d₃] -

0104With the connections established, the binary digits „ to b _Λ and c„ to c are loaded in respective cells 116 0 4 0 4 of shift registers 112, 114. The contents of each cell 118 is cleared so that each latch 132 contains 0 and the inhibit signal 156 is held at logic level 0 to force the output of AND gate 154 to also be zero.

0105The contents of the shift registers 112, 114 and the cells 118 are then rotated one bit position rightwards by successive clock cycles so that after clock cycles one of each part of the paired product terms is accumulated in respective cells 118. The generation of the terms is shown in table 1 below.

0106Thus, it will be seen that the terms in d₄ correspond to the rewritten expression for one of each of the pairs of product terms.

0107After five clock cycles, registers 112, 114 will have undergone a complete rotation so that binary digits b. and c - will be stored in the cells 116 in which they were initially loaded.

0108- Now the contents of the shift registers 112 and 114 are exchanged through connections 150, 152. This may be accomplished by shifting the contents of both registers 112, 114 for five clock cycles as a serial, circular exchange or alternately could be achieved by parallel connections between cells 116. Serial exchange is shown in Figure 4 and is easiest to implement for large values of m. During the exchange, clock 1 goes through five cycles while clock 2 is held low to prevent unwanted terms accumulating in register 120. When binary digits d. pass through accumulating cells, both clock signals are identical.

0109After the exchange of binary digits, the inhibit signal 156 is set to logic level 1 so that AND gate 154 passes the input from cell 116 to the input of ADDER 160. The circuit operation then continues as exemplified by the table below for the next five clock cycles. Again, it will be seen that the terms of each of the binary digits d. are accumulated in each of the cells 118 in parallel so that after 2m clock cycles of computation the binary digits of D are available in the cells 118 of accumulating register 120. Because of the need to exchange the contents of the shift registers 112, 114, additional clock cycles are required to complete the computation. However, the number of the connections between the shift registers and the accumulating register in the multiplier of Figure 3 is less than those shown in the multiplier of Figure 1 to compensate for this.

0110The implementation shown in Figure 3 has been used to illustrate the generality of the above principle. However, in practical implementations particularly for large valves of m, the connections may be simplified further by selecting the grouped terms in ascending order of the coefficient b. or c.. In this manner a maximum of two connections between each

01111 cell of one of the shift registers and the accumulating register is obtained.

0112In order to reduce the time taken to compute the binary digits d. , the multiplier of Figure 3 can be further modified as shown in Figure 4. Again like components will be identified by like reference numerals with a prefix 2 added for clarity. Figure 4 shows a multiplier for generating the binary digits d. in the field GF(2⁶) . It will be noted that the shift registers 212 and 214 have been segmented into 3 units, 212a, b, or c and 214 a, b or c respectively, each having two cells 116. Similarly, the accumulating register 220 is segmented into 3 units 220 a, b or c each having two cells. It will be noted that each of the shift register units 212 a, b, and c is connected to a corresponding shift register unit 214 a, b and c by paths 250 a, b, c, and 252 a, b, c respectively. The paths 250,252 are utilised to exchange the contents of the registers 212, 214 between units a, b and c rather than through the entire shift register. In this way the number of clock cycles necessary to transfer the contents of the shift register is reduced from m to the number of cells 216 in each unit.

0113The binary digit d,. of product D in GF (2 ) is given by

0114d₅ = b₅c₅ + b₅c₄ + b₄c₅

0115+ b₂c₅ + b₅c₂

0116^{+ b}0^C5 ^{+ b}50 + b_lC2 + b^

0117+ b^ + b_χc₃

0118+ b₄c₂ + b₂c₄

0119^{+ b}0°3 ^{+ b}3°0 + b₂c_Q + b_Qc₂

0120Thus by implementing the expression b_Q (c₃ + c₅) + b₁c₂ + b₂(c_Q + C₅) + b₃c_χ + b.c₂ + b_ς {c . + c₅) the binary digits d. of the normal basis representation of the product D can be generated. It is believed to be apparent from the above discussion that the initial connections to be established are as follows: cell 118 physical connection

0121<img file="WO8804805A1_D0006.tif" />^dl ^b2^C3 <img file="WO8804805A1_D0007.tif" />^d3 ^b0^C4 ^d4 ^b2^C0 ^d5 ^b4^(C3 ^{+ C}4^}

0122In this case, the odd term is generated initially in cell 218 [d_ς] and the input to the adder 236 associated with cell 218 [d_c] that is initially from the cell 216 containing digit c. is inhibited after the first pass tnrough the accumulating register 220 by use of an AND gate in a manner similar to that shown in Figure 3.

0123The operation of the multiplier of figure 4 is similar to that described above with reference to figure 3. However, exchange of the contents of the registers 212, 214 occurs over the lines 250, 252 to reduce from 6 to 2 the number of clock cycles necessary to complete the exchange.

0124It is believed the above examples clearly and explicitly explain the operation of GF (2 ) the multiplier. Relatively small values of m have been selected for the sake of simplicity but it will be apparent that the above principles apply for large values of usually employed in encryption.

0125However, for the larger values of usually utilised in encryption, the number of product terms in the expression for binary digit d may increase quadratically with the value of m. This renders the implementation of a multiplier impractical because of the large number of connections necessary. For those values of m listed in Table 3 there does exist an optimal normal basis in the sense that it yields an expression d. that has 2m-l product terms, the smallest number possible. Each of the integers m has an indication of type for use in the computer program discussed below. The binary digits b.c. of the binary digit d„ of the product vector D for the optimal normal basis of a value of m listed in Table 3 may be obtained executing the computer program listed in appendix 1. By running the program for m=6 the following results were obtained:

0126^do - 5 5 0 1 1 0 4 1 1 4 5 3 3 5 4 2 2 4 3 2 3 which yields the equation for d„ as:

0127^d0 ^{= b}5^C5 ^{+ b}0^+Cl ^{+ b}l^C0 ^{+ b}4^Cl ^{+ b}l^C4 ⁺ b₅c₃ +b₃c₅ + b₄c₂ + b₂c₄ + b₃c₂ + b₂c₃

0128Figure 5 shows the implementation of this expression for the segmented GF(2 ) multiplier shown in Figure 4 with appropriate modifications to the connections to implement the above. The rearrangement of d„ to obtain these connections will be apparent from the above and consideration of Figure 5.

0129An optimal multiplier design exists for every value of m listed in Table 3 such that every accumulating cell 218 has a single input from same shift register cell 216. Thus, m modulo-two ADDERS are eliminated as compared to the multipliers of Figures 1, 3 and 4 further simplifying the circuitry.

0130In addition, the applicants believe that the maximum number of connections to the output of any shift register cell 216 is three.

0131The above description has utilised block diagram representations of the registers 12, 14, 20 and the adders and logic functions. However, it is believed that the selection and operation of the components to perform the functions discussed above will be apparent to a person skilled in the art of digital logic design and that further particula risation of the components is not necessary.

0132Clearly different offset patterns may be chosen whilst utilising the principle of parallel generation of terms of each of the binary digits of d.. -26- α Ci o

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2478 TYPE 2 2483 - TYPE 2 2486 - TYPE 2 2493 - TYPE 2

0353^■32- APPENDIX I

0354^include Cstdio.r

03558de f i ne HA>N 2560 maximum ield deare- * / 8de f i ne MAXN32 ^βO array width */

03569de f i ne UORO 32 word size in bits «/ βde f i ne HEX6 ⁽ unsi gned ⁾ 0X80000000 /_* most sig bi t in a word * / in βde f ine HEX4 QX4QQQQQQ0 /* second most sig i t a word */ βde f ine ONE 01 /* least sig bit (oc ta L ) */ βdefine ALl-ONE QXFFFFFF FF / * al L one. vector

0357int ; int N32; unsigned po lyCMAXN3 3;

0358<img file="WO8804805A1_D0015.tif" />

0359in argc; char *argvC ];

0360/^«

0361Program to compute the coefficients b and c of an optimaL rauLtiply equa ion for digit dO of product vector D = B * C where Q t C , and D are the normal basis represen a ions of- eLements in the Galois Field GF(2**m ).

0362Source Language : C under UNIX 0/S Author : Ivan M. Onyszchu

0363Date Last Modified : hay 24, 19S5 2:04 am Modification : uocumen tat ion added

0364Execution : ⁽program name) n type

0365Result : dO eultiply equation, 2»-1 p.i rs of coefficients b and c. IF an invalid value of m or type i. en tered/ an error message printed. /* variable declarations */ unsigned 'BPCMAXN]; unsigned «DPCMAXN3; unsigned *BICf1AXN3; unsigned m&lt;*sK/ i t erms ut/ o t 1/ b/^* int type/ unsigned * suap/' register int i /" register int j -

0366register int k register int i; <img file="WO8804805A1_D0016.tif" /> register unsigned *bp/ _**b1/ _{* *}b2; register unsigned * dp/ *b3 »b4; register unsigned temp/ temp2; unsigned betd1CMAXN323; unsigned be ta2C( AXN32]/' unsigned one MAXN32 ]; unsigned twoC MA N323;

0367/* Read in value of m and type */

0368N = atoi C argvl 1 ]); type = atoi CargvC23); N32 = (N - 1 ) / WORD + 1; f or ( i = 0; i &lt;= N32; i + + ) polyCi D = oneCi l = tuoCi ] = beta1Ci 3 = 0;

0369/* Compute generating polynomial _*/ i f &lt; ⁽ type ! = 1 ) 4&amp; C type ! = 2 ) ) goto next; if C type == 2 ) &lt;

0370«tuo = HEXS;

0371"one = HEX8 ! HEX4; f or( i = 1 ; i ; i ++ ) &lt;

0372"poly = *tuo ^Λ C*one >> 1 ); or ( j =0; j < N32; j ++ ) polyCj D = twoCj D ^Λ ((one[ j-1 ] & ONE ) ?

0373⁽ oneC j D > 1 : Hfc" Xti > ; ( oneC j 3 >> i ; <img file="WO8804805A1_D0017.tif" /> twoCj ] = oneCJ]; <img file="WO8804805A1_D0018.tif" />

0374>

0375i f C t pe 1 ) &lt; for ( j = 1 ; j N32; j + *^• ) poiyc j -1 : = A LONE; polyCN32- 13 = 0X80000000 7? C N X WORD ),

0376for-( i = o; i &lt; N; i + ) &lt;:

0377BPCi D = (unsi ed _* ) calloc (N32/ si zeof( unsigned ))-^'

0378DPC i J = (unsigned calloc (N32/ sizeof( unsigned));

0379BIC i 3 = (unsigned * ) calLoc C N32 si z.eof( unsigned)); > for ( i = 0; i < N32; i++ ) i

0380*(beta1 -r i ) = 0;

0381*( be t<*2 + i ) = 0; > xbetal = HEX4;

0382Construct matrices for norm l basis */ for ⁽ i = 0/ bp = *Bp; i &lt; N32/' i+*-- bp + τ )

0383*bp = *Cbeta1 + i ); ιnult2 ⁽betal/ betal/ * D P ) ; for ⁽ i = 1 ; i < N; !+^■«- ? mult2 ⁽BPC i-13^ BPC i-l },- BPCΪ 3); ιαult2 (BPC03/ BP£ i D - DPCi }); > for ⁽ i = 0; i < N i + + ) < for (j = o; j C N32,~ j++ )

0384BΓC i 3C j i = o;

0385BIC i 3C-i/U0RD D = HEX8 >> C i 7. WORD >; > /« Gaussian elimination section . */ ior ( i = 0; ! < N; i + + ⁾ < if C(_*(8PC i 3 + i / WOR0 ) << i WORD & HEXS ⁾

0386== 0 ) for ( j = i + 1 ; j &lt; ; j ++ ⁾ if ( *(BPCj 3 -r i / WORD ) &lt;&lt; i % WORD S HEXδ) &lt; <img file="WO8804805A1_D0019.tif" /> 8PC j 3 ~ swap; swap = BIC i -i; BIC i 3 = BIC j 3; <img file="WO8804805A1_D0020.tif" /> reak;

0387if (( *(BP i 3 + i / WORD ) &lt;&lt; i '/. WORD &amp; HEX8) == 0 ⁾ &lt; ρrintf(" Error - Matrix is not invertible! \n" ⁾; goto next;

0388for ( j = i T 1 ; j &lt; N; j + + ) i f ( *(BP j + i / UORD J &lt;&lt; i '/. WORD &amp; HEX8 ) &lt; for (K = i / WϋKP; k -T N32; ktt)

0389*( BPC j 3 + k ) ^Λ= *( BPC i 3 + ; for ( k - O; k &lt; N32; k ++ )

0390^•*C βXC j 3 t k) ^Λ~_*(0lC i 3 t k);

0391for ( i = 0; i < N; i + 1 ) for (j = i - 1 ; j >= α; j-- ) i f ^{( «(} BPC j 3 + i / WORD ) << i / '.

0392WORD &amp; HEX5) &lt; for ⁽k = i / WORD; k &lt; N32; k++ )

0393*⁽BP j + k) ^Λ= _*(BPCi + k ); for ( k = O; k &lt; N32; k++ )

0394*⁽ B1C j 3 + k ) ^Λ= _*( B IC i 3 + k ); > * Perform matrix transpose x_/ for ⁽ i = 0/ bi = Bi; i < ; i+t, b11+ ) for ⁽ j = 0, b2 = Bi; j < i; j++, b2++ ) { temp = ^{( (} *b 1 ⁾C j /WORD 3 << ( j % WORD )) & HEXβ; <img file="WO8804805A1_D0021.tif" /> teβp2 = ^{( (} *b2 )C i /WORD 3 << ( i % UORD )) & HEXβ te*p2 >>- j V. ORD;

0395⁽ *bl ⁾C j /WOR03 = ( ( *b1 )C j/WORD 3 S. "(HEXS >> j XWORO ) ) ! temp2; ( «b2 )C i /WORD 3 = ( ( *b2 )C i /WORD 3 & ~⁽HEXfi >>

0396> txwoRon : temp; printf("\n Product digi t dO mult iply \n" >; pr.ntfC" equation coeff icients \π\n" ⁾; print (" b c \nW ; priπtf ("\n Y. ύ ,7.Ad \n" r N-1/ N-1 ⁾; Compute..and print out / c coeff icients */ for ( i = 0/ b1 = OP; i < N; 1++ b1++ ⁾ < for ( j = 0/ b2 = Bi; j < I; j++/ b2r+ ^{) {} out = O_f^* for, ( k = 0- b3 = »b1/> b = *b2; k <

0397<img file="WO8804805A1_D0022.tif" /> ou t 1 = 0; op (k = u; ■ WORD; k-H-/ out >>= 1 ) out 1 ^Λ= out & i; i f ( out 1 ) t 1 = ( N - j ) 7. N; 12 = ( N + i - . j ) 7. N; printf ( " 7. ά 7. d \n" , r t2 ; printf ⁽" . mK V.^ά \n" , t2, t 1 );

0398> > > next: ; >

0399/^■ Element mult iply subrout ine */ <img file="WO8804805A1_D0023.tif" /> uns igned *&amp;r *b/ *c; i register int I ; register Int J ; register uns igned « e; uns igned ECMAXN323; uns i gned FCf1AXN323; unsiαned feed; for ( i = 0, e = E i &lt; N32; 1++/ e++, «&lt;-+, b++, c++ ) &lt;

0400*e = * b;

0401*( F + i ) = *a;

0402«c = o; > for ( i = o; i < N; i ++ ) < i f (*(F + i/WORD ) 1C I 7. WOR0 & HEX8) for ( J - Q, c -= N32, e = E j < N32; j+t, c++/ e ++ ) * c ^Λ= *e; feed = *⁽e = E + (N-1 )/ WORD ) << (CN - 1 ) 7. WORD )

0403& HEXβ; for ⁽ j = N32 - 1; j > 0; J --, β-- )

0404*e = ⁽C*e >> 1 ⁾!(C«(e-1 ) & ONE) <C W0RD-1 ))^Λ( feed ? polyC j 3:0 ); *e = <*_β >> 1 ) ( _{feed ?} *_pol . _{Q );}