Integrable hall element

p0001The invention relates to an integratable Hall element according to the preamble of claim 1.

p0002Such Hall elements are with advantage in electricity meters or power meters used for measuring a magnetic field generated by an electric current.

p0003An integrated Hall element of the initially mentioned type is known for example from EP 0148330 A2. This Hall element, hereinafter briefly called vertical Hall element, measuring a magnetic field which is parallel to its surface effectively.

p0004From US-PS 4,253,107 a further integrated Hall element of the initially mentioned type is known, which measures a magnetic field which is perpendicular to its surface effect, and therefore, hereinafter briefly called horizontal Hall element.

p0005EP 0035103 Al describes an arrangement for compensation of piezoelectric effects, consisting of two complete Hall elements that rotated against each other by an angle of 90 degrees about an axis perpendicular to the surface are disposed. The two-pole current inputs and sensor outputs of the two Hall elements are connected in parallel.

p0006The invention is based on the object, despite the presence of very thin semiconductor layers to realize an integratable, arbitrarily large Hall element with low non-linearity and a small 1 / f noise. Here, the effective length of a vertical Hall element is significantly greater than the thickness of the semiconductor layer.

p0007This object is inventively achieved by the features indicated in characteristics of claim 1.

p0008Embodiments of the invention are illustrated in the drawing and werdem described in more detail below.

p0009Show it:<ul><li>Fig. 1 is a schematic representation of a multi-split Hall element, </li><li>FIG. 2a is a schematic representation of a multi-split vertical Hall element,</li><li>FIG. 2b shows a cross section of a multi-split integrated vertical Hall element,</li><li>Fig. 3 is a schematic representation of a two-split vertical Hall element in sum circuit,</li><li>Fig. 4 is a schematic representation of a two-split vertical Hall element in a differential circuit,</li><li>Fig. 5 shows a further variant of a two-split vertical Hall element in sum circuit,</li><li>Fig. 6 is a doubly split integrated vertical Hall element,</li><li>Fig. 7 shows a cross section of a two-part split integrated horizontal Hall element,</li><li>Fig. 8 is a plan view of the two-part split integrated horizontal Hall element,</li><li>Fig. 9a shows an electrical equivalent diagram of a known Hall element and</li><li>Fig. 9b is an electrical equivalent circuit diagram of the illustrated in the figures 7 and 8 horizontal Hall element.</li></ul>

p0010Like reference numerals designate in all figures of the drawing, identical parts.

p0011The illustrated in Fig. 1, multiple split Hall element consists of a known Hall element in the form of a rectangular parallelepiped made of semiconductor material, which has two electric connections C₁ and C₂ and two sensor terminals S₁ and S₂, which are respectively disposed on two opposite sides of the parallelepiped, whose remaining two parallel sides perpendicular to a magnetic field to be measured <o>H</o> are arranged. This known Hall element is divided at least by a sectional area in a plurality of arrangements, wherein the centers of terminal contacts of the sensor terminals S₁ and S₂ are both together in a common sectional area. The cut surfaces do not need plan-parallel, to be perpendicular to the current density in the Hall element still flat and. In the drawing, was adopted for reasons of graphic simplicity that all cut surfaces are arranged plane-parallel and perpendicular to the current density, that is perpendicular to the line connecting the two centers of the terminals of the two power connectors C₁ and C₂.

p0012In Figures 1, 2a and 2b has been assumed that three cut surfaces and thus four assemblies 1, 2, 3 and 4 are available. In the Figures 3 to 8 the assumption is that only one cut surface, and thus two arrays 2 and 3 are available. Any two points on both sides of each sectional area are connected to a mentally assumed to be elastic and electrically conductive wire. There are theoretically an infinite number of such points and such wires. The points are as all nearly in a straight line. In FIG. 1 and in Figures 3 to 5, the presence of seven compounds a to g per sectional area was, in the Figure 2a of five compounds A to E per sectional area in the Figure 2b of three compounds a to c per sectional area and in the figures 6 to 8 adopted by four compounds A to D per sectional area. It must be present per sectional area in any case at least two of such compounds a and b. be as the two equipotential points, which shall include at least, voted in the average sectional area those two points that have the same electric potential as the sensor terminals S₁ and S₂ with advantage. D. H .: Each of the two Aeus sera equipotential points of the average sectional area is in each case with one of the two sensor circuits S₁ and S₂ to be connected in such a way that it assumes its electrical potential.

p0013Thus, at least two of a plurality of points of each upper and each lower surface of each arrangement 1 to 4 connected to one of the oppositely Aequipotentialpunkt designated surface of an adjacent assembly.

p0014In physical segregation of the four arrangements 1 to 4 by parallel shifting the compounds assumed to be elastically are indeed longer, however, the Hall element illustrated in FIG. 1 operates thanks to the compounds and despite the spatial separation of the arrangement 1 to 4 the same way as if no cutting surfaces were present, since the compounds equipotential points together. In FIG. 1 are located between the assemblies 1 and 2, the seven compounds a1 to g1, between the assemblies 2 and 3, the seven compounds a2 to g2 and between the arrays 3 and 4, the seven compounds a3 to g3.

p0015The selected as equipotential points of points of the outer surfaces of the two outer arrangements 1 and 4 are electrically connected with each other and with the said surface respectively assigned power supply C₁ or C₂, that is, the seven compounds a0 to g0 at the, in the representation of the drawing, upper surface of the upper assembly 1 are all a4 all connected to the first current terminal and those C₁ to G4 on the lower surface of the lower arrangement 4 with the second current terminal C₂.

p0016A supply current I flows in operation through the first current terminal C₁ and the parallel connections a0 to g0 in the arrangement 1 and thus in the Hall element into it. The supply current I flows in the indicated order on through the assembly 1, via the parallel connections a1 to g1, through the arrangement 2, via the parallel connections a2 to g2, by the arrangement 3, via the parallel connections a3 to g3, by the arrangement 4 and out through the parallel connections a4 to g4 to the second current terminal C₂ and thus out of the Hall element. The through this feed stream I and the measured magnetic field<o>H</o> Hall voltage generated in the Hall element appears between the two sensor terminals S₁ and S₂. It remains to point daruf that any arrangement 1 to 4 taken alone is not a complete Hall element.

p0017The arrangements 1 to 4 can arbitrarily apart and even turned against each other, under the condition that in use the vector directions of the magnetic field <o>H</o>, The current density in the Hall element and the electrical Hall field in the Hall element maintaining their relative position (see Fig. 2a, Fig. 3 and Fig. 5).

p0018are in the Fig. 2a the arrangements 1 to 4 are arranged approximately in a straight line next to each other, whereby the arrangements 1 to 4 alternately not twisted (arrays 1 and 3) or upside down twisted (arrangements 2 and 4) parallel shifted arranged such that at least the upper surfaces of the arrangements 1 to 4, finally, all lie in a single common plane. All connections are parallel untereinander.Die relative position of the three mentioned vectorial directions has remained unchanged with respect to its original position. The connections a0 to e0, a2 to e2 and a4 to e4 are all above and the compounds a1 to e1 and a3 to e3 all located below the arrangements 1 to 4. FIG.

p0019The illustrated in Fig. 2b integrated vertical Hall element represents a practical realization of the FIG. 2a shown schematic arrangement. The common plane in which lie the upper surfaces of the arrangements 1 to 4, is the surface plane of a semiconductor layer 5, in which together all the arrangements 1 to 4 are arranged. The semiconductor layer 5 is z. B. a thin epitaxial layer is grown on a substrate 6. In Fig. 2b, only the three arrays 2 to 4 are simply half shown. Set in the representation of the drawing below the arrangements 1 to 4 compounds a1 to c1 and a3 through c3, ie part of the connections between equipotential points, each consisting of a buried layer ( "buried layer"), each in the boundary layer erected between the substrate 6 and the semiconductor layer. 5 The systems 1 and 2 each have as buried layers, the compounds A1 to C1, which are shown in FIG. 2b for the arrangement 2, and the arrangements 3 and 4 each as buried layers, the compounds a3 to c3. In the in Fig. 2b illustrated cross-section of each buried layer located on the surface in the semiconductor layer 5 compared with a respective contact diffusion. These are shown in Fig. 2b refers to the arrangement 2 with 7 to 9, for the assembly 3 with 10 to 12 and for the arrangement 4 with 13 to 15. The other part of the compounds, ie the points of view of the drawing above the arrangements 1 to 4 connections a0 to c0 (not shown in Fig. 2b, since only in the arrangement 1 is not shown yet), a2 to c2 and a4 c4, ever make electrical contact with one of the contact diffusions. These compounds make up the so-called metallization of the integrated circuit and are applied to the surface of the semiconductor layer 5th The metallization is composed of metal, eg aluminum, or from electrically conductive polysilicon. Purpose electrical insulation is located between the metallization and the semiconductor layer 5, an insulating layer 19, for example, consists of SiO₂. Metallization is right on this insulating layer 19, which in turn rests directly on the semiconductor layer. 5 The compounds a4 to c4 of the arrangement 4 are interconnected in order to connect to their common electricity C₂. Each array is 1 to 4 for the purpose of island formation and isolation surrounded laterally from the adjacent arrays with as rectangular insulation ring, two adjacent insulation rings each have a common web 16; have 17 or 18th The isolation ring 16; 17 surrounds eg the assembly 2 and the isolation ring 17;. 18 as the assembly 3. The insulation rings range from the surface of the semiconductor layer 5 to deep down, for example by spatial contact with the substrate 6.

p0020The substrate 6, the isolation rings and their webs 16, 17 and 18 are all made of a semiconductor material of one same material conductivity type, for example of P-material. It could also be N-material. The semiconductor layer 5, the buried layers and the contact diffusions 7 to 15 are all made of a semiconductor material from the other Materialleifähigkeitstyp, so in the example of N-material. The buried layers and the contact diffusions 7 to 15 are all heavily doped with impurity atoms, ie they consist of N + material.

p0021The illustrated in Fig. 3 is a schematic arrangement similar to that in the FIG. 2 arrangement shown, with the advantage that only two assemblies 2 and 3 are available, which results in that the connections to the two current terminals C₁ and C₂ at the lower surfaces of the assemblies 2 and 3 are not, as. shown in Fig. 2a, on the upper surfaces of the arrangements 1 and 4

p0022The illustrated in FIG. 4 schematic arrangement corresponds to the arrangement shown in Fig. 3, with the difference that the compounds at the surface of the assemblies 2 and 3 extending no longer parallel but diagonally. Although this is in line the relative position of the three mentioned vectorial directions to the original location, but not the sense of direction of the vextoriellen directions the magnetic field has namely its relative position at the place of assembly 3 practically rotated 180 °. D. h. That the Hall element shown in FIG. 4 is not more like the Hall element shown in FIG. 3, the sum<o>H1</o>+<o>H2</o>But the difference <o>H1</o>-<o>H2</o> two magnetic fields <o>H1</o> and <o>H2</o> measures which <o>H1</o> the magnetic field at the location of the assembly 2 and <o>H2</o> the magnetic field at the location of the assembly 3 is. In other words, with the Hall element shown in FIG 4, a magnetic field gradient between two spatially separated points can be measured.

p0023The Hall element shown schematically in FIG. 5 corresponds approximately to that which is shown in Fig. 3, with the difference that both arrangements 2 and 3 are not arranged approximately in a row next to each other but nearly in a row behind each other. The representation in the drawing upper connections are made, however, on the cross, this time to leave it to the relative position of the three vectorial directions.

p0024In FIG. 6, the practical realization is shown in the FIG. 3, the Hall element shown schematically as an integrated circuit, in turn, creates a vertical Hall element. The Hall element shown is approximately equal in Fig. 2b shown integrated vertical Hall element with the difference that this time only two arrangements 2 and 3 are available.

p0025The to be connected to a power supply C₁ or C₂ points on the lower surfaces of the two outer arrangements now 2 and 3 time each form a single common buried layer a1; b1; c1; d1 and a3 b3 c3 d3 per arrangement 2 or 3, the. by a respective deep diffusion 20 or 21 by the semiconductor layer 5 passes full, with the surface of the Hall element, ie the integrated circuit is connected The deep diffusion 20 and 21 respectively is connected there to a power connection C₁ or C₂ of the Hall element. The deep diffusions 20 and 21 are made of material that is of the same material conductivity type as the buried layers and the like this is heavily doped with impurity atoms, ie they consist of N + material.

p0026Realized according to Figures 2b and 6 integrated vertical Hall elements have the advantage, in contrast to the known vertical Hall element whose both power connectors C₁ and C₂ are structured very differently and have very different dimensions, have exactly symmetric properties in both current directions to.

p0027To ensure the long term stability of 6, the surface of the semiconductor layer 5 in Fig. Covered with a thin surface layer 22 made of the same material P as the substrate 6. All contact diffusions 7 to 12, all the webs 16 to 18 and the two deep diffusions 20 and 21 pass through fully this thin surface layer 22. the illustrated in Fig. 2b vertical Hall element has with advantage as such a thin surface layer 22, which is however not shown in Fig. 2b.

p0028Both Figures 7 and 8 illustrate the cross-section VII and the plan view of same horizontal Hall element. It also consists of two assemblies 2 and 3, but not next to each other in a row, but against each other in plan view by an angle of approximately 90 ° twisted, that is rotated by an angle of zunähernd 90 ° about a perpendicular axis to the surface, are arranged in the semiconductor layer 5th The spatial arrangement and the material of the substrate 6, of the semiconductor layer 5, the surface layer 22, the insulating layer 19, the metallization and the webs 16, 17 and 18 of insulating rings, which are designated in Fig. 8 by 23 and 24, are the same as shown in Fig. 6. All of the compounds a1 to d1, a2 to d3 are as metallization on the surface of the integrated circuit to d2 and a3. Thus, there are no time buried layers. These have been replaced by contact diffusions 25 to 32, wherein the contact diffusions 25 to 28 on the one hand and the contact diffusions are 29 to 32 on the other hand advantageously arranged approximately in a straight row. The contact diffusions 25 to 32 are all made of the same material as the N⁺-contact diffusions 7 to 12. The lines connecting the centers of the two contact diffusion rows 25; 26; 27; 28 and 29; 30; 31; 32 form approximately a 90 ° angle to each other. Each assembly 2 and 3 has two contact diffusion rows 25; 26; 27; 28 and 7, 8, 9 or 10; 11; 12 and 29; 30; 31; 32, wherein a respective contact diffusion of a number of a contact diffusion of the other series of the surface in the semiconductor layer 5 is opposite. In each of the two contact diffusion rows 7, 8, 9 and 10; 11; 12 an unnumbered contact diffusion is shown in FIG 8 drawn, 26 and 31, respectively opposite to the contact diffusion.. The contact diffusions 7 to 9 on the one hand and 10-12 on the other hand are also approximately advantageously arranged in a respective straight line, which is preferably in parallel to the contact diffusion row 25; 26; 27; 28 or 29; 30; 31; 32nd The compounds A2 to D2 connect the contact diffusions 7-9 electrically connected to the contact diffusions 10 to 12, wherein the compounds a2 and d2 each have a sensor terminal S₁ or S₂. The first current terminal of the Hall element C₁ is connected via the connections A1 to D1 with the contact diffusions 25 to 28, the four array all belong to the second The second current terminal of the Hall element C₂ is connected via the connections a3 to d3 with the contact diffusions 29 to 32, which includes all four for the arrangement 3rd

p0029The illustrated in Figures 7-8 horizontal Hall element has the advantage that its zero-voltage ( "offset" voltage) is largely compensated, which will be explained in detail with reference to figures 9a and 9b.

p0030FIG. 9A illustrates a four resistors bridge circuit, which is the equivalent circuit diagram of a conventional Hall element. The bridge circuit includes two different resistance values ​​R and R + .DELTA.R, wherein two spatially arranged parallel resistors, that is, two in the bridge circuit diametrically opposed resistors are equal. The resistance difference .DELTA.R is created by piezoresistive effects, geometric tolerances, etc. In a magnetic field<o>H</o>S₂ of the Hall element, a zero voltage V = 0, is produced at the sensor output S₁_off= (.DELTA.R / R) V_{C1, C2}, Where V_{C1, C2} represents C₂ of the Hall element pending supply voltage; a the feed stream input C₁.

p0031In FIG. 9B, the equivalent circuit of the shown in the figures 7-8 horizontal Hall element is shown, which differs from that in Fig. 9a depicted equivalent circuit diagram of the fact that one half of the bridge circuit rotated by 90 ° relative to the other half is disposed. Since two spatially arranged parallel resistors is R or R + .DELTA.R are back, this time are, viewed in flow direction of the supply current I, two identical resistors electrically connected in series, which results in that V_off = 0.

p0032The nullification of the zero voltage V_off may be in the vertical Hall element (see Fig. 3) are realized in that the Kurzschlussverbindun gene a2 and b2 are each replaced by two series-connected, not shown, resistors, whose common terminal is connected with one of the sensor terminals S₁ or S₂. These resistors can be realized as adjustable balancing resistors. They consist, for example, preferably of one junction field effect transistor (JFET) or a MOS field-effect transistor whose source to drain channel resistance is in each case the resistor whose resistance value is adjustable by means of the gate voltage of the field effect transistor.

p0033All integrated Hall elements described can be prepared in standard bipolar integrated circuit technology. Thanks to the use of multiple split Hall elements may, despite the presence of a thin epitaxial layer as the semiconductor layer 5, any large Hall elements can be realized. This has the advantage that the non-linearity of the Hall element is low and its 1 / f noise is small.