Integrable Hall element.

0001The invention relates to an integrable Hall element according to the preamble of claim 1.

0002Hall elements of this type are advantageously used in electricity meters or power meters for measuring a magnetic field generated by an electrical current.

0003An integrated Hall element of the type mentioned at the outset is known, for example, from EP 0 148 330 A2. This Hall element, hereinafter referred to as vertical Hall element for short, measures a magnetic field which is effective parallel to its surface.

0004From US Pat. No. 4,253,107, another integrated Hall element of the type mentioned at the outset is known, which measures a magnetic field which is effective perpendicular to its surface and is therefore referred to below as a horizontal semiconductor element.

0005The invention is based on the object of realizing an integrable, arbitrarily large Hall element with low non-linearity and low 1 / f noise despite the presence of very thin semiconductor layers. The effective length of a vertical Hall element is significantly greater than the thickness of the semiconductor layer.

0006According to the invention, the stated object is achieved by the features specified in the characterizing part of claim 1.

0007Embodiments of the invention are shown in the drawing and will be described in more detail below.

0008Show it:<ul id="ul0001" list-style="none"><li>1 is a schematic representation of a multi-divided Hall element,</li><li>2a is a schematic representation of a multiple divided vertical Hall element,</li><li>2b shows a cross section of a multiply divided integrated vertical Hall element,</li><li>3 shows a schematic illustration of a double-divided vertical Hall element in a summation circuit,</li><li>4 shows a schematic representation of a double-divided vertical Hall element in a differential circuit,</li><li>5 shows a further variant of a double divided vertical Hall element in a summation circuit,</li><li>6 shows a two-part integrated vertical holding element,</li><li>7 shows a cross section of a two-part integrated horizontal Hall element,</li><li>8 is a plan view of the two-part integrated horizontal Hall element,</li><li>Fig. 9a is an electrical equivalent image of a known Hall element and</li><li>9b is an electrical equivalent circuit diagram of the horizontal Hall element shown in FIGS. 7 and 8.</li></ul>

0009The same reference numerals designate the same parts in all figures of the drawing.

0010The multi-divided Hall element shown in FIG. 1 consists of a known Hall element in the form of a right-angled parallelepiped made of semiconductor material, which has two current connections C and C₂ as well as two sensor connections S, and S₂ has, which are each arranged on two opposite sides of the parallelepiped, the remaining two parallel sides of which are arranged perpendicular to a magnetic field H to be measured. This known Hall element is divided into several arrangements by at least one cut surface, the centers of the connection contacts of the sensor connections S. and S2 both lying together in a common cut surface. The cut surfaces need not be plane-parallel, nor flat and perpendicular to the current density in the Hall element. For the sake of simplicity of the drawing, it was assumed in the drawing that all of the cut surfaces are arranged plane-parallel and perpendicular to the current density, ie perpendicular to the connecting line of the two centers of the connection contacts of the two current connections C, and C._e.g. lie.

0011In FIGS. 1, 2a and 2b it was assumed that there are three cut surfaces and thus four arrangements 1, 2, 3 and 4. In FIGS. 3 to 8, the assumption applies that there is only one cutting surface and therefore two arrangements 2 and 3. Two points on each side of each cut surface are connected with a wire that is thought to be elastic and is electrically conductive. There are theoretically an infinite number of such points and such wires. The points are, for example all approximately in a straight line. In Fig. 1 and in Figures 3 to 5, the presence of seven connections a to g per cut surface, in Figure 2a of five connections a to e per cut surface, in Figure 2b of three connections a to c per sectional area and in FIGS. 6 to 8 of four connections a to d per sectional area. In any case, there must be at least two such connections a and b per cut surface. Advantageously, the two equipotential points that must at least be present are those two points in the middle sectional area that have the same electrical potential as the sensor connections S and S₂. That means: Each of the two outer equipotential points of the middle cut surface is in each case with one of the two sensor connections S, and S₂ to connect in such a way that it assumes its electrical potential.

0012Thus, at least two of a plurality of points of each upper and each lower surface of each arrangement 1 to 4 are each connected to an equipotential point of the oppositely named surface of an adjacent arrangement.

0013When the four arrangements 1 to 4 are spatially separated by parallel displacement, the connections assumed to be elastic become longer, but the Hall element shown in FIG. 1 works exactly as if there were no cut surface, thanks to the connections and despite the spatial separation of the arrangements 1 to 4 would exist since the connections connect equipotential points with each other. In the Fig. 1 are the eight connections a1 to g1 between the arrangements 1 and 2, the eight connections a2 to g2 between the arrangements 2 and 3 and the eight connections a3 to g3 between the arrangements 3 and 4.

0014The points of the outer surfaces of the two outer arrangements 1 and 4 selected as equipotential points are in each case one below the other and with the power connection C or C respectively assigned to this surface₂ electrically connected, ie the eight connections a0 to g0 on the, in the illustration of the drawing, upper surface of the upper arrangement 1 are all connected to the first power connection C, and those a4 to g4 on the lower surface of the lower arrangement 4 are all connected to the second Power connection C₂ connected.

0015A feed current I flows through the first power connection C, and the parallel connections a0 to g0 into the arrangement 1 and thus into the Hall element. The feed current I flows in the order given through arrangement 1, via parallel connections a1 to g1, through arrangement 2, via parallel connections a2 to g2, through arrangement 3, via parallel connections a3 to g3, through Arrangement 4 and via the parallel connections a4 to g4 to the second power connection C₂ and thus out of the Hall element. The through this feed current I and the magnetic field to be measured<img file="EP0244577A1_D0001.tif" /> Hall voltage generated in the Hall element appears between the two sensor connections S, and S ,. It remains to be pointed out that each arrangement 1 to 4 does not represent a complete Hall element on its own.

0016The arrangements 1 to 4 can be spaced apart from one another and even rotated relative to one another, on the condition that the vectorial directions of the magnetic field H, the current density in the Hall element and the electrical Hall field in the Hall element maintain their relative position (see FIGS. 2a, 3 and Fig. 5).

0017In Fig. 2a, the arrangements 1 to 4 are arranged approximately in a straight row next to each other, the arrangements 1 to 4 alternately not twisted (arrangements 1 and 3) or turned upside down (arrangements 2 and 4) are arranged in parallel such that at least the upper surfaces of the arrangements 1 to 4 finally all lie in a single common plane. All connections are parallel to each other; the relative position of the three vectorial directions mentioned has remained unchanged in relation to their original position. The connections a0 to e0, a2 to e2 and a4 to e4 are all arranged above and the connections a1 to e1 and a3 to e3 are all arranged below the arrangements 1 to 4.

0018The integrated vertical Hall element shown in FIG. 2b represents a practical implementation of the schematic arrangement shown in FIG. 2a. The common plane in which the upper surfaces of the arrangements 1 to 4 lie is the surface plane of a semiconductor layer 5 in which all arrangements 1 to 4 are arranged together. The semiconductor layer 5 is, for. B. a thin epitaxial layer that has grown on a substrate 6. In the Fig. 2b only the three arrangements 2 to 4 are shown for the sake of simplicity. The connections a1 to c1 and a3 to c3 located below the arrangements 1 to 4 in the illustration of the drawing, ie part of the connections between equipotential points, each consist of a buried layer, each in the boundary layer are arranged between substrate 6 and semiconductor layer 5. Arrangements 1 and 2 each have connections a1 to c1 as buried layers, which are only shown for arrangement 2 in FIG. 2b, and arrangements 3 and 4 each have connections a3 to c3 as buried layers. In the cross section shown in FIG. 2b, each buried layer on the surface in the semiconductor layer 5 is opposite a contact diffusion. These are shown in Fig. 2b for the arrangement 2 with 7 to 9, for the arrangement 3 with 10 to 12 and for the arrangement 4 with 13 to 15. The other part of the connections, ie the connections a0 to c0 located above the arrangements 1 to 4 in the representation of the drawing (not shown in FIG. 2b, since only present in the arrangement 1 not shown), a2 to c2 and a4 to c4, has electrical contact with one of the contact diffusions. These connections together form the so-called metallization of the integrated circuit and are applied to the surface of the semiconductor layer 5. The metallization consists of metal, for example aluminum, or of electrically conductive polysilicon. For the purpose of electrical insulation, there is an insulation layer 19, which is made of SiO, for example, between the metallization and the semiconductor layer 5₂ consists. The metallization lies directly on this insulation layer 19, which in turn rests directly on the semiconductor layer 5. The connections a4 to c4 of the arrangement 4 are interconnected for the purpose of connection to their common power connection C2. Each arrangement 1 to 4 is for the purpose of island formation and isolation from the neighboring arrangements with an example Rectangular insulation ring surrounded laterally, two adjacent insulation rings each having a common web 16, 17 or 18. The insulation ring 16; 17 surrounds z. B. the arrangement 2 and the insulation ring 17; 18, for example the arrangement 3. The insulation rings extend from the surface of the semiconductor layer 5 down deep, for example to spatial contact with the substrate 6.

0019The substrate 6, the insulation rings and their webs 16, 17 and 18 all consist of a semiconductor material of the same material conductivity type, for example of P material. It could of course also be N-matter. The semiconductor layer 5, the buried layers and the contact diffusions 7 to 15 all consist of a semiconductor material of the other material conductivity type, that is to say in the example of N material. The buried layers and the contact diffusions 7 to 15 are all heavily doped with foreign atoms, ie they consist of N.^+-Material.

0020The schematic arrangement shown in FIG. 3 is similar to the arrangement shown in FIG. 2a, with the advantage that only two arrangements 2 and 3 are left, which leads to the connections to the two power connections C, and C.₂ are on the lower surfaces of the arrangements 2 and 3 and not, as in FIG. 2a, on the upper surfaces of the arrangements 1 and 4.

0021The schematic arrangement shown in FIG. 4 corresponds to the arrangement shown in FIG. 3, with the difference that the connections on the surface of the arrangements 2 and 3 no longer run parallel, but crosswise. As a result, the relative position of the three vector directions mentioned no longer corresponds to the original position. The magnetic field has practically rotated its relative position at the location of the arrangement 3 by 180 °. That is, that in Fig. 4th Hall element shown no longer like the Hall element shown in FIG. 3 the sum <o ostyle="rightarrow">H1</o> + <o ostyle="rightarrow">H2</o>but the difference <o ostyle="rightarrow">H1</o><o ostyle="rightarrow">H2</o> two magnetic fields <o ostyle="rightarrow">H1</o> and <o>H2</o> measures where <o ostyle="rightarrow">H1</o> Magnetic field at the location of arrangement 2 and <o ostyle="rightarrow">H2</o>. the magnetic field is at the location of the arrangement 3. In other words: with the Hall element shown in FIG. 4, a magnetic field gradient between two spatially distant points can be measured.

0022The Hall element shown schematically in FIG. 5 corresponds approximately to that shown in FIG. 3, with the difference that the two arrangements 2 and 3 are not arranged approximately in a row next to one another, but rather approximately in a row one behind the other. The connections at the top in the illustration of the drawing, however, run crosswise, this time in order to leave the relative position of the three vector directions unchanged.

0023FIG. 6 shows the practical implementation of the Hall element shown schematically in FIG. 3 as an integrated circuit, again producing a vertical Hall element. The Hall element shown corresponds approximately to the integrated vertical Hall element shown in FIG. 2b with the difference that this time only two arrangements 2 and 3 are present.

0024The one with a power connection C or C₂ Points to be connected on the lower surfaces of the two outer arrangements 2 and 3 now form a single common buried layer a1; b1; c1; d1 or a3; b3; c3; d3 per arrangement 2 and 3, which each have a deep diffusion 20 or 21, which passes completely through the semiconductor layer 5, with the surface of the Hall element, ie the integrated circuit, and there with a respective current connection C.₁ or C₂ of the Hall element are connected. The deep diffusions 20 and 21 consist of material which is of the same material conductivity type as the buried layers and which is heavily doped with foreign atoms, ie they consist of N.⁺-Material.

0025The integrated vertical Hall elements realized according to FIGS. 2b and 6 have the advantage that, in contrast to the known vertical Hall element, whose two current connections C, and C₂ are constructed very differently and have very different dimensions, have exactly symmetrical properties in both current directions.

0026To ensure long-term stability, the surface of the semiconductor layer 5 in FIG. 6 is covered with a thin surface layer 22. which consists of the same material P as the substrate 6. All contact diffusions 7 to 12. all webs 16 to 18 and the two deep diffusions 20 and 21 fully cross this thin surface layer 22. The vertical Hall element shown in FIG. 2b advantageously also has such a thin surface layer 22, which, however, is not shown in FIG. 2b.

0027The two FIGS. 7 and 8 represent the cross section VII and the top view of the same horizontal Hall element. It also consists of two arrangements 2 and 3, which, however, are not in a row next to one another, but in plan view at an angle of approximately 90 ° to one another are arranged twisted in the semiconductor layer 5. The spatial arrangement and the material of the substrate 6, the semiconductor layer 5, the surface layer 22, the insulation layer 19, the metallization and the webs 16, 17 and 18 of the insulating rings, which are designated 23 and 24 in FIG. 8, are the same as in FIG. 6. All connections a1 to d1, a2 to d2 and a3 to d3 are located as metallization on the surface of the integrated circuit. So there are no buried layers this time. These have been replaced by contact diffusions 25 to 32, the contact diffusions 25 to 28 on the one hand and the contact diffusions 29 to 32 on the other hand advantageously being arranged approximately in a straight row. The contact diffusions 25 to 32 all consist of the same N.^+-Material like the contact diffusions 7 to 12. The connecting lines of the centers of the two contact diffusion rows 25; 26; 27; 28 and 29; 30; 31; 32 approximately form an angle of 90 ° with one another. Each arrangement 2 and 3 has two contact diffusion rows 25; 26; 27; 28 and 7; 8th; 9 or 10; 11; 12 and 29; 30; 31; 32, wherein in each case a contact diffusion of one row is opposite to a contact diffusion of the other row on the surface in the semiconductor layer 5. In each of the two contact diffusion series 7; 8th; 9 and 10; 11; 12, an unnumbered contact diffusion is drawn in FIG. 8, which lies opposite the contact diffusion 26 or 31. The contact diffusions 7 to 9 on the one hand and 10 to 12 on the other hand are likewise advantageously arranged approximately in a straight row, which is preferably in each case parallel to the contact diffusion row 25; 26; 27; 28 and 29; 30; 31; 32. The connections a2 to d2 electrically connect the contact diffusions 7 to 9 to the contact diffusions 10 to 12, the connections a2 and d2 each having a sensor connection S or S₂ have. The first current connection C, of ​​the Hall element is connected via the connections a1 to d1 to the contact diffusions 25 to 28, which all four belong to the arrangement 2. The second power connector C_e.g. of the Hall element is connected to the contact diffusions 29 to 32 via the connections a3 to d3. which all four belong to arrangement 3.

0028The horizontal Hall element shown in FIGS. 7 to 8 has the advantage that its zero voltage (“offset” voltage) is largely compensated for, which is explained in more detail below with reference to FIGS. 9a and 9b.

00299a shows a bridge circuit consisting of four resistors, which represents the equivalent circuit diagram of a conventional Hall element. The bridge circuit contains two different resistance values ​​R and R + AR, whereby two spatially parallel resistors, that is, two resistors diametrically opposite in the bridge circuit, are the same. The resistance difference AR arises from piezoresistive effects, geometric tolerances, etc. With a magnetic field<o ostyle="rightarrow">H</o>= 0, arises at sensor output S ,; S2 of the Hall element a zero voltage V_off= (AR / R) V _c1, _cε, where V_c1, _c2 one at the feed current input C ,; C2 represents the supply voltage applied to the Hall element.

0030FIG. 9b shows the equivalent circuit diagram of the horizontal hook element shown in FIGS. 7 to 8, which differs from the equivalent circuit diagram shown in FIG. 9a in that one half of the bridge circuit is arranged rotated by 90 ° with respect to the other half. Since two spatially parallel resistors are again equal to R or: R +_AR, this time, viewed in the direction of flow of the feed current I, there are two identical resistors in series, which leads to V_off⁼0 becomes.

0031The zero adjustment of the zero voltage Von can be realized in the vertical Hall element (see FIG. 3) by replacing the short-circuit connections a2 and b2 with two resistors (not shown) connected in series, the common pole of which is connected to one of the sensor connections S or . S₂ connected is. These resistors can be implemented as adjustable trimming resistors. For example, they preferably each consist of a junction field-effect transistor (JFET) or a MOS field-effect transistor, the source-drain channel resistance of which represents the resistance, the resistance value of which can be set by means of the gate voltage of the field-effect transistor.

0032All of the integrated Hall elements described can be produced using standard bipolar integrated circuit technology. Thanks to the use of multiple Hall elements, despite the presence of a thin epitaxial layer as the semiconductor layer 5, Hall elements of any size can be realized. This has the advantage. that the non-linearities of the Hall element are low and its 1ff noise is small.