Sense amplifier for programmable read only memory.

BACKGROUND OF THE INVENTION

1. Field of the Invention

0001The present invention relates to a sense amplifier for a programmable read only memory such as an erasable programmable read only memory (EPROM).

2. Description of the Related Art

0002In general, a conventional EPROM includes a sense amplifier having a p-channel load transistor, an n-channel drive transistor, a sense output terminal, a memory cell array having a plurality of memory cell transistors, and bit lines and word lines. When a field effect transistor having a stacked-gate structure is used as a memory cell of an EPROM, the transistor injects and stores hot electrons, generated by an avalanche breakdown occurring at the drain terminal, into a floating gate during a program operation, so that the changes in threshold voltage Vth of the transistor are utilized.

0003In the EPROM which uses the field effect transistor having a stacked-gate structure, since an electric charge is stored in the floating gate of the programmed, i.e., written, memory cell transistor as described above, it is difficult to pass a drain current, i.e., a cell current, therethrough. Therefore, when data is read in such a case, the potential of the sense output is HIGH level "1". Conversely, since an electric charge is not stored in the floating gate of the non-programmed memory cell transistor, it is easy to flow a cell current therethrough. Therefore, when data is read in such a case, the potential of the sense output is LOW level "0".

0004In order to program, i.e., write in, the EPROM which uses the field effect transistor having the stacked-gate structure, a power supply voltage V_pp for programming is applied to the memory. The power supply voltage V_pp for programming is, for example, 12 V, which is a higher value than a power supply voltage V_cc for reading (for example, 5 V). In this case, a voltage of about 10 V is applied between the drain and the source of the cell transistor, and a voltage of about 12 V is applied to a control gate electrode at the surface. Note that, during a verify read operation, the power supply voltage V_pp for programming is applied to the memory, and the power supply voltage V_cc for reading is applied to the memory cell transistor and other necessary sections by a suitable switch circuit, but during a regular read operation, only the power supply voltage V_cc for reading is applied to the memory.

0005In the above-mentioned EPROM, the completion of a write operation is verified by detecting whether the sense current exceeds the reference value. That is, the voltage V_pp for programming is applied to carry out the write operation as described above. The power supply voltage V_cc for reading is switched and applied to carry out the verify reading operation while the power supply voltage V_pp for programming is still applied. If a cell current exceeding the reference value does not flow in the memory cell transistor, the write operation is determined to be completed.

0006During the above verify reading, the power supply voltage V_pp for programming of, for example, 12 V, and the power supply voltage V_cc for reading of, for example, 5 V, are applied to the memory, and the power supply voltage V_cc for reading is applied to the memory cell transistor. Assuming that the power supply voltage V_cc for reading is, for example, 5 V, a voltage of 5 V is applied to the control gate electrode at the surface of the memory cell transistor, and a voltage of about 1 V is applied between the drain and the source.

0007The reference value of the cell current for carrying out a discrimination between "1" and "0" in the case of the verify reading is the same as that in the case of the regular reading.

0008In the case of programming the above EPROM, when the reference value of the cell current for discriminating whether the write operation is completed is set, for example, as 10 µA, the write operation is determined to be completed if the cell current is, for example, 9 µA, during the verify reading.

0009However, after long-term use of the memory, often the electric charges will leak from the floating gate of the memory cell transistor. As a result, the cell current increases by an amount of, for example, 1 µA.

0010Under such a condition, when the regular read operation is performed and a cell current of 10 µA flows, it is recognized that the potential of the sense output is LOW level "0", although the potential of the sense output should be recognized as being HIGH level "1". Hence, the discrimination between "1" and "0" in the regular reading becomes incorrect. Therefore, the operation of the EPROM can become defective.

SUMMARY OF THE INVENTION

0011It is an object of the present invention to provide an improved sense amplifier for a programmable read only memory, in which the margin of the voltage of the power source, which is the difference between the voltage for normal operation and that for defective operation of the device, is sufficiently ensured, so that HIGH and LOW levels of the potential of the sense output are correctly discriminated even if there is leakage of the electric charge injected in the floating gate.

0012In accordance with the present invention, there is provided a sense amplifier for a programmable read only memory having a sense current source circuit for supplying memory cells in the memory with currents, the sense current source circuit being adapted to supply memory cells with a cell current for both a regular reading and a verify reading. In this device, a reference value of the cell current for the regular reading is selected to be higher than a reference value of the cell current for the verify reading, whereby a sufficient value of margin of voltage of a power source for the memory is ensured.

BRIEF DESCRIPTION OF THE DRAWINGS

0013<ul id="ul0001" list-style="none"><li>In the drawings, Fig. 1 is a circuit diagram of the fundamental structure of a conventional sense amplifier of an EPROM;</li><li>Fig. 2 is a circuit diagram of the fundamental structure of an EPROM according to an embodiment of the present invention;</li><li>Fig. 3 is a detailed circuit diagram of the EPROM shown in Fig. 2;</li><li>Fig. 4 is a circuit diagram of an EPROM according to another embodiment of the present invention; and</li><li>Fig. 5 is a circuit diagram of an EPROM according to still another embodiment of the present invention.</li></ul>

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0014Before describing preferred embodiments of the present invention, a conventional sense amplifier of an EPROM will be described with reference to Fig. 1.

0015The device shown in Fig. 1 is provided with a sense amplifier 1, a p-channel load transistor 11, an n-channel drive transistor 13, a sense output terminal, a memory cell transistor 51, and a word line WL.

0016In Fig. 1, the memory cell transistor 51 is a so-called field effect transistor having a stacked-gate structure. During a write operation, the memory cell transistor 51 injects and stores hot electrons, generated by avalanche breakdown occurring at the drain terminal, to a floating gate, thereby utilizing changes in the threshold voltage Vth of the transistor 51.

0017In the EPROM shown in Fig. 1, since an electric charge is stored in the floating gate of the programmed, i.e., written, memory cell transistor 51, it is difficult for a drain current, i.e., a cell current to flow therethrough. Therefore, when data is read out in such a case, the potential of the sense output is HIGH level "1". Conversely, since an electric charge is not stored in the floating gate of the non-programmed memory cell transistor, it is easy for a cell current to flow therethrough. Therefore, when data is read in such a case, the potential of the sense output is LOW level "0".

0018In order to program, i.e., to write in, the EPROM which uses the field effect transistor having the stacked-gate structure, a power supply voltage V_pp for programming is applied to the memory. The power supply voltage V_pp for programming is, for example, 12 V, which is a higher value than a power supply voltage V_cc for reading of, for example, 5 V. In this case, a voltage of about 10 V is applied between the drain and the source of the cell transistor, and a voltage of about 12 V is applied to a control gate electrode at the surface. Note that, during program verification, the power supply voltage V_pp for programming is applied to the memory, and the power supply voltage V_cc for reading is applied to the memory cell transistor and other necessary sections by a suitable switch circuit. In addition, during a regular read operation, only the power supply voltage V_cc for reading is applied to the memory.

0019A sense amplifier for an EPROM as a preferred embodiment of the present invention will now be described with reference to Figs. 2 and 3. The fundamental structure is shown in Fig. 2, and a detailed circuit diagram is shown in Fig. 3.

0020In a device shown in Figs. 2 and 3, a transistor 12, which is a p-channel type as for the transistor 11, is connected, as an additional load transistor, in parallel with the transistor 11.

0021The load transistor 12 is OFF during the verify reading and is ON during a regular read operation.

0022Therefore, if the load transistors 11 and 12 have the same ability, a load current drive ability during the regular read operation is twice that for the verify read operation.

0023In general, whether the sense output is "1" or "0" depends on the ratio between the current drive ability in the load side and that in the memory cell side, i.e., depends on which of these current drive abilities is higher.

0024More specifically, when the load current drive ability is higher than the memory cell current drive ability, sufficient current cannot flow from the load side to the memory cell side, so that the potential of the sense output is HIGH level. In the reverse case, the potential of the sense output is LOW level.

0025Therefore, during the verify reading operation, only the load transistor 11 is turned ON to reduce the current drive ability and thus reduce the sense current. Whether the write operation is completed is discriminated by setting a reference value of, for example, 10 µA, as described above. During the regular reading, the load transistor 12, in addition to the load transistor 11, is turned ON to increase the current drive ability and thus increase the sense current, thereby discriminating whether the value is "1" or "0" by setting a reference value of, for example, 20 µA.

0026In this manner, even if there is a slight leakage of the electric charge stored in the memory cell transistor 51, correct "1" or "0" data is obtained as the sense output.

0027Figure 3 shows a verify reading / regular reading discrimination signal S(V_ppDET), a bus line 2, a power supply voltage V_pp for a V_pp detection circuit 6, a program circuit 4, a column gate 3, column selection signal lines, a memory cell array 5, word lines, and bit lines.

0028In the regular reading, the voltage V_cc of 5 volts is applied to the V_pp terminal of the V_pp detection circuit 6 so that the voltage of the S(V_ppDET) is 0 volt. In the verify reading, the voltage V_pp of 12 volt is applied to the V_pp terminal of the V_pp detection circuit 6 so that the voltage of the S(V_ppDET) is equal to V_cc.

0029In Fig. 3, during the regular reading operation, S(V_ppDET) = 0 V, and the load of the sense amplifier 1 is the transistors 11 and 12. To the contrary, during the verify reading, S(V_ppDET) = V_cc , and the load transistor 12 is turned OFF. Therefore, the load of the sense amplifier 1 is only the transistor 11. Thus, the magnitude of the load during the verify reading is different from that during the regular reading, so that the magnitude of the sense current can be changed.

0030According to the device shown in Fig. 2, a small sense current can flow during the verify reading, and the reference value of the cell current, for discriminating whether the write operation is completed, is set at a small value so as to ensure the verification of the completion of the programming. Conversely, a large sense current can flow during the regular reading, and the reference value of the sense current for discriminating whether "1" or "0" is set at a large value so as to perform the regular read operation. Therefore, a sufficient margin of the voltage of the power source is ensured to enhance the reliability of the discrimination of information.

0031Figure 4 shows another embodiment of the present invention.

0032In Fig. 4, a gate control signal S(GATE CONTROL) is delivered from a gate voltage generator 7.

0033In a device shown in Fig. 4, the verify read / regular read operation discrimination signal S(V_ppDET) is input to the gate voltage generator 7. In response to the signal S(V_ppDET), the gate voltage generator 7 generates and applies the gate signal S(GATE CONTROL) to the gate of the load transistor 11. In this case, only the transistor 11 serves as the load transistor.

0034When S(V_ppDET) = 0 V, S(GATE CONTROL) = 0 V, and when S(V_ppDET) = V_cc , S(GATE CONTROL) is at an intermediate level between V_cc and 0 V. As a result, conductance of the transistor 11 varies to change the ability for flowing the current. Accordingly, the magnitude of the sense current during the verify read operation can be changed from that during the regular read operation.

0035Figure 5 shows still another embodiment of the present invention. Figure 5 shows a regular reading sense amplifying section 100, a sense output S(100) of the regular reading sense amplifying section 100, a verify reading sense amplifying section 150, and a sense output S(150) of the verify reading sense amplifying section 150.

0036In the sense amplifier 1 of a device shown in Fig. 5, a channel width / channel length ratio W/L of the load transistor 101 of the regular reading sense amplifying section 100 is different from that of the load transistor 151 of the verify reading sense amplifying section 150, i.e., the transistor 101 is larger than the transistor 151. Thus, the sense amplifying sections 100 and 150 in the sense amplifier 1 are switched to be selectively used during the regular reading and during the verify reading. The sense output S(100) or S(150) of the selected section is output as the sense output through the NAND gate 9. Therefore, according to the device shown in Fig. 5, the magnitude of the sense current during the verify reading can be changed from that during the regular reading.