Buffer circuit

57 An integrated circuit unity gain buffer amplifier suitable for low voltage operation in which the input signal is applied to the base of a common emitter NPN transistor first stage (Q1). The collector of the first stage is connected to the base of an emitter follower NPN transistor second stage (Q2). The emitter of the second stage is connected to the base of an emitter follower PNP transistor third stage (Q3). The collector of the first stage is loaded by a constant current source (4) and its emitter is connected through a resistance (R1) to ground. The collector and emitter of the second and third stages respectively are connected together through a resistor (R3) to the supply voltage (Vcc). The emitter of the second stage is connected through a resistance (R2) to ground. The collector of the third stage is connected both to the output terminal (6) and to the emitter of the firs! stage. This allows the circuit to operate at a very low supply voltage without any transistor operating in practical saturation.