Buffer circuit.

This invention relates to a buffer circuit suitable for very low voltage operation.

Integrated circuits commonly require buffer circuits which can operate at a low supply voltage. It is known to provide a buffer circuit for operation at low supply voltages, comprising: first and second transistors of opposite conductivity types, first and second terminal means for connection to a source of supply voltage, input signal terminal means connected to the base of the first transistor, the emitter of which is connected through a first resistance means to the first terminal means, and current source means connected between the collector of the first transistor and the second terminal means for loading the first transistor, the collector of the second transistor being connected to output terminal means and also to the emitter of the first transistor, and the emitter of the second transistor being coupled to the second terminal means, so that an input signal applied at the input signal terminal will cause a corresponding signal at said output terminal means.

A common difficulty in the past has been that when the battery which supplies power to the integrated circuit nears the end of its useful life, the battery voltage drops substantially. When this occurs, one or more stages of the buffer circuit may become saturated. When a stage becomes saturated, its gain falls drastically; its input bias current requirement increases, and in general the performance of the stage deteriorates enormously. The circuit ceases to perform adequately when one or more of its stages become saturated.

Therefore it is an object of the present invention to provide a buffer circuit which is adapted to operate with a low supply voltage and which is less likely than prior art circuits to suffer from saturation of one or more of its stages. To this end the invention provides in its broadest aspect a buffer circuit of the above type and characterised in that the circuit is adapted for operation at a low supply voltage by the provision of a third transistor of the same conductivity type as the first transistor, whose base is connected to the collector of the first transistor, whose emitter is connected to the base of the second transistor and connected through second resistance means to the first terminal means, and whose collector is coupled to the second terminal means, the emitter of the second transistor being coupled to the second terminal means by way of a third resistance means.

In order that the invention may be better understood, a preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, wherein: <ul id="ul0001" list-style="none"><li>Figure 1 is a schematic view of a typical prior art buffer circuit; and</li><li>Figure 2 is a schematic view of a preferred circuit embodying the invention.</li></ul>

Reference is first made to Figure 1, which shows an NPN transistor Qll having an input signal terminal 2 connected to its base and having its collector connected to the base of a PNP transistor Q12. The collector of transistor Qll is also connected through a current source 4 (typically a PNP transistor) to the positive terminal of a source of supply voltage Vcc. The emitter of transistor Q11 is connected through resistor R1 to ground (which is connected to the negative terminal of the supply voltage source).

The emitter of transistor Q12 is connected to the supply voltage Vcc, and the collector of transistor Q12 is connected to an output signal terminal 6 and also to the emitter of transistor Q11.

The circuit of Fig. 1 is assumed to be fabricated as an integrated circuit, in which transistors Q11, Q12, the current source 4, and resistor R1 and their connections are all deposited on a common substrate in miniature form. Since the technology of fabricating integrated circuits per se is very well known and does not form part of this invention, the mechanical construction of such integrated circuit will not be described.

In normal operation, with no transistors saturated, transistor Q11 functions as a common emitter stage, providing high gain. Transistor Q12 is a common emitter PNP stage which supplies negative feedback from its collector to the emitter of transistor Q11, so that the difference between the input and output signals is amplified by transistor Q11. The result is that the Fig. 1 circuit in normal operation functions as a unity gain non-inverting buffer amplifier.

In operation the base of transistor Q11 is typically biased to about .65 volts. In addition, in many circuits the supply voltage source Vcc is provided by a single battery cell 10 and a voltage regulator 12 (e.g. in hearing aids). To allow for a drop in the battery voltage near the end of the battery's life, the supply voltage Vcc should be set lower than the battery voltage near the end of the battery's life. It may therefore be desired to set voltage Vcc at about 0.9 volts.

It is well known that the base-emitter voltage of a typical integrated circuit PNP transistor such as Q12 is normally .6 volts. (For an integrated circuit NPN transistor the base-emitter voltage is typically 0.6 volts.) This places .6 volts across the current source 4 and places the collector of transistor Q11 at .3 volts. These voltages are all marked in parentheses in Fig. 1 for explanatory purposes.

Since the base of transistor Q11 is as indicated biased to .65 volts, it will be seen that the collector voltage of transistor Q11 is well below the base voltage. This places transistor Q11 in saturation.

Technically saturation occurs when the base-collector junction of a transistor is forward biased. In practice, serious degradation of the transistor's performance does not occur until the base-collector junction is forward biased by about .35 volts for an NPN integrated circuit transistor and about .4 volts for a PNP integrated circuit transistor. The precise voltage in question depends on the device geometry and the fabrication technology. The point at which such degradation occurs will be referred to as practical saturation.

In the Fig. 1 circuit it will be seen that the base-collector junction of transistor Q11 is forward biased by .35 volts. This causes practical saturation which is undesirable. In addition the beta constant of transistor Q12 is typically low in integrated circuits and this necessitates a higher collector current in transistor Q11 and hence higher input bias current. In addition transistor Q12 loads the collector of transistor Q11, reducing loop gain.

Reference is next made to Fig. 2, which shows a preferred circuit embodying the invention. In Fig. 2 corresponding reference numerals indicate corresponding parts, but three transistors are provided, namely transistors Q1, Q2 and Q3. Transistor Q1 is connected in a common emitter configuration the same as transistor Q11. The collector of transistor Q1 is connected to the base of transistor Q2. Transistor Q2 has its emitter connected through resistor R2 to ground and its collector connected to the emitter of transistor Q3. The emitter of transistor Q3 is connected through resistor R3 to the supply voltage Vcc. The emitter of transistor Q2 is connected to the base of transistor Q3, and the collector of transistor Q3 is connected both to the output signal terminal 6 and to the emitter of transistor Q1.

The DC operation of the Fig. 2 circuit is as follows. As in the Fig. 1 circuit, transistor Q1 operates as a common emitter amplifier with current source 4 as an active load. The current supplied by current source 4 is chosen to be very small, typically one microampere, so that the base current of transistor Q1 is only a few nanoamperes. In addition the base of transistor Q1 is again typically biased to about 0.65 volts by an external biasing circuit (not shown). This sets the voltage across resistor R1 at .65 volts less the base-emitter voltage of transistor Q1. The base-emitter voltage of transistor Q1 is defined by the geometry of transistor Q1 so that the voltage across resistor R1 is typically 0.15 volts. The following equations are then applicable (ignoring base current effects, which are small), where: <ul id="ul0002" list-style="none"><li>VBE1 is the base-emitter voltage of transistor Q1,</li><li>VBE2 is the base-emitter voltage of transistor Q2,</li><li>VBE3 is the base-emitter voltage of transistor Q3,</li><li>VCE2 is the collector-emitter voltage of transistor Q2,</li><li>VBC2 is the base-collector voltage of transistor Q2,</li><li>I is the current supplied by current source 4,</li><li>IC2 is the collector current of transistor Q2,</li><li>IC3 is the collector current of transistor Q3,</li><li>VR1 is the voltage across resistor R1,</li><li>VR2 is the voltage across resistor R2,</li><li>VR3 is the voltage across resistor _R3,</li></ul>

It can be seen from the circuit of Fig. 2 that <ul id="ul0003" list-style="none"><li>IC2.R2 + (IC2 + IC3) R3 = Vcc - VBE3...(1)</li><li>Also IC3 = .150/R1 - I</li></ul>

If IC3 is much greater than I, then <ul id="ul0004" list-style="none"><li>IC3 ≈ to .150/R1...(2)</li><li>Combining equations 1 and 2 above,<maths id="math0001" num=""><img file="EP0180337A2_D0001.tif" /></maths></li></ul>

If all resistors are equal in value to resistance R, then<maths id="math0002" num=""><img file="EP0180337A2_D0002.tif" /></maths>

Typically R = 5000 ohms, so that IC2 = 15 uA for Vcc = 0.9 volts and VBE 3 = 0.6 volts (from equation 1). In addition, IC3 ≈ 30 uA (from equation 2). These voltages, and those discussed below, are all marked in Fig. 2 for exemplary purposes.

It will be seen from Fig. 2 that <ul id="ul0005" list-style="none"><li>VR3 + VCE2 + VR2 = .9 volts...(4)</li><li>Now VR3 = (IC3 + IC2) R3 = .225 volts</li><li>and VR2 = IC2.R2 = .075 volts</li></ul>

Therefore from equation (4), <ul id="ul0006" list-style="none"><li>VCE2 = .6 volts.</li></ul>

Since VBE2 = .6 volts (for an integrated circuit NPN transistor), therefore

VBC2 = zero volts.

It will thus be seen from Fig. 2 that the voltage across current source 4 is VR3 + VBC2, which is .225 volts. This is sufficient to keep current source 4 (which is typically a PNP transistor) out of practical saturation. In addition the collector of transistor Q1 is at a potential .225 volts below Vcc, i.e. it is at .675 volts.

As noted, the base of transistor Q1 is biased at .65 volts. It will be seen that this is below the voltage of .675 volts at the collector of transistor Q1. Since the base voltage of transistor Q1 is below its collector voltage, the base collector junction remains reverse biased and transistor Q1 is not saturated.

Similarly, the collector voltage of transistor Q2 remains at zero volts above its base voltage so that transistor Q2 is not operated in saturation.

Further, the base of transistor Q3 is biased at .075 volts, while the collector of transistor Q3 is biased at .15 volts, only slightly above the base voltage so that transistor Q3 is not operated in practical saturation. The result is that no transistor of the Fig. 2 circuit is operated in practical saturation, even with Vcc as low as 0.9 volts.

The connection of the collector of transistor Q2 to the emitter of transistor Q3, rather than to Vcc allows resistor R3 to be smaller for the same voltage at the emitter of transistor Q13. This reduces the area required for resistor R3 in integrated circuit implementation and also produces some increase in open loop gain. If desired the collector of transistor Q2 could be connected directly to the supply voltage Vcc, but the arrangement shown is preferred.

The AC operation of the Fig. 2 circuit is best understood by assuming that the collector of transistor Q2 is connected to the supply voltage Vcc rather than to the emitter of transistor Q3. This simplification results in only a minor error in the derived value for open loop gain. It will then be seen that transistor Q1 acts as a common emitter stage, amplifying the difference between the input and output signals. The current source 4 is an active load for transistor Q1, providing high gain (typically 200).

Transistor Q2 in combination with resistor R2 acts as an emitter follower impedance buffer and level shifter. Transistor Q3 is connected in a common emitter configuration with emitter degeneration resistor R3. Resistor R1 serves as the collector load for transistor Q3. It will be seen that with a gain of 200 in the first stage and approximately unity gain in the following stages, the output voltage must closely follow the input voltage, in accordance with conventional feedback theory. Conventional feedback theory also indicates that the output impedance is approximately R1/200 (since the loop gain is 200) or 25 ohms. The feedback will also multiply the input impedance of transistor Q1 by approximately 200.

The concentration of all of the gain in the first stage, and the use of local feedback in the third stage, ensures that the circuit is stable under closed loop conditions.

Although transistors Q1 and Q2 have been shown as NPN transistors and Q3 as a PNP transistor, this can if desired be reversed.