GaN film having a reduced threading dislocations density and fabrication method thereof
24 claims: 5 independent, 19 dependent
- 1Halbleiterdünnfilm mit einer unteren Halbleiterschicht ( 2 ), in der eine Vielzahl von Facetten ( 1 ) angeordnet ist, und mit einer selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ), die so ausgebildet ist, daß sie die genannte untere Halbleiterschicht ( 2 ) vollständig überdeckt, wobei die Facetten ( 1 ) künstlich von Ebenen gebildet werden, die gegenüber der Anordnungsebene der unteren Halbleiterschicht ( 2 ) geneigt sind, so daß in der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) Durchstoßungsversetzungen (d) in einer solchen Weise ausgebildet werden, daß jede dieser Durchstoßungsversetzungen (d) gebogen von einer der genannten Facetten ( 1 ) der unteren Halbleiterschicht ( 2 ) in einer Richtung im wesentlich entlang der Anordnungsebene der unteren Halbleiterschicht ( 2 ) verläuft, wobei sie mit einer anderen der genannten Durchstoßungsversetzungen (d) verbunden wird, die gebogen von dem gegenüberliegenden Exemplar der genannten Facetten ( 1 ) aus verläuft und gebogen von dem verbundenen Abschnitt in der Richtung verläuft, die die Anordnungsebene der unteren Halbleiterschicht ( 2 ) kreuzt.
- 2Halbleiterdünnfilm nach Anspruch 1, bei dem die Abweichung der Kristallorientierung zwischen der unteren Halbleiterschicht ( 2 ) und der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) im Bereich von 0,1 ° oder weniger liegt.
- 3Halbleiterdünnfilm nach Anspruch 1, ferner mit einer Verbundhalbleiterschicht ( 8 ), die aus einem Gruppe-III-Nitrid hergestellt ist, das Stickstoff (N) sowie wenigstens eine Art eines Gruppe-III-Elements enthält, das aus einer Gruppe ausgewählt ist, die aus Gallium (Ga), Aluminium (Al), Bor (B) und Indium (In) besteht, wobei die Verbundhalbleiterschicht ( 8 ) durch die untere Halbleiterschicht ( 2 ) und die selektiv gezüchtete/vergrabene Halbleiterschicht ( 3 ) auf einem Substrat ausgebildet ist.
- 4Halbleiterdünnfilm nach Anspruch 3, bei dem die selektiv gezüchtete/vergrabene Halbleiterschicht ( 3 ) aus einem Verbundhalbleiter hergestellt ist, der aus einem Gruppe-III-Nitrid besteht, das Gallium (Ga) und Stickstoff (N) enthält.
- 5Haibleiterdünnfilm nach Anspruch 3, bei dem das genannte Substrat ( 6 ) aus Saphir hergestellt ist.
- 6Halbleiterdünnfilm nach Anspruch 3, bei dem das genannte Substrat ( 6 ) aus Siliziumkarbid, SiC hergestellt ist.
- 7Halbleiterdünnfilm nach Anspruch 3, bei dem das genannte Substrat ( 6 ) aus einem Galliumnitrid-Einkristall hergestellt ist.
- 8Halbleiterdünnfilm nach Anspruch 7, bei dem die untere Halbleiterschicht ( 2 ) direkt auf dem genannten Substrat ( 6 ) ausgebildet ist.
- 9Halbleiterelement mit einem Halbleiterhauptkörper, der auf einem Halbleiterdünnfilm ausgebildet ist, dadurch gekennzeichnet, daß der Halbleiterdünnfilm einem der Ansprüche 1 bis 8 entspricht.
- 10Halbleiteranordnung, die ein Halbleiterelement nach Anspruch 9 aufweist.
- 11Verfahren zur Herstellung eines Halbleiterdünnfilms mit den Verfahrensschritten:Ausbilden einer unteren Halbleiterschicht ( 2 ) auf einem Substrat ( 6 ) in der Weise, daß in der unteren Halbleiterschicht ( 2 ) eine Vielzahl von Facetten ( 1 ) angeordnet wird, und Züchten einer selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) in einer solchen Weise, daß die selektiv gezüchtete/vergrabene Halbleiterschicht ( 3 ) die untere Halbleiterschicht ( 2 ) vollständig überdeckt, wobei die Facetten ( 1 ) künstlich von Ebenen gebildet werden, die gegenüber der Anordnungsebene der unteren Halbleiterschicht ( 2 ) geneigt sind, und wobei der Verfahrensschritt des Züchtens der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) den Verfahrensschritt umfaßt: Züchten der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) von den Facetten ( 1 ) der unteren Halbleiterschicht ( 2 ) in der im wesentlichen entlang der Anordnungsebene der unteren Halbleiterschicht ( 2 ) verlaufenden Richtung, wobei in der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) Durchstoßungsversetzungen (d) in einer solchen Weise ausgebildet werden, daß jede dieser Durchstoßungsversetzungen (d) gebogen von einer der genannten Facetten ( 1 ) der unteren Halbleiterschicht ( 2 ) in einer Richtung im wesentlich entlang der Anordnungsebene der unteren Halbleiterschicht ( 2 ) verläuft, wobei sie mit einer anderen der genannten Durchstoßungsversetzungen (d) verbunden ist, die gebogen von dem entgegengesetzten Exemplar der genannten Facetten ( 1 ) verläuft und gebogen von dem verbundenen Abschnitt in der die Anordnungsebene der unteren Halbleiterschicht ( 2 ) kreuzenden Richtung verläuft.
- 12Verfahren zur Herstellung eines Haibleiterdünnfilms nach Anspruch 11, bei dem die untere Halbleiterschicht ( 2 ) auf dem Substrat ( 6 ) durch selektives Wachstum in der Weise aufgebracht wird, daß in der unteren Halbleiterschicht ( 2 ) eine Vielzahl von Facetten angeordnet wird.
- 13Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem der Verfahrensschritt des Ausbildens der unteren Halbleiterschicht ( 2 ) durch reaktives Ionenätzen unter Verwendung einer Maske durchgeführt wird.
- 14Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem der Verfahrensschritt des Ausbildens der unteren Halbleiterschicht ( 2 ) durch reaktives Ionenätzen unter Verwendung einer aus Siliziumdioxid, Siliziumnitrid oder Aluminiumoxid hergestellten Maske durchgeführt wird.
- 15Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem die Abweichung der Kristallorientierung zwischen der unteren Halbleiterschicht ( 2 ) und der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) im Bereich von 0,1° oder weniger liegt.
- 16Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, mit dem weiteren Verfahrensschritt:Züchten einer Verbundhalbleiterschicht ( 8 ) auf der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ), wobei die Verbundhalbleiterschicht ( 8 ) aus einem Gruppe-III-Nitrid hergestellt ist, das Stickstoff (N) sowie wenigstens eine Art eines Gruppe-III-Elements enthält, das aus einer Gruppe ausgewählt ist, die aus Gallium (Ga), Aluminium (Al), Bor (B) und Indium (In) besteht.
- 17Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem die selektiv gezüchtete/vergrabene Halbleiterschicht ( 3 ) aus einem Verbundhalbleiter hergestellt ist, der aus einem Gruppe-III-Nitrid besteht, das Gallium (Ga) und Stickstoff (N) enthält.
- 18Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem der Verfahrensschritt des Züchtens der selektiv gezüchteten/vergrabenen Halbleiterschicht ( 3 ) mittels eines Verfahrens der chemischen Ablagerung aus der Dampfphase durchgeführt wird.
- 19Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem das genannte Substrat ( 6 ) aus Saphir hergestellt ist.
- 20Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem das genannte Substrat ( 6 ) aus Siliziumkarbid, SiC hergestellt ist.
- 21Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem das genannte Substrat ( 6 ) aus einem Galliumnitrid-Einkristall hergestellt ist.
- 22Verfahren zur Herstellung eines Halbleiterdünnfilms nach Anspruch 11 oder 12, bei dem die untere Halbleiterschicht ( 2 ) direkt auf dem genannten Substrat ( 6 ) ausgebildet ist.
- 23Verfahren zur Herstellung eines Halbleiterelements, das einen Halbleiterhauptkörper auf einem Halbleiterdünnfilm aufweist, der nach einem der Ansprüche 1 bis 8 hergestellt ist.
- 24Verfahren zur Herstellung einer Halbleiteranordnung, welches das Verfahren zur Herstellung des Halbleiterelements nach Anspruch 23 umfaßt.
Independent claims24
111 paragraphs, as filed
0001the This invention relates to a semiconductor thin film made of a compound semiconductor is typically made of a group III nitride, and also a semiconductor element using the semiconductor thin film, and a semiconductor device, which uses the semiconductor element, as well as corresponding manufacturing process.
0002In recent years, the development of light emitting Semiconductor devices such as semiconductor lasers or light-emitting Diodes (LEDs) is activated, the light emission in the visible allow light to ultraviolet light, said compound semiconductor, as AlGaInN, were used on the basis of group-III nitride. In the field of optical recording rose particularly the demand for a semiconductor laser which is capable of light in the short wavelength region to emit and can be used in practice to the recording density improve optical disks or the like..
0003In younger Time was in Jpn. J. Appl. Phys. 35L74 (1996) and ditto 36L1059 (1997) on a semiconductor laser based on AlGaInN reported that in is capable of 300 hours at room temperature continuous wave to realize, wherein one organometallic by a method for chemical vapor deposition (MOCVD) on a substrate of sapphire over a buffer layer of gallium nitride (GaN), a semiconductor layer of a compound semiconductor on the basis of group-III nitride is grown.
0004at the semiconductor laser described above, however, a problem occurs on. As can be seen from the curve, the change of the semiconductor laser applied voltage over time shows the growing Drive voltage from the initial live period gradually at. This means that the voltage characteristic over time gradually worse becomes. The deterioration of the voltage characteristic can it depend, that on the substrate compound semiconductor formed on the basis of Group III nitride dislocations (These are defects that propagate and pass through the crystal) having a density in the range of 1 × 10<sup>8</sup>/cm<sup>2</sup> to about 1 x 10<sup>9</sup>/cm<sup>2</sup> having.
0005Around a practical service life of the semiconductor laser of 10,000 hours to achieve or more, must therefore the density of the threading dislocations be reduced. to fulfill this demand, various methods have been studied.
0006In the European Patent Application 0,469,790 A has been proposed a method in the one by epitaxial layers on a substrate faulted formed semiconductor device comprises a low density of dislocation defects having to by the thickness of the epitaxial layer in comparison its maximum lateral dimension made sufficiently large becomes. With sufficient thickness occur coming from the interface dislocations from the sides of the epitaxial structure and reach the top surface not.
0007This However, process limits the lower thickness of the semiconductor film and does not reduce the density of threading dislocations, the inclination a exceeds certain value, which depends on the dimensions of the epitaxial layer.
0008In Jpn. J. Appl. Phys. 36L899 (1997), J. Appl. Phys. 71, 2638 (1997) and Appl. Phys. Lett. Volume 71, no. 16 (20 October 1997), a proposed method in which a on a sapphire substrate by Buffer layer a lower GaN layer is formed, then the GaN layer, a mask layer of silicon dioxide (SiO<sub>2</sub>) Is arranged, the periodic one Pattern of stripes (width of 1 to 4 microns), which at a distance of 7 microns are arranged, and on the mask layer selectively in the lateral Direction by a halide vapor deposition method or MOCVD method grown a GaN layer becomes. If the method is applied, in which the GaN semiconductor layer is grown on the mask layer in the lateral direction by it selectively leaves grow from the lower GaN layer GaN, the through openings exposed between the periodic stripes of the mask layers are, the density of threading dislocations in the GaN layer on SiO<sub>2</sub>Mask layer to about 1 × 10<sup>7</sup>/cm<sup>2</sup> be reduced.
0009As in Journal of Crystal Growth, vol 189-190, page 820-5 (1998) reported is, to semiconductor laser diodes can be on AlGaInN base that on the Semiconductor layer produced by the application of the above process be formed with a practical service life of 1150 hours or realize more. In view of the by selective growth formed using the mask layer above Semiconductor layer have discovered, the present inventors randomly, that between a portion of the semiconductor layer on the stripe of the mask layer and a part of the semiconductor layer in the opening of the mask layer a Deviation in crystal orientation (c-axis) occurs in the the order of 0.4 ° to 0.5 °.
0010If on the semiconductor layer, the such a deviation in crystal orientation having, a semiconductor element is formed, containing an active Region of the semiconductor element, the deviation in crystal plane. This has the consequence that various characteristics of the semiconductor element deteriorate and when the semiconductor element is formed as a semiconductor laser, the efficiency of light emission and the life are degraded.
0011in the following are the problems in detail explained, the when the above-mentioned conventional methods occur. A substrate for culturing a semiconductor based on GaN, which, as described above, from Sapphire or SiC is produced, is different in lattice constant and in thermal expansion coefficient significantly from the semiconductor GaN-based, and therefore occur in the layer growth defects, how to dislocations when the semiconductor GaN based directly on the substrate grows, with the result that it is difficult to obtain a high-quality single crystal on the epitaxial Semiconductor layer to grow GaN-based.
0012Out this reason, as described above, a lower GaN layer, the threading dislocations contains a high density, formed on the sapphire substrate or the SiC substrate through a buffer layer, on the lower GaN layer, a mask layer is formed, the of SiO<sub>2</sub> produced and patterned in stripes is arranged with a specific distance, and the lower GaN layer, the through openings between the stripes the mask layer is exposed, GaN is selectively laterally bred direction thereby forming the GaN semiconductor on the mask layer, contains the defects in a low density. As a result of analysis the sample thus prepared by electron diffraction or X-ray diffraction However demonstrated that between a part of the formed on the stripes of the mask layer GaN semiconductor layer and a portion of the opening formed in the mask layer GaN semiconductor layer has a deviation in the Kristallorie ntierung occurs, of the order of 0.4 ° to 0.5 °.
0013Of the The reason for this, why a deviation in crystal orientation (c-axis) occurs, is that in the lateral growth of GaN on the SiO<sub>2</sub>mask layer between a portion of the strip of the mask layer and a portion in the opening the mask layer has a deviation in the direction of crystal growth occurs.
0014On the base of the performed by the inventors, structure analysis by means Transmission Electron Microscopy or the X-ray diffraction method, it turned out that a deviation occurs in the direction of crystal growth along the <11-20> direction and crystal defects arise when the orientation of the stripes of the SiO<sub>2</sub>- Mask to the <11-20> direction is set, that contrast no crystal defects occur when the orientation of the stripes the SiO<sub>2</sub>Mask to the <1-100> direction is set and a deviation in along the direction of crystal growth the <1-100> direction takes place. In any case However, a deviation occurs in the orientation of crystal growth to which of the difference in thermal expansion coefficient between SiO<sub>2</sub> as a mask material and GaN depends. As a result, it is possible to reduce the deviation in the orientation of crystal growth, if, in the lateral growth of GaN, the SiO<sub>2</sub>mask layer does not exist.
0015At the Prior art has placed a great importance on an epitaxial breeding methods with not matching [non-matching] grid available to provide in order to gain an epitaxial growth layer, the low has dislocation density, as shown in <patcit><text>JP 08064791 A</text></patcit> disclosed is. The method consists in a on a sapphire substrate amorphous GaN film growing up to be. The amorphous GaN is formed by etching to Strip shaped, and then allowed to on the strip a GaN film epitaxially grown.
0016A However amorphartige GaN layer produces the same effects as an oxide film or a mask, and shall meet as a significant Deviation in the GaN crystal orientation.
0017There the SiO<sub>2</sub>is mask layer provided dislocations eliminate from the substrate side to the semiconductor layer, compatible eliminating the mask layer is not the purpose of the defect density the semiconductor layer to reduce.
0018It An object of the present invention, a semiconductor thin film, which is able to reduce the density of threading dislocations and also the occurrence of a deviation in crystal orientation to suppress, Further, a semiconductor element using the semiconductor thin film, and a semiconductor device using the semiconductor element, to disposal deliver. It is a further object of the invention to provide methods for Production of this semiconductor thin film, the semiconductor element and the semiconductor device available to put.
0019the We have found the following: While in the lateral growth a semiconductor threading dislocations are bent by growth facets, which, accompanied by the growth, are generated, such a bending of the dislocations not only by the aforementioned Growth facets broughtout be, but also by artificially trained facets. Based on this finding, the Inventor a semiconductor thin film brought about, in which the density of threading dislocations reduced in a specific region and also the occurrence of a Deviation in crystal orientation can be suppressed, and a semiconductor element, the semiconductor thin film used, and a semiconductor device, the semiconductor element, the used, and manufacturing method thereof.
0020the Invention is shown in the appended claims.
0021As has been described above, in the semiconductor thin film, the semiconductor element, the semiconductor device and the process for their preparation According to the invention, the selective grown / buried Semiconductor layer selectively from the facets, ie the inclination levels the lower semiconductor layer grown from. With this configuration, be in the selectively grown / buried Semiconductor layer dislocations formed in the manner that each these dislocations extends laterally, ie bent from one of said facets of the lower semiconductor layer in a direction substantially along the disposition plane of the lower semiconductor layer extends, wherein it with another of said dislocations connects that bent from the opposite copy of that runs facets and bent extends from the connection point of in the direction the assembly plane of the lower semiconductor layer crosses. As a result, can be in other parts than the connecting sections mentioned above the threading dislocations Regions with low defect density, where almost dislocations are present in the selectively grown / buried semiconductor layer produce.
0022There continue the present Invention is not applied the configuration in which the out SiO<sub>2</sub> buried, or the like. prepared mask is the occurrence of the deviation described above, in the Crystal orientation (c-axis) can be prevented.
0023There wherein the semiconductor element of the present Invention and the semiconductor element-use semiconductor device an active region (work area) of the semiconductor element on a region of the selectively grown / buried Semiconductor layer having a low defect density or in a subsequent formed semiconductor layer is formed, can Properties of the semiconductor element can be improved.
0024It Note that the Facet of the present Invention means not only a perfect slant plane, but a plane which is somewhat curved partially or entirely and its principal plane tilted at a specific angle α is.
0025<figref idrefs="S25">1</figref> shows is a schematic sectional view of an embodiment of a semiconductor thin film according to the invention,
0026<figref idrefs="S25">2</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention,
0027<figref idrefs="S26">3</figref> shows is a schematic sectional view of another embodiment the Haibleiterdünnfilms according to the invention,
0028<figref idrefs="S26">4</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention,
0029<figref idrefs="S27">5</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention,
0030<figref idrefs="S27">6</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention,
0031<figref idrefs="S28">7</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention,
0032<figref idrefs="S28">8</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention,
0033<figref idrefs="S29">9A</figref> to <figref idrefs="S29">9C</figref> show are schematic sectional views of fragments of a semiconductor thin film in processing steps according to one embodiment of a method for producing a semiconductor thin film according to the invention,
0034<figref idrefs="S30">10A</figref> to <figref idrefs="S30">10B</figref> show are schematic cross sections of fragments of the semiconductor thin film in process steps in the <figref idrefs="S29">9A</figref> to <figref idrefs="S29">9C</figref> illustrated Steps to connect,
0035<figref idrefs="S31">11A</figref> to <figref idrefs="S31">11C</figref> show are schematic sectional views of fragments of a semiconductor thin film in process steps according to another exemplary embodiment of a method for producing a semiconductor thin film according to the invention,
0036<figref idrefs="S32">12A</figref> and <figref idrefs="S32">12B</figref> show are schematic sectional views of fragments of the semiconductor thin film in process steps, resulting in the <figref idrefs="S31">11A</figref> to <figref idrefs="S31">11C</figref> Method steps shown connect,
0037<figref idrefs="S33">13</figref> shows a schematic cross section of an embodiment of a light emitting Semiconductor element according to the invention,
0038<figref idrefs="S34">14</figref> shows a schematic cross section of a further embodiment of the semiconductor light emitting element according to the invention.
0039in the following are embodiments of the Invention with reference to the accompanying drawings.
0040<figref idrefs="S25">1</figref> shows is a schematic sectional view of an embodiment of a semiconductor thin film according to the invention. The semiconductor thin film has a lower semiconductor layer <figref>2</figref>In which a plurality of facets <figref>1</figref> is arranged, and a selectively grown / buried Semiconductor layer which is formed so that the lower semiconductor layer <figref>2</figref> covered. The lower semiconductor layer <figref>2</figref> is made of a compound semiconductor a group III Nitridtyps made of gallium (Ga) and nitrate (s). the selectively bred / buried semiconductor layer is also made of a compound semiconductor of a group III nitride established, the Ga and N. The facet <figref>1</figref> is formed from a plane, the relative the arrangement plane A of the lower semiconductor layer <figref>2</figref> inclined is.
0041Dislocations "d" in the selectively grown / buried semiconductor layer <figref>3</figref>, the in <figref idrefs="S25">1</figref> are represented by fine lines, are formed such that each the threading dislocations "d" from one of the facets <figref>1</figref> of the lower semiconductor layer <figref>2</figref> bent in a direction substantially along the plane of arrangement of the lower semiconductor layer <figref>2</figref> extends, said it coincides with another of the threading dislocations, "d", the bent from the opposing Copy of said facets <figref>1</figref> runs out, and bent from the joint in which the plane of arrangement of lower semiconductor layer <figref>2</figref> intersecting direction, more precisely in a substantially vertical direction, runs.
0042This has the consequence that in the selectively grown / buried Semiconductor layer <figref>3</figref>That the cover of the lower semiconductor layer <figref>2</figref> scheduled is, at the connecting locations of the threading dislocations "d" regions <figref>4</figref> high defect density are formed, which in the dislocations of a having high density. In the other Portions are regions <figref>5</figref> low defect density formed, in which hardly dislocations occur.
0043<figref idrefs="S25">2</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention. First is a substrate <figref>6</figref> produced, or from C-surface sapphire SiC. subsequently is on a principal plane <figref>6a</figref> the substrate <figref>6</figref> by a buffer layer <figref>7</figref> a lower semiconductor layer <figref>2</figref> educated, the facets <figref>1</figref> are arranged.
0044<figref idrefs="S26">3</figref> shows a sectional view of another embodiment of the semiconductor thin film according to the invention. First is a substrate <figref>6</figref> prepared from the C-surface sapphire or SiC. subsequently is on a principal plane <figref>6a</figref> the substrate <figref>6</figref> over a buffer layer <figref>7</figref> a lower layer <figref>12</figref> educated, and on the lower layer <figref>12</figref> is a lower semiconductor layer <figref>2</figref> educated, the facets <figref>1</figref> are arranged.
0045<figref idrefs="S26">4</figref> shows is a schematic sectional view of another embodiment of the semiconductor thin film according to the invention. First is a substrate <figref>6</figref> prepared consisting of a single crystal of an Group III nitride is, and then directly to a main level <figref>6a</figref> the substrate <figref>6</figref> a lower semiconductor layer <figref>2</figref> educated, consisting of a Group III nitride and in the facet <figref>1</figref> arranged are.
0046<figref idrefs="S27">5</figref> to <figref idrefs="S28">8</figref> show are schematic sectional views of further embodiments of the semiconductor thin film according to the invention. Each of the in <figref idrefs="S27">5</figref> to <figref idrefs="S28">8</figref> illustrated embodiments is formed so that on the selectively grown / buried Semiconductor layer <figref>3</figref>Which, in conjunction with one of the embodiments of <figref idrefs="S25">1</figref> to <figref idrefs="S26">4</figref> has been described, a compound semiconductor layer <figref>8</figref> epitaxially is grown, the is composed of a group III nitride containing nitrogen (N) and at least contains one kind of group III element selected from a group comprising of gallium (Ga), aluminum (Al), boron (B) and indium (In) consists. In this case, the threading dislocations extend in the lower selectively grown / buried Semiconductor layer <figref>3</figref> in the compound semiconductor layer <figref>8</figref>. and in the compound semiconductor layer <figref>8</figref> are regions <figref>4</figref> With high defect density and regions <figref>5</figref> low defect density and without threading dislocations generated.
0047On embodiment a semiconductor element according to the invention is characterized in that in of the region <figref>5</figref> low defect density of selectively bred / buried Semiconductor layer of each of the semiconductor thin films of <figref idrefs="S25">1</figref> to <figref idrefs="S26">4</figref> at least an active region, that is, a work area, the crystal defects affect the semiconductor element is is formed.
0048On Another embodiment of the semiconductor element according to the invention is characterized in that at least an active region, that is, a work area, the crystal defects affect the semiconductor element is, in the region <figref>5</figref> with low defect density of the compound semiconductor <figref>8</figref> each the semiconductor thin films of <figref idrefs="S27">5</figref> to <figref idrefs="S28">8</figref> is formed.
0049It Note that in <figref idrefs="S25">2</figref> to <figref idrefs="S28">8</figref> such Parts corresponding to parts of <figref idrefs="S25">1</figref> comply with the same Designations are provided and that their duplicate explanation is omitted here.
0050In each of the above embodiments is with respect to the semiconductor thin film the deviation in crystal orientation, that is, a deviation in the direction of c-axis between the lower semiconductor layer <figref>2</figref> and the selectively grown / buried Semiconductor layer <figref>3</figref> or between the lower semiconductor layer <figref>2</figref> and the on the selectively grown / buried Semiconductor layer <figref>3</figref> epitaxially grown compound semiconductor layer <figref>8</figref> so adjusted to in the range of 0.1 ° or less.
0051As next is based on <figref idrefs="S29">9A</figref> to <figref idrefs="S29">9C</figref> and of <figref idrefs="S30">10A</figref> and <figref idrefs="S30">10B</figref> a A process for producing a semiconductor thin film described in accordance with the invention.
0052first let on <figref idrefs="S29">9A</figref> Referring. It is a substrate<figref>6</figref> out produced a C-surface sapphire, and on one principal plane <figref>6a</figref> the C-surface sapphire is a buffer layer <figref>7</figref> out GaN by the MOCVD method is formed up to a thickness of 30 nm. In the MOCVD method, the temperature is set at 520 ° C and as a source gas are trimethyl gallium gas ((CH<sub>3</sub>)<sub>3</sub>Ga)) and ammonia gas (NH<sub>3</sub>) used.
0053On the buffer layer <figref>7</figref> is a lower semiconductor layer <figref>2</figref> out GaN to a thickness of 2 .mu.m formed by the MOCVD method. is In the MOCVD method the substrate temperature to 1050 ° C set and uses the same source gas as in the preparation the buffer layer <figref>7</figref>, It should be noted that in the lower semiconductor layer <figref>2</figref> Threading dislocations, "d", in the <figref idrefs="S29">9A</figref> by fine lines are shown, in a high density, for example, 1 x 10<sup>9</sup>/cm<sup>2</sup> available.
0054It Referring now to <figref idrefs="S29">9B</figref> Referring. On the lower Semiconductor layer <figref>2</figref> A mask <figref>9</figref> educated. The mask is prepared by the over the entire surface lower semiconductor layer <figref>2</figref> a dielectric SiO<sub>2</sub>Layer at a substrate temperature of 450 ° C to formed a CVD method and the SiO<sub>2</sub>layer by Photolithography and etching is patterned. More specifically, the SiO<sub>2</sub>-Layer is coated with a photoresist layer and the photoresist layer is desired for a Pattern exposed and developed, which has a plurality of strips, which at specific intervals are arranged. By using such a patterned photoresist layer as a mask, the SiO<sub>2</sub>layer selectively etched the mask <figref>9</figref> produce, the stripe-shaped openings <figref>9w</figref> owns. In the mask <figref>9</figref> the stripes run in the <1-100> direction (perpendicular to the plane of <figref idrefs="S29">9B</figref>) and exhibit in the <11-20> direction, the specific distances on.
0055The resulting substrate, wherein the mask <figref>9</figref> on the bottom layer <figref>2</figref> was formed with acetone (CH<sub>3</sub>COCH<sub>3</sub>) And methanol (CH<sub>3</sub>purified OH), for 10 seconds in dilute hydrochloric acid (HCl) or diluted dipped hydrofluoric acid and cleaned with pure water.
0056the interiors the openings <figref>9w</figref> of the mask <figref>9</figref> are selectively etched by reactive ion etching (RIE). there be the strip portions of from the SiO<sub>2</sub>-Layer existing mask <figref>9</figref> etched somewhat, with the result that, as shown in <figref idrefs="S29">9C</figref> shown, the width of individual openings <figref>9w</figref> enlarged and simultaneously the lower semiconductor layer <figref>2</figref> is partially etched, to groove <figref>10</figref> produce, each approximately V-shaped cross-section have. By continuing this etching, the grooves<figref>10</figref> deeper and wider so that, as in <figref idrefs="S30">10A</figref> shown, the mask <figref>9</figref> away is and the upper ends of neighboring copies of the grooves <figref>10</figref> together get connected. As a result, strips<figref>11</figref>, Each triangular have cross-section, formed in such a manner that they are parallel are arranged to each other and on both sides of each strip <figref>11</figref> will facets <figref>1</figref> formed, which at a specific angle are oppositely inclined. The level of training of the grooves<figref>10</figref> used RIE is measured using a parallel plate RIE system using BCl<sub>3</sub> and N<sub>2</sub> as Source gas and having an output of 15 W and a pressure of 20 m Torr.
0057By the RIE under the above conditions are each on both side surfaces strip <figref>11</figref>Which extend in the <1-100> direction, the facets <figref>1</figref> formed relative to the substrate plane, that is, to the lower semiconductor layer <figref>2</figref>, Inclined at 45 ° are.
0058The resulting substrate <figref>6</figref>, On the superimposed semiconductor layers concerned arranged are sufficiently long in hydrofluoric acid (HF) is immersed to the on the surface remaining SiO<sub>2</sub>Film to remove, and then cleaned with pure water.
0059On the thus purified lower semiconductor layer <figref>2</figref>, in the the facets <figref>1</figref> are arranged, is allowed by the MOCVD method GaN high quality epitaxially. In this GaN is selectively from the facets<figref>1</figref> in lateral direction, or grown in the <11-20> direction, ie in the lateral direction along the plane of arrangement of the lower semiconductor layer <figref>2</figref>, By continuing the selective growth of the conflict the opposite facets <figref>1</figref> grown GaN-sections into one another, So that the grooves <figref>10</figref> be buried, and by further continuing of selective growth grows GaN in the direction crossing the disposition plane of the lower semiconductor layer <figref>2</figref> crosses, more specifically in a substantially vertical direction relative to the assembly plane of the lower semiconductor layer <figref>2</figref>, As Result is a selectively bred / buried Semiconductor layer <figref>3</figref> generated from GaN having a flat surface, the lower semiconductor layer <figref>2</figref> completely covered.
0060at this MOCVD method for forming the selectively grown / buried Semiconductor layer <figref>3</figref> is used, the substrate temperature to 1050 ° C set, and as a source gas, ammonia gas and trimethyl gallium gas used. More specifically, letting ammonia gas low flow rate, typically 10 l / min, flow, and leads trimethyl gallium gas with such a flow rate to that the Growth rate of the film about 4 microns / h becomes. Under these conditions, both Gases at atmospheric pressure react with each other.
0061On this way you can, as in <figref idrefs="S30">10B</figref> shown, GaN so grow, that it the grooves <figref>10</figref> completely buries, the selectively bred / buried Semiconductor layer <figref>3</figref> form, which has a flat surface.
0062the trained in this manner selectively bred / buried semiconductor layer <figref>3</figref> has been observed using a transmission electron microscope. The Result confirmed that the Dislocations "d" in the lower semiconductor layer <figref>2</figref> at the facets <figref>1</figref> are bent. Until the opposite of the facets <figref>1</figref> grown GaN-parts at the stage of the selective GaN growth for forming the selectively grown / buried semiconductor layer <figref>3</figref> together collide, the dislocations "d", by the lower semiconductor layer <figref>2</figref> in that direction substantially perpendicular to the c-axis extend, at the facets <figref>1</figref>. the pseudo-facets are that on the side surfaces of the grooves <figref>10</figref> artificially by etching are formed, bent and do not extend in the vertical direction but in the horizontal direction substantially along the disposition plane the lower semiconductor layer <figref>2</figref>, Ie along the main plane the substrate <figref>6</figref>,
0063If of the opposite facets <figref>1</figref> grown GaN Part collide with each other, the threading dislocations "d", are the from opposite facets <figref>1</figref> go out together connected and partially bent and extend upwardly in the Assembly plane of the lower semiconductor layer <figref>2</figref> crossing Direction, ie in the stacking direction. As a result, the defect density in the selectively grown / buried Semiconductor layer <figref>3</figref> to 1 × 10<sup>7</sup>/cm<sup>2</sup> reduced.
0064Accordingly occur in the selectively grown / buried Semiconductor layer <figref>3</figref> at the connection points of the threading dislocations regions <figref>4</figref> With high defect density, which the threading dislocations in high have density. In the other Parts are regions <figref>5</figref> formed with low defect density, having the dislocations in low density.
0065There the trained so selectively bred / buried Semiconductor layer <figref>3</figref> in direct contact with the lower Semiconductor layer <figref>2</figref> is without any intervening mask from a SiO<sub>2</sub>Layer, or the like. For the selective Growth is disposed, the deviation of the c-axis is between the selectively grown / buried Semiconductor layer <figref>3</figref> and the substrate <figref>6</figref> in a The range of 1 ° or fewer.
0066There in the manufacturing method according to this embodiment, the regions <figref>5</figref> With low defect density can be produced, the dislocations at a low have density, and the deviation in crystal orientation repressed is, can be a Semiconductor thin film <figref>40</figref> With extremely high quality produce, the terschicht selectively bred / buried semicon <figref>3</figref> contains. If to a semiconductor element or the semiconductor element main body of a A semiconductor device on the regions <figref>5</figref> low Defect density of the semiconductor thin film <figref>40</figref> arranges, Is it possible, the semiconductor element or the semiconductor device with an extremely high reliability to win.
0067As next is based on <figref idrefs="S31">11A</figref> to <figref idrefs="S31">11C</figref> and <figref idrefs="S32">12A</figref> and <figref idrefs="S32">12B</figref> a Another embodiment the method for producing a semiconductor thin film according to the invention.
0068at this embodiment is a substrate <figref>6</figref> made of C-surface sapphire, and on one major surface <figref>6a</figref> of substrate <figref>6</figref> is by means of the MOCVD method, a buffer layer <figref>7</figref> GaN formed to a thickness of 30 nm. In this MOCVD method is the substrate temperature set to 520 ° C, and as the source gas are trimethyl gallium gas ((CH<sub>3</sub>)<sub>3</sub>Ga) and ammonia gas (NH<sub>3</sub>) Used. On the buffer layer<figref>7</figref> becomes a Lower class <figref>12</figref> of GaN by the MOCVD method formed flat. In this MOCVD method, the substrate temperature to 1050 ° C set and uses the same source gas as described for the preparation of the buffer layer <figref>7</figref> was used.
0069the buffer layer <figref>7</figref>That a crystal layer near an amorphous layer which grew at the low temperature is acting as nuclei for the growth of the lower layer <figref>12</figref>, The lower layer<figref>12</figref>. consisting of crystals, has threading dislocations "d" in a density of about 1 × 10<sup>9</sup>/cm<sup>2</sup>That in the stacking direction extend.
0070Around on the flat lower layer <figref>12</figref> a lower semiconductor layer form, comprising the facets, as shown in <figref idrefs="S31">11B</figref> is shown, on the flat bottom layer <figref>12</figref> a mask <figref>13</figref> of SiO<sub>2</sub> to to a thickness of 5 microns for the generated selective growth of a semiconductor. The mask<figref>13</figref> for the selective Growing has a pattern in which, in the <11-20> direction extending strips parallel microns with a distance of 112 (width eg 5 microns, Distance 7 microns) located in the <1-100> direction are.
0071More accurate specifically, the mask <figref>13</figref> For selective growth is made by the on the entire surface lower layer <figref>12</figref> a SiO<sub>2</sub>-Layer at a substrate temperature of 450 ° C by the CVD method is and the SiO<sub>2</sub>Layer by photolithography and pattern etching is patterned, ie the SiO<sub>2</sub>layer with is coated a photoresist, the photoresist layer by Pattern exposure and development is patterned and the SiO<sub>2</sub>Layer using the patterned photoresist layer as an etching mask selectively etched is to strip-shaped openings <figref>13w</figref> produce.
0072The resulting substrate in which on the lower layer <figref>12</figref> the mask <figref>13</figref> For selective growth has been formed, is washed with acetone (CH<sub>3</sub>COCH<sub>3</sub>) And methanol (CH<sub>3</sub>OH) to give for about 10 seconds in dilute hydrochloric acid (HCl) or diluted Hydrofluoric acid (HF) immersed and cleaned with pure water. Furthermore, the substrate is sufficiently long in hydrofluoric acid (HF) dipped to SiO<sub>2</sub> completely remove the on the surface the lower layer <figref>12</figref> remains, through the openings <figref>13w</figref> of the mask <figref>13</figref> For selective growth outward is exposed, and is then cleaned with pure water.
0073On the lower layer <figref>2</figref>, Through the openings <figref>13w</figref> with the help the mask <figref>13</figref> For selective growth as a mask for the MOCVD method outwardly is exposed, can be a lower semiconductor layer <figref>2</figref> grow GaN high quality, to the lower semiconductor layer <figref>2</figref> the mask <figref>13</figref> covered. In the lower semiconductor layer <figref>2</figref> will strip <figref>11</figref> generated, each having rectangular cross section and run periodically in the <11-20> direction, and on both side surfaces each strip <figref>11</figref> are facets <figref>1</figref> educated, respectively compared to the C-surface the {1-101} facets, ie the assembly plane of the lower semiconductor layer <figref>2</figref>, around inclined about 69 ° are. In this MOCVD method used in the formation of the lower semiconductor layer<figref>2</figref> used is, the substrate temperature is set to 1050 ° C, and as the source gas Ammonia gas and trimethyl gallium gas are used. More specifically, allowed ammonia gas low flow rate, typically 10 l / min, flow, and leads Trimethyl gallium gas to a flow rate such that the growth rate of Film is about 4 microns / h becomes. can under these conditions both gases at atmospheric pressure react with each other.
0074The resulting substrate, wherein the lower semiconductor layer <figref>2</figref> on the lower layer <figref>12</figref> has been formed, is sufficiently long in hydrofluoric acid (HF) dipped to the mask <figref>13</figref> for selective growth by etching to complete remove. subsequently the substrate with acetone (CH<sub>3</sub>COCH<sub>3</sub>) And methanol (CH<sub>3</sub>OH) purified, for about 10 seconds in diluted hydrochloric acid (HCl) or dilute Hydrofluoric acid (HF) immersed and cleaned with pure water.
0075On the lower semiconductor layer <figref>2</figref>In which arranged the facets are allowed to by the MOCVD process a selectively bred / buried semiconductor layer <figref>3</figref> out GaN high quality after the MOCVD method selectively grow. In this MOCVD method is the substrate temperature set to 1050 ° C, and as a source gas Ammonia gas and trimethyl gallium gas are used. More specifically, allowed ammonia gas low flow rate, typically 10 l / min, flow, and leads trimethyl gallium gas with such a flow rate to that the Growth rate of the film about 4 microns / h becomes. Under these conditions, both Gases at atmospheric pressure react with each other. In such a MOCVD GaN grows selectively from the facets <figref>1</figref> tion in the lateral Rich, ie in the <11-20> direction along the Assembly plane of the lower semiconductor layer <figref>2</figref>, By the Continuing the selective growth collide the opposite of the facets <figref>1</figref> grown GaN parts into each other, to the grooves <figref>10</figref> between the strips <figref>11</figref> bury and by further continuing the selective growth to grow GaN in the direction perpendicular to the plane of arrangement of the lower semiconductor layer <figref>2</figref>, In this way, the selectively bred / buried semiconductor layer <figref>3</figref> out GaN, which has a flat surface has, formed so that they the lower semiconductor layer <figref>2</figref> completely covered.
0076Also for this embodiment confirmed located in observing the selectively grown / buried semiconductor layer <figref>2</figref> by the transmission electron microscope, that the penetration dislocations "d" at the facets <figref>1</figref> bent are. More specifically, in the stage of selective growth of GaN- for forming the selectively grown / buried Semiconductor layer <figref>3</figref>Until the of the opposite facets <figref>1</figref> grown GaN parts collide with each other, are the dislocations "d", the lower the Semiconductor layer <figref>12</figref> in the direction substantially perpendicular to the c-axis extend, at the facets <figref>1</figref> bent and extend im not in a vertical direction but in the horizontal direction substantially along the plane of arrangement of said semiconductor layer <figref>2</figref>, Then, as based on <figref idrefs="S30">10B</figref> described, of the opposite facets <figref>1</figref> grown GaN Part collide with each other, the opposite of the facets <figref>1</figref> outgoing dislocations "d" connected to each other and partially bent and extend upward in the direction crossing the disposition plane of the lower semiconductor layer <figref>2</figref> crosses, ie in the stacking direction. As a result, the defect density in the selectively grown / buried Semiconductor layer <figref>3</figref> to 1 × 10<sup>7</sup>/cm<sup>2</sup> reduced.
0077Accordingly occur in the selectively grown / buried Semiconductor layer <figref>3</figref> at the connection points of the threading dislocations regions <figref>4</figref> With high defect density, which the threading dislocations in high have density. In the other Parts are regions <figref>5</figref> formed with low defect density, having the dislocations in low density.
0078There the trained so selectively bred / buried Semiconductor layer <figref>3</figref> in direct contact with the lower Semiconductor layer <figref>2</figref> is without any intervening mask from a SiO<sub>2</sub>Layer, or the like. For the selective Growth is disposed, the deviation of the c-axis is between the selectively grown / buried Semiconductor layer <figref>3</figref> and the substrate <figref>6</figref> in a The range of 1 ° or fewer.
0079There in the manufacturing method according to this embodiment, the regions <figref>5</figref> With low defect density can be produced, the dislocations at a low have density, and the deviation in crystal orientation repressed is, can be a Semiconductor thin film <figref>40</figref> With extremely high quality produce, of the selectively bred / buried semiconductor layer <figref>3</figref> contains. If to a semiconductor element or the semiconductor element main body of a A semiconductor device on the regions <figref>5</figref> low Defect density of the semiconductor thin film <figref>40</figref> arranges, Is it possible, the semiconductor element or the semiconductor device with an extremely high reliability to win.
0080Among Using the semiconductor thin film <figref>40</figref> after the embodiments described above of <figref idrefs="S25">1</figref> to <figref idrefs="S28">8</figref> can be a semiconductor element according to the invention manufacture.
0081<figref idrefs="S33">13</figref> shows is a schematic sectional view of a semiconductor light emitting element embodying of the semiconductor element according to the invention. In this embodiment, the semiconductor light emitting element as a SCH (Separate Confinement Heterostructure) -Halbleiterlaser configured with a semiconductor laser element main body, the on the semiconductor thin film <figref>40</figref> of <figref idrefs="S25">2</figref> educated is or as a semiconductor layer <figref>8</figref> of the semiconductor thin film <figref>40</figref> of <figref idrefs="S27">6</figref> educated is.
0082In <figref idrefs="S33">13</figref> are Parts corresponding to parts of <figref idrefs="S25">2</figref> and <figref idrefs="S27">6</figref> correspond, provided with the same reference numerals, and a repetition of the corresponding description is omitted. In this embodiment, lets you to the selectively grown / buried Semiconductor layer <figref>3</figref> a first contacting <figref>21</figref>. a first cladding layer <figref>22</figref> and a first guide layer <figref>23</figref>, the each of a first conductivity type, for example n-type, are epitaxially grown in this order. Then, on the first guide layer <figref>23</figref> sequentially superimposed an active layer <figref>24</figref> and a layer <figref>25</figref>, the prevent deterioration, and further comprises a second guiding layer <figref>26</figref>. a second cladding layer <figref>27</figref> and a second contacting layer <figref>28</figref> arranged, each of a second conductivity type, for example p-type, are.
0083On the second contacting layer <figref>28</figref> an insulating layer <figref>29</figref> of SiO<sub>2</sub> arranged.
0084the in this way, the epitaxially grown layers of the Side of the insulating layer <figref>29</figref> etched partially until the first contacting layer <figref>21</figref> is exposed to a Ätzrille to form, and it is a first electrode <figref>31</figref> formed which with the exposed part of the first contacting layer <figref>21</figref> in ohmic contact is. A stripe-shaped opening<figref>29w</figref>, in the the insulating layer <figref>29</figref> is formed, a second electrode <figref>32</figref> formed, the exposed with the strip Part of the second contacting layer <figref>28</figref> in ohmic contact stands, in such a way that they in the direction perpendicular to the plane in <figref idrefs="S33">13</figref>, Ie in the direction of extension the facets <figref>1</figref> or strip <figref>11</figref> of the semiconductor thin film <figref>40</figref> runs.
0085As next An exemplary example of a method for producing the above semiconterelements described, as the A semiconductor laser element according to the invention configured. Following the same procedure as based on<figref idrefs="S29">9A</figref> to <figref idrefs="S29">9C</figref> and <figref idrefs="S30">10A</figref> and <figref idrefs="S30">10B</figref> described was, on a substrate <figref>6</figref> via a buffer layer <figref>7</figref> a lower semiconductor layer <figref>2</figref>, The facets <figref>1</figref> arranged are, and a selectively grown / buried Semiconductor layer <figref>3</figref> educated. Then you can on the flat surface of the selectively grown / buried Semiconductor layer <figref>3</figref> successively a first contacting <figref>21</figref> out with Si-doped n-GaN, having a thickness of 2 .mu.m, further comprising a first cladding layer <figref>22</figref> out a doped Si n-type AlGaN alloy crystal, the thickness of a of 0.5 mm, and a first guide layer <figref>23</figref> out with Si-doped n-GaN, having a thickness of 0.1 microns, is epitaxially grown.
0086On the first guide layer <figref>23</figref> allowed to a active layer <figref>24</figref> with multi-quantum well structure of a quantum well layer having a thickness of 3 nm, further comprising a barrier layer having a Thickness of 4 nm, and a GaInN alloy crystal layer having a Thickness of 4 nm epitaxially grown.
0087On the active layer <figref>24</figref> allowed to a layer <figref>25</figref> out AlGaN is epitaxially grown in preventing worsening, has a thickness of 20 nm. Then allowed to the layer<figref>25</figref> prevention a deterioration in succession a second guide layer <figref>26</figref> out doped with a p-type impurity Mg p-type GaN having a thickness of 0.1 microns, a second plating <figref>27</figref> of p-type AlGaN alloy crystal with a thickness of 0.5 microns and a second contacting layer <figref>28</figref> of p-type GaN alloy crystal with a thickness of 0.5 microns is epitaxially grow up.
0088at the epitaxial growth of the semiconductor layers <figref>21</figref> to <figref>28</figref> becomes a substrate temperature in the range of 800 ° C to 1000 ° C is set, and as the source gas for aluminum is trimethyl aluminum gas ((CH<sub>3</sub>)<sub>3</sub>Al) used as a gas for gallium is trimethyl gallium gas ((CH<sub>3</sub>)<sub>3</sub>Ga) used, as a source gas for Nitrogen, ammonia gas (NH<sub>3</sub>) Used as Source gas for Silicon is silane (SiH<sub>4</sub>) Is used, and as a source gas for Magnesium is bis (methylcyclopentadienyl) magnesium gas (MeCp<sub>2</sub>Mg) or bis (cyclopentadienyl) magnesium gas (Cp<sub>2</sub>Mg) used.
0089the insulating layer <figref>29</figref> is prepared by the CVD method, and the stripe-shaped opening <figref>29w</figref> becomes in the insulating layer <figref>29</figref> by photolithography and pattern etching produced.
0090In this embodiment the second electrode <figref>32</figref> in ohmic contact with the contacting layer <figref>28</figref> through the opening <figref>29w</figref> educated, However, it can also be by means of a lift-off (Lift-off method) getting produced. In this case, a photoresist layer produced by photolithography which has a pattern that the other serving as the part for forming the electrode portion covers. About the entire surface successively Ni and Au are deposited from the vapor phase, and the patterned resist layer is lifted, that is, removed to thereby to remove the Ni and Au, the patterned by vapor deposition on the is applied resist layer. In this manner, the second electrode<figref>32</figref> out Ni and Au formed.
0091In a portion of the stacked layers on which a first electrode <figref>31</figref> is to be formed are successively the insulating layer <figref>29</figref>That contacting layer <figref>28</figref>. the second cladding layer <figref>27</figref>, The second guide layer <figref>26</figref>. the layer <figref>25</figref> to prevent deterioration, the active layer <figref>24</figref>, The first guide layer <figref>23</figref> and the first cladding layer <figref>22</figref> selectively removed. Then selectively in sequence Ti, Al and Au from the vapor phase from the exposed portion of the contacting layer <figref>21</figref> n-type deposited to the first electrode <figref>31</figref> to build.
0092In In this way, the epitaxially grown semiconductor layers <figref>21</figref> to <figref>28</figref> is the density of the threading dislocations extremely low because the density of threading dislocations in the selectively grown / buried Semiconductor layer <figref>3</figref>As described above, extremely low and in particular is about the in <figref idrefs="S25">2</figref> or <figref idrefs="S27">6</figref> Regions shown <figref>5</figref> With formed lower defect density regions with low defect density are, so that accordingly in this embodiment in a position above the region with lower defect density, that is, substantially over the strip <figref>11</figref>, A laser resonator is formed.
0093More accurate specifically, in this embodiment, is in the active region <figref>24</figref> in a position below the Section in which the second electrode on the stripe-shaped opening <figref>29w</figref> With the contacting layer <figref>28</figref> is in contact, restrictive current injection region formed to where a laser resonator form. Therefore on the strip <figref>11</figref> the opening <figref>29w</figref> of the insulating layer <figref>29</figref> formed, the contact part of the the second electrode <figref>32</figref> with the contacting layer <figref>28</figref> equivalent to is.
0094After the formation of the electrodes <figref>31</figref> and <figref>32</figref> is the Semiconductor element separated by breaking to the length of the to bring the laser resonator to a specific value. The parting planes form mirror surfaces, the end surfaces of the constitute the resonator.
0095If in the semiconductor laser having the above described configuration, between the first and the second electrode <figref>31</figref> or. <figref>32</figref> a Forward current flows, flows this in the active layer <figref>24</figref> with the result that by Recombination of electrons and positive holes light emission takes place.
0096There at least the working range of the semiconductor light emitting element, that is, in this embodiment, of the semiconductor laser, is formed in the region in which the dislocations have low density, and also the deviation is avoided in the crystal orientation, it is possible to reduce threshold current and the driving voltage and thereby the deterioration of the properties that enlarged by the threshold current and the increased driving voltage caused to reduce. Consequently, the life span of the semiconductor laser can be increased in this embodiment.
0097<figref idrefs="S34">14</figref> shows is a schematic sectional view of another embodiment of the semiconductor element according to the invention. In this embodiment, is the semiconductor element configured as the semiconductor laser having a SCH structure, the the on the in each <figref idrefs="S26">3</figref> and <figref idrefs="S28">7</figref> illustrated Semiconductor thin film <figref>40</figref> according to the invention is trained.
0098Of the Semiconductor thin film <figref>40</figref> of Semiconductor laser, in this embodiment in the same Compounds are prepared, such as that based on <figref idrefs="S31">11A</figref> to <figref idrefs="S31">11C</figref> and <figref idrefs="S32">12A</figref> and <figref idrefs="S32">12B</figref> described has been. The semiconductor laser main body of the semiconductor laser can have the same structure as based on <figref idrefs="S33">13</figref> described was, and the method for its production can also the be the same, as based on <figref idrefs="S33">13</figref> described has been.
0099In <figref idrefs="S34">14</figref> are those parts which correspond to parts of <figref idrefs="S26">3</figref>. <figref idrefs="S28">7</figref> and <figref idrefs="S33">13</figref> correspond, provided with the same reference numerals, and a repetition the description is omitted.
0100There Also in this embodiment, similar to in the semiconductor laser of <figref idrefs="S33">13</figref>, at least the work area in a region with a low density of dislocations is formed and also the deviation is avoided in the crystal orientation may be the reduced threshold current and the driving voltage and thus the through increased Threshold current and drive voltage caused deterioration the properties can be kept low. Consequently, the Lifetime of the semiconductor laser according to this embodiment extended will.
0101It Note that the present invention not limited to the embodiments described above limited is. It is further to be noted that various variations possible are, without this being the technical idea of departing from the invention. When training the stripe <figref>11</figref>, Ie the facet <figref>1</figref>By selectively Growth in accordance with the <figref idrefs="S31">11A</figref> to <figref idrefs="S31">11C</figref> Steps shown are the facets <figref>1</figref> eg to about 58 ° relative to the C-surface the {11-22} facets, ie the assembly plane of the lower semiconductor layer <figref>2</figref>Inclined, by the direction of extension of the strips <figref>11</figref> in the <1-100> direction is chosen. On Thus, the extending direction of the facets <figref>1</figref> and Thus, the extension direction of the regions <figref>4</figref> with high Defect density and the regions <figref>5</figref> low defect density selected to be that they one of the directions along different crystal axes equivalent.
0102What the individual semiconductor layers <figref>21</figref> to <figref>28</figref> of <figref idrefs="S33">13</figref> and <figref idrefs="S34">14</figref> relates, then the conductivity type opposite to described may be reversed, and the composition may be differ from that described. In other words, the present Invention can be applied to a semiconductor element, wherein the above-described semiconductor layers of other suitable made semiconductors.
0103According to the present Invention, however, it is particularly effective when each of the semiconductor layers of a compound semiconductor composed of a group III nitride is assembled, the nitrogen (N) and at least one kind contains a group III element, the selected from a group is consisting of Al, Ga, B and In.
0104During the A semiconductor laser in each of the above embodiments, a SCH structure has, in between the first and the second guide layer <figref>23</figref> and <figref>26</figref> the active layer <figref>24</figref> is disposed, the present Invention also relates to a semiconductor light emitting element, such as a semiconductor laser or a light emitting diode used, will have a different structure, such as a DH (double hetero) structure without elites.
0105The Semiconductor element of the present invention is not limited to a light emitting Semiconductor element is limited, but can also be another element, such as a FET (Field Effect Transistor).
0106On Semiconductor element according to the invention may be configured as a single semiconductor element described above comprises semiconductor element or an integrated circuit system, in which a plurality of semiconductor elements on a common Semiconductor thin film are formed which according to the present Invention is manufactured.
0107In in this case, each of the <figref idrefs="S25">1</figref> to <figref idrefs="S28">8</figref> illustrated Semiconductor thin films after each of the with in conjunction <figref idrefs="S29">9A</figref> to <figref idrefs="S32">12B</figref> The method described may be made, and each of the semiconductor elements such as semiconductor light emitting elements with in <figref idrefs="S33">13</figref> and <figref idrefs="S34">14</figref> Illustrated structures can according to any of based on <figref idrefs="S33">13</figref> and <figref idrefs="S34">14</figref> described be prepared method.
0108By the use of the semiconductor thin film or the semiconductor element, as described above, can be a producing semiconductor device with excellent properties.
0109at the manufacture of a semiconductor integrated circuit system must facets <figref>1</figref> and accordingly the Regions <figref>5</figref> With low defect density in the common semiconductor thin film <figref>40</figref> not necessarily be arranged at equal intervals.
0110While each semiconductor layer by the MOCVD method, or a method grow up with halide vapor deposition in the above embodiments may be, they may be distributed by some other method of Vapor deposition, for example by a MBE (Molecular Beam Epitaxy) method be grown. The semiconductor layers<figref>21</figref> to <figref>28</figref> can eg are generated according to the MBE method or the halide method.
0111There in the semiconductor thin film, the semiconductor element and the semiconductor device and the method for their preparation according to the invention as described above, in the selectively grown / buried semiconductor layer <figref>3</figref> the dislocations are formed in such a manner that each of the threading dislocations bent extends from one of said facets, with another of the connected dislocations is that from the opposite copy of the facet <figref>1</figref> along the epitaxial growth from the facets <figref>1</figref> runs and extends from the juncture of curved, it is possible that Defect density, at least a work area of the main body of the Semiconductor element, to reduce significantly, by the operating range is arranged in a region with low defect density, and since the selectively grown / buried semiconductor layer <figref>3</figref> not by selectively bred Mask of SiO<sub>2</sub> or the like. is cultured the deviation in crystal orientation to a value of 0.1 ° or be less lowered. As a result, according to the invention, a semiconductor thin film with high quality and thus a semiconductor element and a semiconductor device with good properties, high reliability and extended Life available are provided by this semiconductor thin film is used.
10 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10
25 members in 9 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 33630798 | Japan | – | |
| 33630798 | Japan | A |
Members25
| Document | Office | Kind | |
|---|---|---|---|
| JPH1044178A | Japan | A | |
| CA2247314A1 | Canada | A1 | |
| WO9829228A1 | World Intellectual Property Organization (WIPO) | A1 | |
| AU5339898A | Australia | A | |
| EP0890423A1 | European Patent Office (EPO) | A1 | |
| EP1005068A2 | European Patent Office (EPO) | A2 | |
| JP2000164929A | Japan | A | |
| KR20000035610A | Republic of Korea | A | |
| EP1005068A3 | European Patent Office (EPO) | A3 | |
| TW426989B | Taiwan Province of China | B | |
| EP0890423A4 | European Patent Office (EPO) | A4 | |
| US2002064641A1 | United States of America | A1 | |
| US6399189B1 | United States of America | B1 | |
| US2002115267A1 | United States of America | A1 | |
| US2003044594A1 | United States of America | A1 | |
| US6576533B2 | United States of America | B2 | |
| US2003168763A1 | United States of America | A1 | |
| US6620495B1 | United States of America | B1 | |
| EP1005068B1 | European Patent Office (EPO) | B1 | |
| DE69918643D1 | Germany | D1 | |
| DE69918643T2This record | Germany | T2 | |
| US7048879B2 | United States of America | B2 | |
| KR100700677B1 | Republic of Korea | B1 | |
| JP4032538B2 | Japan | B2 | |
| JP4299375B2 | Japan | B2 |
2 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Willingness to grant licences declared (paragraph 23)8320 | 8320 | |
| No opposition during term of oppositionOpposition8364 | 8364 |
Numbers
- Publication
- 69918643
- Application
- 69918643
Titles2
- German
- GaN Film mit reduzierter Verspannungsdichte und Herstellungsverfahren
- English
- GaN film with reduced strain density and manufacturing processes
Classification
- CPC, 24
- C30B25/02
- H01S5/30
- B29C43/222
- B29C43/28
- B29C59/005
- B29C59/04
- B29C59/046
- B32B37/153
- B32B38/06
- B32B2305/022
- B32B2457/20
- C30B25/18
- C30B29/403
- C30B29/406
- H10H20/0137
- H10H20/01335
- H10H20/8215
- H10P14/2901
- H10P14/2925
- H10P14/2921
- H10P14/3248
- H10P14/3216
- H10P14/3416
- H10P14/27
- IPC, 20
- B29C43 22
- B29C43 28
- B29C59 00
- B29C59 04
- B32B37 15
- B32B38 04
- B32B38 06
- C30B25 02
- C30B25 18
- H01L33 00
- H01L33 02
- H01L33 06
- H01L33 12
- H01L33 32
- H01L33 34
- H01S5 00
- H01S5 30
- H01S5 323
- H01S5 343
- H10P14 24
