Voltage-clamped power accumulation-mode MOSFET

The invention relates to power enhancement field effect transistors and, more particularly, to power enhancement field effect transistors enabling greater voltage limiting as described in the preamble of claim 1.

One such enhancement FET is from T. Syau et al., "Comparison of Ultralow Specific On-Resistance UMOFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOFETs, IEEE Electron Device Letters, Vol. 41, No. 5, May 1994 , Pp. 800-808.

Enhancement field effect transistors, sometimes referred to as "ACCUFETs", are trench MOSFETs that have no body region and thus no PN junctions. The region between the trench gates, sometimes referred to as a "mesa", is relatively narrow (eg, 0.5 to 4.0 μm wide) and the gate material (eg, polysilicon) is doped so that, due to its Work function of the entire mesa area depleted, much like a junction FET (JFET). The current path extends between a source region in the upper region of the mesa and a drain region in the lower region of the substrate. The trenches are usually completely formed in an epitaxial layer grown on the substrate.

1 shows a cross-section through a typical ACCUFET 10. The trench gates 11 are etched into a silicon material 12 that includes an N-epitaxial layer 13 grown on an N + substrate 14. The trench gates 11 define two cells 10A and 10B. An N + Source 15 is located on the Mesa between the Gates 11. A metal layer 16 extends over the source regions, and a power source 17 and a load 18 are connected between the N + source 15 and the N + substrate 14, which acts as a drain.

The ACCUFET 10 is turned off when the gate voltage has the same value as the source voltage (ie VGS = 0). As VGS is increased, the depletion zones contract around the gates (shown by dashed lines) and open a current path between source and drain. If VG5 is increased even further, the depletion zones continue to contract until enrichment zones form next to the trenches, which increase the channel conductivity and further reduce the on-resistance of the device.

This operation is shown in Figs. 2A, 2B and 2C, with Fig. 2A showing the ACCUFET 10 in the off state, Fig. 2B the same in partially on and Fig. 2C in the fully on state; the enrichment zones are marked with the number 19. In Figs. 2B and 2C, the arrows represent the flow of electrons from the source to the drain.

The initially mentioned ACCUFET differs slightly from the structure shown in FIG. On one side of the trench, there is additional P-diffusion under the N + source regions under the contacts, to constrict the current between the source and drain to the trench zone.

Further information on ACCUFETS can be found in U.S. Patent No. 4,903,189 to Ngo et al .; BJ Baliga et al., "The Accumulation-Mode Field-Effect Transistor A New Ultralow On-Resistance MOSFET", and IEEE Electron Device Letters, Vol. 13, No. 8, August 1992, pages 427-429. Each of these documents is hereby fully inclusive, if so referred to.

ACCUFETs can be manufactured with very high cell density and very low on-resistance. Despite these advantages, ACCUFET has not yet been able to find much use in the field of power semiconductors for a number of reasons. One of the main reasons is that he is unable to cope with high voltages when switched off.

The problem is illustrated in FIGS. 3A and 5B which show the oxide layers 11A adjacent to the gates 11A. In Fig. 3A it can be seen how the ACCUFET 10 is connected to an inductor 30. The notations t 0, t 1, t 2, t 3 and t 2 are as follows. and t & sub4; The successive times in the turn-off operation of the ACCUFET 10 are shown in FIG. 3A. The broken lines in FIG. 3A are the edges of the expanding depletion regions at the times t 0, t 1, t 2, t 3. and t & sub4 ;. Fig. 3B shows the strength of the electric field in the gate oxide layer 11A and the epitaxial layer 13 at times t 0, t 1, t 2, t 3. and t & sub4; at. As shown, the electric field is in the gate oxide layer 11A and part of the epitaxial layer 13 at the time t0 at which VGS begins to decrease. At the times t & sub1; and t & sub2; For example, the field strength in the gate oxide layer 111A has slightly increased, but part of the increase is absorbed by the epitaxial layer 13. At time t & sub2; however, the electric field has reached the interface between epitaxial layer 13 and N + substrate 14. Since the N + substrate 14 is heavily doped, it can not receive a large electric field, and therefore all further field increases must be accommodated in the limited space of gate oxide film 11A and epitaxial layer 13. This means that the electric field in the gate oxide layer 11A begins to increase more rapidly as the VGS decreases. Eventually, if not limited, then the field strength increase may destroy the gate oxide layer 11A. Such a case is shown in Fig. 3B for the time t & sub4; shown. If the gate oxide layer destroyed, then the device is usually not reparable.

It often happens that a load (such as the load 30) has an induction coil. Thus, it is also inevitable that arise when turning on and off in the power lines voltage spikes. The inability of the ACCUFET to handle such voltage spikes has meant that it is used in the field of power MOSFET only to a very limited extent.

The push-pull half-bridge circuit 40 of FIG. 4A illustrates the problem that arises when ACCUFETs are used in conjunction with an inductive load. The half-bridge circuit 40 includes a high-side ACCUFET 41 and a low-side ACCUFET 42. For example, they drive a motor coil 43 at. The two ACCUFETs 41 and 42 are connected in series between a battery voltage Vbatt and ground. From Fig. 4B, the voltages (VGS) at the gate oxides of the ACCUFETs 41 and 42 and the voltage V & sub0; to see at the output of the half-bridge circuit. It is assumed that V & sub0; is low at the start point, ie that the high-side ACCUFET 41 is turned off and the low-side ACCUFET 42 is turned on. When the ACCUFET 42 is turned on, some current will typically flow through the ACCUFET 42 and coil 43. In this case, the gate of ACCUFET 42 is coupled to Vbatt and the gate of ACCUFET 41 is tied to the same voltage as V 0. coupled, so that the voltage VGS in the ACCUFET 41 is zero.

To V & sub0; from low to high, the low-side ACCUFET 42 is turned off and then the high-side ACCUFET 41 is turned on. However, both ACCUFETs must not be switched on at the same time, otherwise a direct current path from Vbatt to ground results, which leads to a high current value and most probably to a destruction of both components. Therefore, the ACCUFET 42 is turned on at time T & sub1; turned off by its gate voltage of Vbatt is grounded. However, the current flowing through the coil 43 resists the sudden shutdown, and therefore V & sub0; rapidly to a value greater than Vbatt, as can be seen in the upper curve of FIG. 4B. V0 increases until ACCUFET 42 is either breached or destroyed. At the same time, the voltage VGS in the ACCUFET 41 decreases equally rapidly (its source region is more positively charged than its gate). It is most likely that the gate oxide of the ACCUFET 41 will be destroyed in this case before the ACCUFET 42 becomes conductive, attempting to control the output voltage V o. to limit.

A similar procedure to that shown in Figures 4A-4B results in virtually all cases where an ACCUFET is used to switch currents through an inductive load. For further explanation, reference is made to a MOSFET described in EP-A-0583022 in which a heavily doped region is formed between two trenches and in the center of which a curved PN junction is defined such that the point at which the MOSFET blows avalanche is moved away from the trench corners in the mass of the semiconductor material in order to mitigate the injection of hot carriers into the gate insulation layer.

The invention is therefore based on the object of specifying a component which has the outstanding cell density and the on-resistance of an ACCUFET, and yet can switch an inductive load or reliable voltage peaks in a limited amount, in particular without damaging the trench gate cope.

The object is achieved according to the characterizing part of claim 1.

The ACCUFET of the present invention includes a plurality of trench gate-limited cells and is selected conductivity semiconductor material. Each of the trench gates is made of conductive gate material, in particular polysilicon, and an insulating layer, in particular silicon dioxide, which separates the conductive gate material from the semiconductor material in each cell. In order to limit the electric field occurring in the gate oxide layer, a protection zone is formed with a conductivity opposite to the semiconductor material in the cell. This creates a PN junction that has the effect of a protection diode that runs parallel to the current path through the ACCUFET cell. The doping level and location of the PN junction are set to provide a breakdown voltage for the diode which prevents the voltage on the gate oxide layer from rising to a level that would destroy or damage the gate oxide layer. The diode should also limit the maximum value of the electric field in the silicon in the gate environment and thus keep it as low as possible, so that the emergence of hot charge carriers is minimized or prevented.

In the preferred embodiment, the guard zone is formed in an adjacent cell having a conductivity opposite to the ACCUFET cells. The cells may be in the form of longitudinal stripes or of hexagonal, square, polygonal or other figures. The guard zones are preferably formed as a repeating pattern on the ACCUFET to provide a guard zone for a selected number of ACCUFET cells, respectively.

Embodiments of the invention will now be described by way of example and with reference to the accompanying drawings. These show:

Fig. 1 is a cross section of a conventional enhancement MOSFET (ACCUFET).

2A shows an ACCUFET in the off state; FIG. 2B shows a partially activated ACCUFET; FIG. and FIG. 2C shows a fully activated ACCUFET.

Fig. 3A shows the changes in the depletion zone when the ACCUFET transitions from the on to the off state.

Figure 3B is a schematic representation of the strength of the electric field in the gate oxide and epitaxial layers of the ACCUFET of Figure 3A as it transitions from on to off states.

4A shows a push-pull half-bridge circuit with two ACCUFETs connected to an inductive load.

4B are diagrams showing the voltages at the output of the bridge circuit and over the gate oxides of the ACCUFETs shown in FIG. 4A.

5A shows a cross section of a voltage-limited ACCUFET according to the invention.

Fig. 5B is a diagram of an equivalent circuit diagram for the ACCUFET shown in Fig. 5A.

Figures 6A and 6B are three-dimensional cross-sections of alternative ACCUFET structures according to the invention, with Figure 6A representing a square and Figure 6B a striped cell structure.

Fig. 7 is a plan view of the ACCUFET shown in Fig. 6B.

Fig. 8 shows an alternative embodiment according to the invention in which the gate trenches extend into the heavily doped substrate.

FIGS. 9A-9E illustrate the process steps in the manufacture of the ACCUFET illustrated in FIG. 5A.

An inventive ACCUFET is shown in FIG. 5A. The ACCUFET 50 has the trench gates 51A and 51B formed in an epitaxial N-layer grown on the surface of an N + substrate 53.

Gates 51A and 51B are insulated from epitaxial layer 52 by gate oxide layers 54A and 54B, respectively. A flat N + region 55 on the surface of the epitaxial layer 52 contacts a metal layer 56. The epitaxial N-layer 52 is typically at a concentration of 1 x 10¹ & sup4; - 1 x 10¹ & sup5; cm &³ doped. The gates 51A and 51B are preferably made of boron in a concentration of 8 x 10¹ & sup8; - 5 x 10¹ & sup9; cm &³ doped polysilicon. Typically, the gate oxide layers 54A and 54B are 90-1000 Å thick and the gap between gate 51A and gate 51B is about 1.0 μm, but may vary between 0.5 and 4.0 μm.

The N + substrate 53 serves the ACCUFET 50 as a drain region and can be contacted from below. Alternatively, instead of the N + substrate, a buried N + layer may be used as the drain region, wherein the contacting from above, e.g. B. with the help of this N + sinker area and an overhead contact, would be possible. As protection for the gate oxide layers 54A and 54B, a deep P + region 57 is formed in the epitaxial layer 52, thus providing a PN junction that functions like a diode (symbolically represented as diode D1).

Fig. 5B shows an equivalent circuit for the ACCUFET shown in Fig. 5A. As shown, the diode D1 is connected in parallel with the ACCUFET 50 main current path. It should be noted that the integration of the diode D1 in the ACCUFET 50 causes a different result than when only one external diode is connected in parallel to the ACCUFET. Integrating the diode avoids a series inductance in the diode (occurring in the discrete, multi-chip or PCB version) so that the diode can almost instantaneously limit the internal voltages within the ACCUFET (no overshoot). In addition, the diodes can be distributed over the entire component, so that a uniform boundary arises.

As stated above, the voltages at the gates 51A and 51B and the source (N + zone 55) are substantially identical when the MOSFET 50 is turned off. Since the N + region 55 is connected to the deep P + region 57 via the metal layer 56, the voltages across the gate oxides 54A and 54B can not be greater than at the diode D1 when the MOSFET 50 is turned off. If the diode D1 is switched in the reverse direction, then the voltage across the diode D1 is limited to its breakdown voltage; if diode D1 is operated in the forward direction, then the voltage drop across diode D1 is limited to the normal diode voltage (typically about 0.7 V).

The breakdown voltage of the diode D1 is determined by the doping concentrations of the deep P + region 57, the epitaxial N-layer 52 and the N + substrate 53 and the separation between the PN junction 58 and the interface between epitaxial N-layer 52 and the N + substrate 53 are controlled accordingly. In a normal ACCUFET, the doping concentration of the N-type epitaxial layer 52 is in the range of 10.sup.14 -10.sup.15 cm.sup.-5. cm &³ for the ACCUFET to be turned off. The N + substrate 53 has a resistivity of 3 mΩ-cm and the deep P + region 57 has a sheet resistance of 40-150 Ω /. The epitaxial N layer 52 is 2.5-5.0 μm thick, but the net height from the bottom of the deep P + region 57 to the N + substrate 53 is 0.3 to 1.5 μm.

Figures 6A and 6B are three-dimensional cross sections of the alternative ACCUFET structures according to this invention. The ACCUFET 60 shown in FIG. 6A consists of a pattern of square or rectangular cells, one of which forms the deep P + zone 61. In the ACCUFET 62 shown in FIG. 6B, the cells are striped, with one of the cells forming the deep P + region 63.

Fig. 7 is a plan view of the MOSFET 62 shown in Fig. 6B, with the cross section of Fig. 6B being indicated as VI B - VI B. As indicated, a metallic contact layer (not shown) forms a number of contacts to the N + source regions 64 and 65 and to the P + region 63. An N + region 67 formed around the structure serves to form the N + substrate to contact. Alternatively, the N + substrate could also be contacted from the back.

FIG. 8 shows an alternative embodiment with a MOSFET 80 in which the trench gates 81 extend into the N + substrate 82. Since the N + substrate 82 can not sustain a significant voltage differential, the gate oxide layers 85 are exposed to the overall voltage on the ACCUFET when it is turned off. In other words, a lightly doped epitaxial N-layer is not present which could absorb some of the voltage drop across the device. Therefore, the doping concentrations of the P + zone 83 and the N + substrate 82 must be carefully set so that the diode D2 breaks down before the gate oxide layer 85 is destroyed. According to industry standards, the gate oxide layer should not be exposed to a voltage greater than 4 mV / cm by thickness of the oxide layer expressed in centimeters. For example, a gate oxide layer having a thickness of 400 Å is destroyed at about 32V. Therefore, the breakdown voltage of the diode D2 should be about 16V. If the gate oxide layer is 175 .ANG. Thick, a voltage limit of about 8 V is needed.

Although there are numerous fabrication methods for an ACCUFET according to the present invention, FIGS. 9A-9E show an example of the fabrication of ACCUFET 50 shown in FIG. 5A.

The starting point is a conventional N + substrate 53 on which an epitaxial N-layer 52 is grown using known techniques, see Fig. 9A.

A thick oxide layer 90 is grown, masked and etched, and a thin oxide layer 91 is grown on the surface of the structure where the deep P + region 57 is to be formed. Then, the deep P + region 57 is implanted through the thin oxide layer 91, with a doping of 1 × 10¹ & sup4; to 7 x 10¹ & sup5; cm & supmin; ² and an energy of 60-100 keV. The resulting structure is shown in Fig. 9B. Then the oxide layers 90 and 91 are removed.

In another version of the process, a thick oxide layer 92 is grown and removed by photomask technique, but not over the deep P + region 57. Then, a thin oxide layer 93 is grown. This thin oxide layer 93 is masked and removed at the locations of the structure where the trenches are to be formed, see Fig. 9C. The trenches are then masked and etched using known reactive ion or dry plasma etching techniques. Subsequently, the trenches are oxidized, forming the gate oxide layers 54A and 54B. Furthermore, polysilicon is introduced into the trench until it is completely filled.

Now, the polysilicon is doped with phosphorus by POCl3, preseparation or ion implantation with a doping of 5 × 10¹³ to 6 <10¹ & sup5; cm &² and an energy of 60 KeV, producing a sheet resistance of 20-70 Ω / □. For a P-channel device, the polysilicon is doped with boron using ion implantation to give a sheet resistance of roughly 40-120 Ω / □. Then, the polysilicon is etched back until it is level with the top of the trench, except where it is protected by a mask and then contacted with metal.

Now, the N + source region 55 is inserted using a mask and an arsenic ion implantation (or a boron ion implantation, if it is a P-channel device) with a doping of 5 · 10¹ & sup4; to 1 x 10¹ & sup6; cm &² at 20-100 KeV. The resulting structure is shown in Fig. 9D.

A thin oxide layer is grown thermally. Boron phosphosilicate glass (BPSG) is then applied to the structure surface. The BPSG is heated briefly to about 850 ° -950 ° C to allow it to flow well and smooth the surface of the chip. Vias are etched into the oxide and BPSG layers and the metal layer 56 is deposited. Through the contact holes, contacts are formed to the N + source region 55 and to the deep P + region 57. The result is the ACCUFET 50 shown in FIG. 9E. The chip is then passivated with SiN or BPSG at low temperature and masked connection windows are etched to make the bonds.

Specific embodiments of this invention have been described. These are to be understood as examples only and not as any limitation.