Manufacturing method for semiconductor device having capacitor

The present invention relates to a semiconductor device having a capacitor utilizing a dielectric layer and its manufacturing method.

Recently, in the trend of higher speed and lower power consumption of semiconductor devices such as microcomputers and digital signal processors, the electronic applications for consumers are becoming more and more efficient, while the foreign emissions generated by these applications, such as the electromagnetic noise, pose serious problems. Consequently, measures against this foreign mission have been demanded not only in electronic applications but also in the semiconductor devices used in them. The most effective measure against external emissions in a semiconductor device is to install a large capacitance capacitor between the bias line and the ground line, with a capacitor connected outside the semiconductor device.

On the other hand, in recent years, a simple-structure, non-volatile RAM memory having a capacitor using a ferroelectric layer and a dynamic random access memory using a capacitor made of a high-dielectric-constant dielectric layer as a holding capacitor have been developed.

A normal semiconductor device with capacitor will be specifically explained below. FIG. 1 is a partial sectional view of a representative semiconductor device. In Fig. 1 Reference numeral 1 denotes a semiconductor substrate, and the integrated circuit formed on the semiconductor substrate 1 is omitted from the drawing. On the semiconductor substrate 1, an insulating layer 2 is formed. On this insulating layer 2 made of aluminum or an aluminum alloy metal compounds 3, 4, 5 are formed. On these metal compounds 3, 4, 5, an insulating layer 6 is formed, wherein in this insulating layer 6, a lower electrode 9, a ferroelectric layer 10 and an upper electrode 11 are formed, and the lower electrode 9 through a contact opening 8 with the metal compound 4 and the upper electrode 10 is connected to the metal interconnection 3 through a contact opening 7.

In Fig. 1, assuming that the metal interconnection 3 is the bias line Vss and the metal interconnection 4 is the bias line Vdd, a capacitor having the lower electrode 9, a ferroelectric layer 10 and the upper electrode 11 is inserted between the bias line Vss and the bias line Vdd.

A manufacturing method of the conventional semiconductor device with capacitor shown in FIG. 1 will be described below. On the insulating layer 2 of the semiconductor substrate 1 on which the circuits and others are formed, a metallic layer of aluminum or an aluminum alloy is formed by sputtering or by another method. This metallic layer is etched by ordinary photoetching, and metal interconnections 3, 4, 5 are formed. Consequently, the insulating layer 6 is formed on the entire surface of the semiconductor substrate 1 by CVD method, wherein the contact openings 7, 8 are formed in specific areas of this insulating layer 6 by photoetching. Subsequently, a metal layer is formed on the insulating layer 6, which is photoetched to form the lower electrode 9. The ferroelectric layer 10 is formed by sputtering including the upper part of the lower electrode 9. After removing the ferroelectric layer 10 in the contact hole 7, an aluminum layer or layer of an aluminum alloy is formed, and the upper electrode 11 is formed by photoetching.

In this conventional semiconductor device with capacitor, it is necessary that the material of the lower electrode 9 should not react with the metallic compound 4 during the heat treatment of the ferroelectric layer 10, since the ferroelectric layer 10 in a contact state of the lower electrode 9 with the metallic compound 4 of the integrated circuit, and that insulating layer 6 and ferroelectric layer 10 should adhere firmly to each other. In fact, it is difficult to select the material that meets these conditions. For example, if aluminum is used for the metal compounds 3, 4, 5 and the bottom electrode 9 as well, matching to their mutual relationship and adhesion to the insulating layer 6 is excellent, but if oxidic ferroelectric material is used, for example, BaTiO & sub3; and PZT is used as the ferroelectric layer 10, aluminum and the ferroelectric layer 10 react with each other, and hence the capacitance of the capacitor changes.

Besides, in such a conventional semiconductor device with a capacitor, the metal interconnections 3, 4, 5 are already formed when the ferroelectric layer 10 is formed, and a part of the metal interconnections 3, 4, 5 is in contact with the diffusion layer (shown in FIG. 1 not shown) of the semiconductor substrate 1, and therefore, the ferroelectric layer 10 can not be treated at a high temperature. That is, when the metal interconnections 3, 4, 5 are made of aluminum and the semiconductor substrate 1 is a silicon substrate, when heated to 450 ° C or higher, aluminum may tip into the diffusion layer to penetrate the diffusion layer.

In addition, in a conventional semiconductor device with capacitor, after the contact holes 7 and 8 are simultaneously formed on the insulating layer 6, the lower electrode 9 and then the ferroelectric layer 10 are formed. Therefore, during the heat treatment of the ferroelectric layer 10, the reaction product due to the reaction between the ferroelectric layer 10 and the metal compound 3 is formed on the bottom side of the contact hole 7. This reaction product also remains when the ferroelectric layer 10 is removed, which may result in a contact failure between the metal interconnection 3 and the upper electrode 11.

On the other hand, in the method where first the contact hole 8 and then the contact hole 7 is formed after the ferroelectric layer 10 is formed, both the ferroelectric layer 10 and the insulating layer 6 must be etched, but the etching liquid has both etching conditions fulfilled, deviates and the procedure is complicated.

Capacitors according to the preamble of claim 1 are known from EP-A-192 989.

Therefore, it is an essential object of the invention to propose a semiconductor device having a capacitor with high reliability. Another object of the invention is to introduce a method of manufacturing the semiconductor device without degrading the circuit formed on the substrate.

According to the present invention, a semiconductor device is provided

with an integrated circuit;

an insulating layer formed on the integrated circuit;

a capacitor comprising a lower electrode consisting of a conductive layer formed on the insulating layer, a dielectric layer formed on at least the lower electrode, and an upper electrode consisting of a conductive layer formed on the dielectric layer is formed;

a protective layer formed on the capacitor, the protective layer having at least one contact opening extending to the lower electrode and having at least one contact opening extending to the upper electrode;

and metal interconnections connected to the upper electrode and the lower electrode through the contact holes;

characterized, that the dielectric layer is a ferroelectric layer, and that either the upper electrode or the lower electrode is connected to a bias line of the integrated circuit and the other electrode is connected to a ground line of the integrated circuit, so as to reduce foreign missions, indam these are derived to the grounding, and that at least the one contact opening, which is arranged to the upper electrode is disposed at a portion of the upper electrode, which does not cover the lower electrode.

According to this structure, since the capacitor is formed in a state independent of the integrated circuit, the lower electrode can be made of an optimum material selected with respect to the dielectric layer below the lower electrode. Therefore, a favorable capacitor can be formed whose capacitance fluctuation is small.

Besides, the dielectric layer can be heated to a sufficiently high temperature because the manufacturing process of the capacitor including the heat treatment of the dielectric layer is performed in a state where the integrated circuit on the substrate is already formed but the metal interconnections are not yet formed, and a dielectric layer having a high dielectric constant can be formed.

In addition, in the structure according to the invention, the first contact hole provided in the insulating layer formed on the substrate and the second contact hole provided on the insulating layer formed to protect the capacitor may be formed, the metal interconnections directly after the formation of the contact holes can be formed, the inside of which is not contaminated, and a favorable electrical contact can be easily realized. Before forming the first contact hole and the second contact hole, the dielectric layer is patterned, and therefore, the contact holes can be formed only by etching the nitride layer or oxide layer used in the ordinary semiconductor device, so that the manufacturing process is not complicated.

Brief description of the accompanying drawings

In the drawings show

Fig. 1 is a partial sectional view showing the structure of essential parts of a conventional semiconductor device with capacitor;

Fig. 2 is a partial sectional view showing the structure of essential parts of a semiconductor device with capacitor in Example 1 of the application;

Fig. 3 is a partial sectional view showing the structure of the capacitor of a semiconductor device in Example 2 of the application, in which the end of the upper electrode of this semiconductor device is formed at a position away from the end of the lower electrode;

4 is a partial sectional view showing the structure of the capacitor of a semiconductor device 2 modified from Example 2 in which the dielectric layer of this semiconductor device is formed beyond the end of the lower electrode;

5 is a partial sectional view showing the structure of the capacitor of another semiconductor device modified from Example 2, in which the end of the upper electrode of this semiconductor device is disposed between the inclined portion in the step of the substrate and the end of the lower electrode;

Fig. 6 is a partial sectional view showing the structure of the capacitor of a semiconductor device in Example 3 of the application in which the upper electrode and metal interconnections of the semiconductor device are connected by a conductive layer. mainly made of titanium, shaped to contain contact holes;

Fig. 7 is a sectional view showing the structure of the capacitor of a semiconductor device modified from Example 3 in which the upper electrode and metal interconnections are connected by a mainly titanium-made conductive layer formed on the upper electrode;

Fig. 8 is a partial sectional view showing the structure of a semiconductor device in an embodiment of the invention, in which the upper electrode leading to the contact opening, which is formed on the insulating layer for protecting the capacitor, is formed in a position in which they are not the lower electrode covered;

FIG. 9 16 are partial sectional views illustrating a manufacturing method of the semiconductor device with capacitor, FIG. 9 FIG. 12 is a diagram showing the state of forming a conductive layer as the lower electrode, FIG. 10 the state of formation of the dielectric layer, Fig. 11 the state of forming a conductive layer as the upper electrode, FIG. 12 the state of formation of the upper electrode and the dielectric layer, FIG. 13 the state of forming the lower electrode and the state of removing the residue of the dielectric layer; 14 the state of forming a protective layer to protect the capacitor, Fig. 15 the state of forming contact holes in the protective layer and the insulating interlayer, and FIG. 16 represent the state of formation of the metal compounds;

17 is a schematic view of a dielectric layer forming apparatus in the manufacturing method of the semiconductor device with capacitor according to the invention.

Description of the examples and the preferred embodiment

example 1

In Fig. 2 reference numeral 11 denotes an N-type silicon substrate, wherein a P-type potential well 12 is formed on this N-type silicon substrate 11, an isolation region 13 for the isolation of circuit elements in the P-type potential well 12, an isolation region 14 for isolating circuit elements in the silicon substrate 11, an insulating oxide layer 15, which consists of a thick silicon oxide layer, a gate electrode 16 and an N-type diffusion layer 17 and a P-type diffusion layer 18; which form a transistor.

The reference numeral 19 is an insulating interlayer consisting of a silicon oxide film or the like formed on the N-type silicon substrate 11, and in this insulating interlayer 19, contact holes 20a, 20b are formed. On this insulating interlayer 19, metal interconnections 21a, 21b made of aluminum or an aluminum alloy, which are connected to the N-type diffusion layer 17 and the P-type diffusion layer 18, are formed through the contact openings 20a, 20b.

On the insulating interlayer 19, there is formed a capacitor composed of a lower electrode 22 of, for example, a platinum layer, a dielectric layer 23 having a high dielectric constant such as Ba1 + x Srx TiO3. (0≤X≤1) and an upper electrode 24 is made of platinum or the like, on which capacitor a protective layer 25 such as a silicon oxide film and a silicon nitride film is formed.

Contact openings 26a, 26b are formed on the protective layer 25 of the capacitor, and metal interconnections 27, 28 made of aluminum or an aluminum alloy are formed on this protective layer 25, respectively connected to the upper electrode 24 and the lower electrode 22 through the contact holes 26a, 26b to become.

According to such a structure of Embodiment 1, the capacitor is formed on the insulating interlayer 19 independently of the integrated circuit formed on the silicon substrate 11, and after heat treatment of the dielectric layer 23, the metal interconnections 21a, 21b, 27 and 28 are formed, and therefore the Material for the lower electrode 22 can be selected from a wide range. That is, the material for the lower electrode 22 can be selected only with respect to the insulating interlayer 19 and the dielectric layer 23. Moreover, the dielectric layer 23 may be treated at a temperature higher than the alloying temperature of aluminum and silicon because the dielectric layer 23 is heated before the metal interconnections 21a, 21b, 27, and 28 are formed. Therefore, in comparison with the prior art, a dielectric layer excellent in electrical characteristics can be obtained.

Moreover, the temperature of the heat treatment for improving the interface of metal interconnect 21a and N-type diffusion layer 17 and the interface between metal interconnect 21b and P-type diffusion layer 17 may be the same as in the manufacturing state of the ordinary integrated circuit (450 ° C or less), since the metal compounds 21a, 21b, 27 and 28 are formed after the heat treatment of the dielectric layer 23, the supplemented capacitor inclusion process will not degrade the integrated circuit.

Example 2

In the Figs. 3, 4 and 5, transistors and other integrated circuit integrated circuit elements are formed on a silicon substrate 31 away from the capacitor, but in the drawings transistors and other parts not directly related to the explanation of example 2 and their modified semiconductor devices are not shown are. The silicon substrate 31 has a step 31 a which is formed during the molding process of the integrated circuit, wherein on the surface of this silicon substrate 31, an insulating intermediate layer 31 b, for example, a silicon oxide layer is formed. On this insulating intermediate layer 31b, the capacitor is formed.

The capacitor consists of the lower electrode 22 as a layer of a platinum layer, the dielectric layer 23 having a high dielectric constant such as Ba 1-x Sr x TiO 3. (0≤X≤1), and the upper electrode 24, for example, a platinum layer. On the surface of the capacitor, a protective layer 25, for example, a silicon oxide layer and a silicon nitride layer is formed.

In the protective layer 25 of the capacitor, contact holes 26a, 26b are formed in which metal interconnections 27 and 28 made of aluminum or an aluminum alloy are formed, which are connected to the upper electrode 24 and the lower electrode 22, respectively.

The details of these structures will be discussed below while referring to FIGS. 3, 4 and 5.

According to FIGS. 3, 4 and 5, the arrangement in each structure is such that the end of the lower electrode 22 and the end of the upper electrode 24 are in remote positions. By this composition, a stress due to the thermal expansion of the lower electrode 22 and the upper electrode 24 generated during the heat treatment of the dielectric layer 23 is distributed and reduced, whereby breakage of the dielectric layer 23 and the interlayer insulating layer 31b can be prevented, so that the Reliability is improved.

Besides, in the structure in which the dielectric layer 23 is formed beyond the end of the lower electrode 22, as shown in FIG. 4, an effect which reduces the current leakage at the end of the dielectric layer 23 as compared with the structure of FIG. 3 is brought about Although the manufacturing process is more complicated than in the structure of FIG. Third

Moreover, the stress concentration upon heat treatment of the dielectric layer 23 of FIG. 5 can be alleviated by sequentially arranging the end of the dielectric layer 23, the end of the upper electrode 24, and the end of the lower electrode 22 from the step 31 a of the silicon substrate 31.

Example 3

In the Figs. 6 and FIG. 7 illustrates transistors and other circuit elements for assembling the integrated circuits on a silicon substrate 41 away from the capacitor, but the other parts not directly related to the explanation of Example 3 and their modified semiconductor devices are not shown in the drawings. The silicon substrate 41 has an insulating intermediate layer 41b formed thereon, for example, a silicon oxide layer, and a capacitor is formed on this insulating intermediate layer 41b. The capacitor consists of the lower electrode 22, for example a platinum layer, a dielectric layer 23 having a high dielectric constant such as Ba 1-x Sr x TiO 3. (0≤x≤1), and the upper electrode 24, for example, a platinum layer. On the surface of the capacitor, a protective layer 25, such as a silicon oxide layer and silicon nitride layer, is formed.

In the protective layer 25 of the capacitor, there are formed contact holes 26a, 26b through which the upper electrode 24 and the lower electrode 22 and aluminum or aluminum alloy-made metal interconnections 27 and 28 are mutually connected by the conductive layers 29a and 29b mainly made of titanium.

In the in Fig. 6 The conductive layers 29a, 29b consisting mainly of titanium are formed on the protective layer 25 containing the contact openings 26a, 26b, through which conductive layers 29a, 29b the metal connection 27 with the upper electrode 24 and the metal connection 28 with the lower electrode 22 connected is. By this composition, during the heat treatment of the metal compounds 27 and 28 after their formation, the reaction between the metal compounds 27, 28 and the upper electrode 24 and the lower electrode 22 through the conductive layers 29a mainly made of titanium. 29b be prevented so that the reliability can be improved and at the same time the materials for the upper electrode 24 and the lower electrode 22 can be selected from a wider range.

In the in Fig. 7 In addition, the conductive layer 29a mainly made of titanium is formed on the upper electrode 24 with the metal interconnection 27 being connected to the upper electrode 24 and the metal interconnection 28 directly to the lower electrode 22 through the conductive layer 29a. With such a structure, separation does not occur between the upper electrode 24 and the protective layer 25 upon heat treatment of the dielectric layer 23 or heat treatment of the metal interconnects 27, 28 because the titanium main conductive layer 29a is fixed to the upper electrode 24 and the protective layer 25 is connected.

embodiment

FIG. 8 shows the capacitor structure of the semiconductor device modified from Example 1 according to an embodiment of the present invention.

In Fig. 8th are the same parts as those in the in FIG. 2 Example 1 shown with the same reference numerals, with their explanations are omitted. On the insulating interlayer 19, a capacitor is formed, and in this case, the dielectric layer 23 and the upper electrode 24 are formed beyond the end of the lower electrode 22. Moreover, for connecting the upper electrode 24 and the metal interconnection 27 in the protective layer 25 of the capacitor, a contact hole 26 a is provided at a position not covering the lower electrode 22. The capacitor is formed in a covered region of the lower electrode 22 and the upper electrode 24 through the dielectric layer 23, and therefore, the effects applied to the capacitor when forming the contact holes 26a, 26b and the upper electrode are small, and the reliability is improved ,

Example 4

Figs. 9 to 16 are drawings for explaining an example of the manufacturing method of a semiconductor device with a capacitor according to the present invention.

According to FIG. 9 For example, on a silicon substrate 51, there are an insulating oxide layer 52 consisting of a thick silicon oxide layer for insulating a transistor region, a gate electrode 53 made of a polycrystalline silicon layer, a conductor wiring 54 made of a polycrystalline silicon layer, a diffusion layer 55, and an insulating interlayer 56, which consists of a silicon oxide layer formed. The surface of the interlayer insulating layer 56 is corrugated due to the effects of the gate electrode 53 formed below the interlayer insulating layer 56 and the conductor wiring 54. On such a composite insulating interlayer 56 of the integrated circuit, a multilayer film consisting of a titanium layer 57 and a platinum layer 57b is formed as a lower electrode 57.

Next, as shown in FIG. 10, on the entire surface of the silicon substrate 51, a dielectric layer 58a having a high dielectric constant such as Ba1-x Srx TiO3 is formed. (0≤x≤1), coated and heated by per se known manner.

As a result, as shown in FIG. 11, a platinum layer 59a is formed as the upper electrode 59 on the entire upper surface of the dielectric layer 58a.

Subsequently, according to FIG. 12 a cover pattern 60 is formed on the platinum layer 59a, and by using this cover pattern as a mask, platinum layer 59a and dielectric layer 58a are sequentially etched, and the upper electrode 59 and the dielectric layer 58 are formed. At the same time, the residue 58b of the dielectric layer 58 is often left in the recess of the interlayer insulating layer 56, and when this residue 58b is left, contact failure may occur in forming the contact openings 64a, 64b in a later process.

After removing the cover pattern 60, as shown in FIG. 13, a cover pattern 61 is again formed on the platinum electrode 57b to cover the capacitor, whereby the platinum layer 57b and the titanium layer 57a are etched by using this cover pattern 61 as a mask, thereby forming the lower electrode 57 , By further using the masking pattern 61 as a mask, the residue 58b of the dielectric layer 58a is removed.

After removing the cover pattern 61, as shown in FIG. 14, a protective layer 62 is formed on the entire upper surface of the silicon substrate 51.

According to FIG. 15 For example, in the protective layer 62 on the capacitor, a contact opening 63a leading to the upper electrode 59 and a contact opening leading to the lower electrode 57 are successively formed, and in the protective layer 62 and the insulating interlayer 56 in a region other than the capacitor, one to the diffusion layer 55 leading contact opening 64a and leading to the conductor wiring 54 contact opening 64b are formed. The Kontaktöff openings 63 a, 63 b and the contact openings 64 a, 64 b may be formed simultaneously in the same process or in different operations.

Next, as shown in FIG. 16, an aluminum layer or an aluminum alloy layer is formed on the entire surface of the silicon substrate 51, and the metal interconnections 65a, 65b, 66 and 67 are formed by a normal photoetching process.

Incidentally, the process of removing the residue 58b explained in Fig. 13 may be omitted if it has been sufficiently removed in the process of Fig. 12.

In this example, the titanium layer 57a and platinum layer 57b for the lower electrode 57, the dielectric layer 58a and the platinum layer 59a for the upper electrode 59 are preliminarily laminated, and then the upper electrode 59 and the dielectric layer 58 are formed, and finally the lower electrode 57, but an equally excellent capacitor can be formed by changing the order of the manufacturing process as follows.

First, on the insulating interlayer 56 of the silicon substrate 51, a multilayer film consisting of a titanium layer 57a and a platinum layer 57b is formed to compose the lower layer 57. On this multi-layer layer, a first cover pattern is formed, and by using this first cover pattern as a mask, the multi-layer is etched and the lower electrode 57 is formed. Then, after removing the first cladding layer on the silicon substrate 51 to form the upper electrode 59, the dielectric layer 58a and the platinum layer 59a are successively formed. On the platinum layer 59a, a second cap pattern is formed, and by using it as a mask, the platinum layer 59a and the dielectric layer 58a are etched, and the upper electrode 59 and the dielectric layer 58 are formed. After removing the second cover pattern, the protective layer £ 2 is formed on the whole surface. On this protective layer 62 is formed a third resist pattern for covering the entire capacitor, and by using this third resist pattern as a mask, the residue 58b of the dielectric layer 58 is removed in regions other than the capacitor. After removing the third cover pattern, contact holes 63a, 63b, 64a, 64b are formed in the protective layer 62 and the insulating interlayer 56. As a result, an aluminum layer or an alloy layer mainly composed of aluminum is formed on the entire surface of the silicon substrate 51, forming the metal interconnections 65a, 65b, 66 and 67 by normal photoetching.

Example 5

Fig. 17 is a schematic diagram of an apparatus for forming a dielectric layer, which apparatus for forming a dielectric layer will be explained herein together with the method of forming the dielectric layer in each of the examples and the embodiment.

In Fig. 17 Reference numeral 71 denotes a sputtering chamber, 72 a layer growth chamber, 73 a suction pump, and 74 particles. The sputtering chamber 71 comprises means 71a for sputtering material for the composition of the dielectric layer and a gas supply port 71b for supplying a carrier gas. Sputtering chamber 71 and film growth chamber 72 are connected to a pipe 71c for feeding particles 74 into the film growth chamber 72 together with the carrier gas. The layer growth chamber 72 comprises a substrate holding device 72a for holding the substrate 75, a grid electrode 72b arranged above the substrate holding device 72a, and an injection opening 72c for injecting air 74 into the layer growth chamber 72. The layer growth chamber 71 and the suction pump 73 are connected to a suction pipe 73a.

In growing the dielectric layer by using the dielectric layer forming apparatus, the particles 74 generated in the sputtering chamber 71 are injected through the injection port 72c into the film growth chamber 72 reduced by the suction pump 73a. The particles 74, when sputtered through the sputtering chamber 71 and injected from the injection port 72c, are mostly electrically charged by the collision and the mutual friction. Incidentally, it is more effective when they are accidentally charged by a force by installing an electrode for charging. The grid electrode 72b is charged with the reverse electric potential of the electric charge of the particles 74, and by this electric potential, the injected particles 74 on the side of the substrate 75 are attracted. The particles 74 moving through the grid electrodes 72b reach the substrate 75 and a dielectric layer is formed. Since the particles 74 are accelerated by the electric field, the kinetic energy is large, and they move and dissipate on the surface after they reach the substrate 75, so that also in the wellign part of the surface of the substrate 75, a dielectric layer is trained.

In the device for growing the dielectric layer, there is no risk of disruption of the integrated circuit when using a high voltage, because the high voltage is not directly applied to the substrate 75, if it is a semiconductor substrate on which an integrated circuit is formed and a dielectric layer is formed thereon.

Besides, by controlling the direction of the injection port 72c, a distance between the injection port 72c and the substrate 75, and a voltage applied to the grid electrodes 72b, coarse particles 76 are dropped before being attracted to the grid electrodes 72b, and only fine particles 74 can reach the substrate 75 ,

In this way, the dielectric layer can be formed on the wavy part of the surface of the substrate 75, and the precipitation of coarse particles 76 onto the substrate 75 can be prevented, by heat-treating this dielectric layer, a small defect and excellent electrical properties having dielectric layer can be achieved.

In another known method for the formation of the dielectric layer is a gel-like liquid present in colloidal solution, which consists of metallic alkoxide, which contains the metal for assembling the dielectric layer, or a metallic-organic solution is applied, containing the metal for assembling the dielectric layer, wherein the applied layer in an oxidizing, atmospheric gas is heated, while being irradiated with ultraviolet rays. Although the performance of the obtained dielectric layer is inferior compared to the embodiment of the dielectric layer of Example 5, this method does not require special equipment and is reliable for mass production. Therefore, the method may be suitable depending on the required design of the dielectric layer as well as price and performance.

In this invention, various modifications are possible in addition to the embodiments illustrated so far. For example, Examples 1 to 3 and the embodiment relate to examples of using silicon substrates on which integrated circuits are formed, but for example, the capacitor can be constructed in exactly the same manner even in substrates composed of the III-V compound or II - VI compound, or be formed in isolated substrates on which thin-film elements are formed.

In Examples 1 to 3 and in the embodiment, platinum layers are used as the lower electrode and upper electrode, but other materials, including high melting point metal layers such as Paladlum, Tungsten, tantalum, Titanium, Nickel and chromium, their alloy layers and layers of silicon metal compounds, conductive oxide layers such as indium tin oxide (ITO) and rhenium oxide, conductive nitride layers such as titanium nitride and their laminate layers can also be used.

As the dielectric layer, in Examples 1 to 3 and in the embodiment, Ba1-x Srx TiO₃ is used. (0 <x <1) but other materials including lead titanate, PZT (PbZr1 + xTixO3), PLZT (Pb1-yLayZr1-xTixO3) bismuth titanate, tantalum oxide, other dielectric and ferroelectric materials may also be used.

Meanwhile, in Examples 1 to 3 and the embodiment, by forming an amorphous layer of relatively high electric resistance on the surface of the upper electrode side of the dielectric layer, a capacitor having a low leakage current and a high insulation breakdown voltage is realized. To form this amorphous layer, after forming the dielectric layer, the pulse light beam of an excimer laser is irradiated to the surface of the dielectric layer, the layer being immediately melted and cooled rapidly.

In Examples 1 to 3 and in the embodiment, a capacitor of several nanofarads or more may be inserted between the bias line and the ground line by connecting either the upper or the lower electrode to the bias line of the integrated circuit and the other to the ground line of the integrated circuit , Therefore, the equalizing current component flowing into the biasing line can be suppressed to almost zero, so that a foreign emission can be remarkably reduced.

Moreover, in Examples 1 to 3 and the embodiment, it is better to form a silicon nitride film and a silicon oxide film below the lower electrode, and therefore, transistors and other parts composing the integrated circuit are not contaminated when the dielectric layer is heated to high temperature. In addition, by patterning the silicon nitride layer or the multilayer silicon nitride and silicon oxide layer in almost the same shape as the lower electrode after the heat treatment, in addition to the above effects, the voltage of the silicon nitride layer applied to the insulating interlayer is reduced, so that the reliability can be improved.