Method and system for bidirectionally transmitting data

The present invention relates to a two-sided-ge oriented transmission method and apparatus, and be is particularly a bi-directional-transfer method and apparatus that is capable of a rela tively slow full duplex traffic and a relatively fast Half-duplex traffic to be achieved by a transmission medium.

In the transmission apparatuses bilaterally-directed the Prior art that a two cable Übertragungslei device use, are an echo suppression system in wel Chem a transmission signal and a received signal at a Broadcast reception terminal are separated, as a Time-division transmission system in which a transmis settling time and a reception time are separated, well be known. In a fast data transfer will take time -division transmission system, no means for suppressing an echo and therefore, its hardware configuration is a fold than that of the suppression system. The time division system is described in detail in IEEE Transactions on Communications Com-30, no. 9 (1982), pages 2057-2065.

In the above-mentioned conventional technique, it is beab into account, that a full duplex traffic generally between a data terminal equipment (DTE) and an exchanger takes place. In a half-duplex traffic mode, in which Data on only one of the two directions of transmission will bear, is only one half of the transmission capability speed of the transmission line used.

It is an object of the present invention, a two to create mutually-directional transfer device effectively the transmission capacity of a transmis supply line even in a relatively fast data tragungs mode, z. B. a half-duplex transmission mode, in effectively can capitalize.

Another object of the present invention, it is a relatively slow data traffic, such. as a rela tively slow full-duplex traffic, and a relatively fast Traffic, such. As a relatively fast Halbduplexver transport, by one and the same transmission medium in response to achieve full way.

is with regard to one aspect of the present invention a transmission period (block) in a period, in which remains fixed, the transmission direction, and a time section in which the transmission direction changeable or is reversible, divided and control information for controlling the direction in the time period in which the direction of transmission is variable or reversible, is transmitted using a part of a signal is sent in the time period in which the transmis movement direction is determined so that a transmitter / receiver at a Terminal station, the transmission direction in the Zeitab can control section, in which the direction of the block About transmission is variable based on the control information or the control information and the state of the Terminal station data to be transmitted.

In the half-duplex traffic mode then data is only one of the two directions transmitted currently. Dement speaking, when a with a transmitter / receiver ver affiliated terminal station requests a service, the data using the time portion of the fixed transmission direction are transmitted, but the fixed transmission Rich tion must preset between the two transmitters / receivers will. In one embodiment of the present invention is a two-sided or reversible data transmission one or more time periods performed before the one or more periods of the fixed transmission direction are such that the transport direction in the Zeitab cut for the fixed transmission direction for each transmis tion period can be controlled by the use a portion of the information mentioned in the above- fixed section or sections is transmitted, and further if necessary, by a transport request that between the transmitters / receivers at the two Anschlußsta tions is replaced. As a result, the transmission of data, which most parts of the transmission period take, be performed in an effective manner.

Most parts of the apparatus can a conven his union apparatus, in which only a partial Variegated tion of a transmission direction control of the transmitter / Emp catcher is provided. The device is thus economic Lich.

According to one embodiment of the present invention is the relatively rapid half-duplex traffic using a scored two cable transmission line and is equally applic bar to the full duplex traffic without changing the hardware. Accordingly, the data transmission speed is with the two-wire transmission line improves, and Data transmitter / receiver is simplified, and economical.

According to a further embodiment of the present inven tion to the transmitter / receiver of the two terminal stations, which coupled by the two cable transmission line are, be identical in structure. Accordingly reduce the production costs. When sending slow data are without fast data present in the terminal are, a dummy signal is transmitted so that a time measurement signal is extracted accurately.

Further advantages, features and possible uses of present invention will become apparent from the following Be scription of embodiments in connection with the undersigned tion. This shows

<b>Fig.</b> 1a and 1b, an operation of an embodiment of the bilaterally-directional transmission according to the prior invention;

<b>Fig.</b> 2 a time-sequential operation ends in the <b>Fig.</b> 1a and 1b shown embodiment,

<b>Fig.</b> 3 is a block diagram of an example of a transmitter / EMP scavenger in the bi-directional-transmis transmission in an embodiment of the present invention is used;

<b>Fig.</b> 4a to 4c signal formats in one embodiment, the present invention;

<b>Fig.</b> 5 is a flowchart of an algorithm for controlling the transmission direction in one embodiment, the present invention;

<b>Fig.</b> 6 is a circuit diagram of a major part of the in <b>Fig.</b> 5 embodiment shown;

<b>Fig.</b> 7 is an operation of another embodiment of the present invention;

<b>Fig.</b> 8 a time-sequential operation ends in the <b>Fig.</b> 7 illustrated embodiment, and

<b>Fig.</b> 9 is a signal format in an embodiment of the prior invention.

The <b>Fig.</b> 1a and 1b illustrate an operation of a bilaterally-directional transmission device, comprising a Two cable transmission line according to an embodiment of the present invention.

As in <b>Fig.</b> 1b, two termination stations <i>A</i> and <i>B</i> through a transmission line, z. B. a two cable transmis supply line <b>3</b>Coupled. The terminal station<i>A</i> has a Data transmitter / receiver <b>1</b>Using a telephone, or a data connection <b>4</b> with the line <b>3</b> couples, and the Anschlußsta tion <i>B</i> has a data transmitter / receiver <b>2</b>Using a phone or a data terminal <b>5</b> with the line <b>3</b> coupled. In such a transport device is a block format of a by the two cable transmission line <b>3</b> transmitted Si gnals in <b>Fig.</b> 1a shown. In a block (a transfer period) are periods fixed-transfer direction, z. B. a period <b>6</b><i>(A</i> after <i>B)</i> and a period of time <b>8th</b><i>(B</i> after <i>A)</i>And periods <b>7</b> and <b>9</b> provided in wel chen the direction of transmission is variable or reversible and which for the transmission of both <i>A</i> after <i>B</i> and <i>B</i> after <i>A</i> can be used. numerals<b>10</b>. <b>11</b>. <b>12</b> and <b>13</b> be draw safety times which the collision of two mutually-related signals on the transmission line ver prevent.

In the present embodiment, there are two variable transmission direction-periods (<b>7</b> and <b>9</b>), Although only such a time period, such as in a further embodiment declared form, may be provided.

In the present embodiment, a control Informa tion for controlling the transmission direction in the variable transmission direction-periods <b>7</b> and <b>9</b> in the Fixed directional periods <b>6</b> and <b>8th</b> transfer.

In the present embodiment, the transmission is period 125 microseconds, a link clock rate of 2.56 MHz, the Number of bits of the variable-direction period of time 26 bits in each direction, a block synchronization signal has 4 Bits, and a transfer direction control signal for the Variable directional period has 4 bits. Thus be Three channels on the two cable transmission line:

<ul><li>(1) channel with 144 Kbps (Kbps per second) for two two-way data,</li><li>(2) channel at 32 Kbps for controlling the direction of the Variable directional time period, and</li><li>(3) channel at 1.536 Mbps (Mbyte per second) for Variable transmission direction.</li></ul>

To achieve these three channels, it is necessary, data 244 to transmit bits in 125 microseconds, and it takes 95.4 microseconds. Thus , the remaining 29.6 microseconds on the safety times (<b>10</b>. <b>11</b>. <b>12</b>. <b>13</b>) Are distributed.

An example of the switching of the transmission direction is in <b>Fig.</b> 2 explains. numeral<b>14</b> called slow because th, z. B. a voice which real-time and two-way Transmission needs, and Paragraph <b>15</b> Denotes a fast Since th which no real-time and two-way communication be necessary. When a data transmitter / receiver<b>1</b> with the other Data transmitter / receiver <b>2</b> communicates, the slow Data from first <i>A</i> after <i>B</i> transmitted and the fast data then transferred, and then the slow data from <i>B</i> after <i>A</i> transmitted and the speed data are then will wear, and the above steps, as in <b>Fig.</b> 2 (a) GE shows repeated.

If the terminal station <i>A</i> fast data to be transmitted has, during the terminal station <i>B</i> to be transmitted no fast data has, the slow data and are fast data <i>A</i> after <i>B</i> transmitted, and then the long Common data <i>B</i> after <i>A</i>, as in <b>Fig.</b> 2 (b). If the station <i>A</i> detects that no high-speed data from the station <i>B</i> are transmitted, transmits the station <i>A</i> the fast Data to the station <i>B</i>, By repeating the above Steps are the slow data bilaterally between <i>A</i> and <i>B</i> transmitted, but the fast data side from <i>A</i> after <i>B</i> transfer. If the station<i>A</i> no quick has data to be transmitted, said station <i>B</i> fast to transmitting data has, the reverse process is carried out.

If neither the station <i>A</i> still <i>B</i> fast to be transmitted, since th has slow data is first with transmis supply directional control bits (z. B. for rapid data transmis tion) of <i>A</i> after <i>B</i>, as in <b>Fig.</b> 2 (c), transmitted. If the station <i>B</i> detects that no high-speed data from the station <i>A</i> are transferred, are blind bits <b>16</b> from <i>B</i> after <i>A</i> Posted. Then the slow data together with Transmission direction control bits (z. B. for fast data transfer of <i>B</i> after <i>A</i> transmitted, and when the station <i>A</i> detects that no high-speed data from the station <i>B</i> transmis gen are the dummy bits <b>16</b>Which, for. Example, from the the same number of bits as that of the high-speed data can be of <i>B</i> after <i>A</i> Posted. The dummy bits<b>16</b> have no meaning as information and they can all have a "0" pattern to to permit withdrawal of the time measurement.

<b>Fig.</b> 3 shows a configuration of an embodiment of Data transmitter / receiver <b>1</b> or <b>2</b>, Input signals from a slow input and a fast input are in the buffers <b>103</b> and <b>104</b> through the respective interfaces <b>101</b> or. <b>102</b> stored. will transfer data through a Transmission data pattern generator <b>107</b> under the control of a direction control <b>108</b> generated that the above be performs prescribed direction control algorithm. A encoder <b>113</b> encoded transmission data on a Transmission line-code by a converter <b>116</b> on a two-wire transmission line <b>117</b> is sent. On the other hand, a signal from the Zweikabel- management <b>117</b> is received, a balancer <b>114</b> only for the data reception time by a switch <b>115</b> to out, which by the direction control <b>108</b> controlled becomes. The output of the equalizer<b>114</b> becomes an NRZ signal from the transmission line code by a decoder <b>112</b> decoded and in a Langsameingang- Quick input signal and a signal by a reception signal separator <b>109</b> separated. The outputs of the separation facility <b>109</b> are the respective inputs Buffer <b>105</b> and <b>106</b> and the interfaces <b>101</b> and <b>102</b> supplied. The output of the comparator <b>114</b> is also a Timer-stripper <b>111</b> supplied, which you Clock signal extracts that used in the receive mode becomes. A block sync stripper<b>110</b> syn chronized the block on the basis of the output of Deco coder <b>112</b> and performs block information of the directional control <b>108</b> to.

The <b>Fig.</b> 4A to 4C show signal formats. Both Ka channels <i>B</i> and a channel <i>D</i> are the slow data allocated, and a channel <i>H</i><b>11</b> is allocated to the high-speed data. As in<b>Fig.</b> shown 4a, have a slow data <i>F</i><b>1</b>-Merker- Pattern "0110" <b>17</b> for block synchronization, two 8-bit Channel B data <b>18</b> and <b>19</b>, 2-bit channel D (control channel) data <b>20</b> and 4-bit direction control data <b>21</b>Which indicate whether to follow the high-speed data or not. If the fast to transmit data after the transmission of slow data are, the directional control bits to "1111" are is, and when the fast data not to transmit , they are set to "0000".

As in <b>Fig.</b> 4b shown, the fast data Data tragungs block a 4-bit<i>F</i><b>2</b>-Myflag Patterns <b>22</b> on that for fast data-block synchronization and the 96-bit channel <i>H</i><b>11</b>-Data <b>23</b> serves. In<b>Fig.</b> 4c are in <b>Fig.</b> 4b fast data shown in the following <b>Fig.</b> 4a ge showed slow data sent. In<b>Fig.</b> 4c are from A simplicity reasons omitted the safety times.

<b>Fig.</b> 5 shows an algorithm in the in the direction <b>Fig.</b> 4a to 4c shown to control signal formats. If the Sta tion <i>A</i> Data transfers, the 4-bit flag is <i>F</i><b>1</b> for the Sending block synchronization (<b>26</b>), And the 18-bit data <b>2</b><i>B</i>+<i>D</i> are sent (<b>27</b>), And it is checked whether the over transmission of data <i>H</i><b>11</b> has been requested or not (<b>28</b>), And if positive, the direction control signal "1111" Posted (<b>29</b>), And then the 4-bit flags <i>F</i><b>2</b> and the 96-bit data <i>H</i><b>11</b> Posted (<b>30, 31</b>). Otherwise, if the On requirement, the data <i>H</i><b>11</b> transmitted, not output wor the is, the direction control bits "0000" sent (<b>32</b>). The first four bits of from the station<i>B</i> transmitted Signal is received (<b>32</b>) And with the internal relay,<i>F</i><b>2</b>-Pattern compared. If they are equal, the following 96-bit is Signal as a data <i>H</i><b>11</b> (<b>35</b>) Received. If they are not equal are the following 96-bit signal is used as dummy data <b>36</b> be concerns.

Then, the station receives <i>A</i> the flag <i>F</i><b>1</b>Which of the Sta tion <i>B</i> (<b>37</b>) was transferred. Then it receives the 18-bit data <b>2</b><i>B</i>+<i>D</i> (<b>38</b>) And the direction control bits (<b>39</b>). If the direction control bits "1111" (<b>40</b>) Are to be the subsequent 4-bit internal relay<i>F</i><b>2</b> and the 96-bit data <i>H</i><b>11</b> received (<b>41, 42</b>). When the direction control bits "0000" are, the transmission request for the data is <i>H</i><b>11</b> from the station <i>A</i> checked (<b>43</b>). If the request is issued has, transmits the station <i>A</i> the 4-bit flags <i>F</i><b>2</b> and the 96-bit data <i>H</i><b>11</b> (<b>44, 45</b>). If the request does not has been issued, the station transmits <i>A</i> 100-bit all-zero pattern (<b>46</b>). In this way, a transmission period completed.

A configuration of an embodiment of a device to implement the above-described Richtungssteue tion is in <b>Fig.</b> 6 is shown. It shows details of About tragungs pattern generator <b>107</b>, The directional control <b>108</b> and the reception pattern separator <b>109</b>, as in <b>Fig.</b> 3 shown. The operation of the circuit in the in Flußdia program of <b>Fig.</b> 5 sequence illustrated explains.

The channels-<b>2</b><i>B + D</i>are data in the slow data buffer <b>103</b>, And the channel<i>H</i><b>11</b>are data in the fast data channel buffer <b>104</b> stored. The data<b>2</b><i>B</i>+<i>D</i> are 18 Bits pulled out to the time and to a shift register <b>120</b> transfer. The data<i>H</i><b>11</b> are 96-bit out of time and drawn to a shift register <b>121</b> transfer. The shift register <b>120</b> has 22 bits, and the data <b>2</b><i>B</i>+<i>D</i> will in the left 18 bits and the flag <i>F</i><b>1</b> "1001" is in the right 4 bits stored. Similarly, has the Schie beregister <b>121</b> 100 bits, and the data <i>H</i><b>11</b> be in the left 96 bits and the flag <i>F</i><b>2</b> "0110" is in the right 4 bits stored. A read-only memory<b>122</b> About stores tragungszustands flag "1111" and "0000" and dummy bits from All-zero pattern.

The frame sync-stripper <b>110</b> of the <b>Fig.</b> 3 pulls the 8 KHz-block synchronizing signal under USAGE tion of the flag <i>F</i><b>1</b> the received signal out. It will 62.5 microseconds by in <b>Fig.</b> 6 delay line shown <b>139</b> delayed to a transmit timing signal to produce. A flip-flop<b>125</b> is determined by the transmission time measurement signal is triggered and a line <b>160</b> is a high <i>(H)</i> Level adjusted during a time measuring device <b>127</b> 22 bits count and a selector <b>123</b> the Schie beregister <b>120</b> is adjusted so that the flag <i>F</i><b>1</b> and the data <b>2</b><i>B</i>+<i>D</i> are successively transferred. This will be a Flip-flop <b>128</b> triggered and a line <b>161</b> is the <i>H</i>Level set. A flip-flop<b>136</b> simultaneously ge triggers, such that a duct <b>162</b> ge to the same level sets as a logic level of a line <b>165</b>, The management <b>165</b> comes from the fast data buffer <b>104</b> and is on <i>H</i>Level when the request, the data <i>H</i><b>11</b> to transmis gene, is output, and <i>L</i>Level, if the request is not output. Accordingly, it is when the On requirement is output, the line <b>161</b> on <i>H</i>level and the administration <b>162</b> well on <i>H</i>-Level. Thus, the selector facility <b>123</b> the pattern "1111" of the read-only memory <b>122</b> and transmits it. If, however, if the request does not is output, the line <b>161</b> on <i>H</i>Level, and the line <b>162</b> on <i>L</i>-Level. Thus, the selection means selects<b>123</b> the Pattern "0000" of the read-only memory <b>122</b> and transmits it. If the request for data <i>H</i><b>11</b> unspent is, the transmission is ended. If the request for data <i>H</i><b>11</b> is output, the flip-flop <b>132</b> ge triggers and a line <b>163</b> on <i>H</i>Level set and the selector <b>123</b> selects the shift register <b>121</b>, This state continues until a timer <b>133</b> 100 cycles at End of the transfer counts, all lines <b>160</b>. <b>161</b>. <b>162</b>. <b>163</b> and <b>164</b> be on the <i>L</i>set level and a gate <b>124</b> detects the end of the transmission and sets a switch <b>115</b> to the receiving position.

In the receiver normally selects a selector <b>152</b> a shift register <b>150</b> and Goals <b>148</b> and <b>149</b> capture each Weil, the flags <i>F</i><b>1</b> and <i>F</i><b>2</b>,

When the internal relay,<i>F</i><b>1</b>Pattern "1001" is detected, checks a goal <b>140</b>Whether the associated time measurement with that of the previously pulled-block synchronizing signal matches, and then a flip-flop <b>141</b> triggered. The administration<b>166</b> is on the <i>H</i>Level for a period of 187 clocks by a timer <b>142</b> held, and selecting means <b>152</b> selects the slow data buffer <b>105</b>To the data <b>2</b><i>B</i>+<i>D</i> transferred to. Then, a flip-flop<b>143</b> triggered and a timer <b>144</b> holding a line <b>167</b> on a <i>H</i>-Level for a period of 4 clocks and the selector <b>152</b> selects the shift register <b>151</b>, Then the direction will control bits tested. To an accurate determination to ge equip, even if a bit error during the transmis tion had a majority decision circuit provided see that the <i>H</i>generates level when the number of "1" bits of 4 bits of bits is greater than that of "0". If the data<i>H</i><b>11</b> are continuously transmitted, the <i>H</i>Level-Si signal is generated and when the transfer is completed, will the <i>L</i>Level signal generated. After the Richtungssteuerungs- Bits have been received, the flip-flop <b>143</b> reset so that the selection means reproduces the shift register <b>150</b> chooses. If the flag<i>F</i><b>2</b> is detected, the flip-flop <b>145</b> triggered and the line <b>168</b> is on the <i>H</i>level ge hold, while the timer <b>146</b> 96 clocks one, and the selector <b>152</b> fast data buffer <b>106</b> chooses, the data <i>H</i><b>11</b> to recieve.

On the other hand, if the received direction control bits "0000" are a line <b>169</b> on <i>L</i>-Level set. When the transmitting station, the data to be transmitted<i>H</i><b>11</b> has, is a line <b>165</b> on the <i>H</i>Level and the flip- flop <b>132</b> is triggered, so that the data <i>H</i><b>11</b> receive will. When the transmitting station no data to be transmitted<i>H</i><b>11</b> has, is the line <b>165</b> on the <i>L</i>Level and a gate <b>138</b> produces the <i>H</i>-Level. Thus, the flip-flop<b>134</b> triggered and the line <b>164</b> on <i>H</i>set level and the off selection device <b>123</b> selects the dummy pattern or all-zero Pattern in the read-only memory <b>122</b>, This state continues until the timer <b>135</b> 100 cycles counts. In this way, a broadcast reception period completed.

In the present embodiment, the data can Sen / receiver in two terminal stations through common Algorithm and circuit are implemented.

<b>Fig.</b> 7 shows a signal format in a transmission period in another embodiment of the present invention. In the present embodiment, a transmission period in two periods <b>76</b> and <b>77</b> divided in which the data in a fixed direction by <i>A</i> after <i>B</i> or <i>B</i> after <i>A</i> are transmitted, and a period of time <b>78</b>, in which the data from either <i>A</i> after <i>B</i> or <i>B</i> after <i>A</i> for each Peri ode be transferred.

In particular, a transmission period is 125 microseconds (8 KHz) and a transmission rate is 2.04 MHz. Thus , 256 bits in a 125 microsecond time domain arranged who the. Of the 256 bits 16 bits on each of firm tragungsrichtungs-periods <b>76</b> and <b>77</b> distributed 184 be on the semi-direction transfer period <b>78</b> distributed, and the remaining 40 bits (= 256-184-2 × 16) be on safety times <b>80</b>. <b>81</b> and <b>82</b> distributed.

Each of the 16 bit time periods <b>76</b> and <b>77</b> includes a 4-bit block synchronization signal, a 2-bit signaled ative signal and a 2-bit transmission direction control signal for the semi-direction transfer time range <b>109</b>, With the signal format described above, the four channels,

<ul><li>(A) channel 64Kbps for two-way low speed data transmission</li><li>(B) signaling channel at 16 kbps (the used can be used as a channel <i>D</i> an ISDN [Integrated Services Digital Network], when a data connection technology Means [DTE] <b>104</b> an exchanger)</li><li>(C) a channel of 16 Kbps for controlling the transmis movement direction of the semi-Richtungsübertragungs- Time interval, and</li><li>(D) a channel with 1.472 Mbps for Halbduplexver traffic,</li></ul>

achieved on the two-wire transmission line.

As an embodiment of the transmission direction control is for the semi-direction transfer period a method for controlling the direction of transmission performed if one of the data transmitter / receiver as a master station is used. The two bits<i>S</i> and <i>T</i> (Bit <i>S</i>. that from <i>A</i> after <i>B</i> is transmitted is through <i>S</i>_A_→_<i>B</i> designated, and of <i>B</i> after <i>A</i> transmitted bits <i>S</i> and <i>T</i> will by <i>S</i>_B_→_<i>A</i> and <i>T</i>_B_→_<i>A</i> each shown) of Übertragungsrichtungs- are control channel for directional control used. <i>(T</i>_A_→_<i>B</i> is not used.) <i>S</i>_A_→_<i>B</i> = "1" indicates that the side-directional transfer period <b>78</b> for the data transmission of <i>A</i> after <i>B</i> or <i>B</i> after <i>A</i> used is, and <i>T</i>_B_→_<i>A</i> = "1" indicates the presence of the data transmission from <i>B</i> after <i>A</i> at. The operation of the data transmitter / receiver<i>A</i> is as follows.

<ul><li>(A) If <i>T</i>_B_→_<i>A</i> a previous transmission period "0" , and the request for the data transmission after <i>B</i> is present, <i>S</i>_A_→_<i>B</i> set to "1", and the side-directional transmission line is used for the <i>A</i>_→_<i>B</i>-Data Used.</li><li>(B) If <i>T</i>_B_→_<i>A</i> a previous transmission period "0" , and the request for the data transmission after <i>B</i> is missing, <i>S</i>_A_→_<i>B</i> set to "0", and if <i>S</i>_<i>B</i>_→_<i>A</i> "1", the data of be <i>B</i> receive.</li><li>(C) If <i>T</i>_B_→_<i>A</i> a previous transmission period "1" , and the request for the data transmission after <i>B</i> is present, then there is the requirement for the two-way data before and the transmission direction is opposite to the previous selected. When the transfer direction of<i>A</i> after <i>B</i> running, <i>S</i>_A_→_<i>B</i> set to "1", and the data to <i>B</i> transfer. When the transfer direction from <i>B</i> after <i>A</i> running, <i>S</i>_A_→_<i>B</i> on "0" is set, and the data from <i>B</i> received.</li><li>(D) If <i>T</i>_B_→_<i>A</i> an earlier Übertragungsgperiode "1" , and the request for the data transmission after <i>B</i> is missing, <i>S</i>_A_→_<i>B</i> set to "0", and the data from <i>B</i> received.</li></ul>

On the other hand, the data transmitter operates / receiver <i>B</i> as follows:

<ul><li>(A) When the request for data transmission by <i>A</i> missing and <i>S</i>_<i>A</i>_→_<i>B</i> "1", the data of be <i>A</i> receive.</li><li>(B) If the request for data transmission by <i>A</i> present and <i>S</i>_<i>A</i>_→_<i>B</i> Is "0", is <i>S</i>_<i>B</i>_→_<i>A</i> set to "1", and the data is to <i>A</i> transfer. If <i>S</i>_<i>A</i>_→_<i>B</i> Is "1", then <i>S</i>_<i>B</i>_→_<i>A</i> "0" is set, and <i>T</i>_<i>B</i>_→_<i>A</i> is set to "1", and the data from <i>A</i> received. An example of traffic, of the above-described traffic direction control system used is in <b>Fig.</b> 8, in the <i>S</i>_<i>A</i>_→_<i>B</i>. <i>S</i>_<i>B</i>_→_<i>A</i> and <i>T</i>_<i>B</i>_→_<i>A</i> and the direction of data transfer by 1.472 Mbps traffic channel are shown. In<b>Fig.</b> 8 (a) is only the Requirement for transport of <i>B</i> after <i>A</i>, There<i>S</i>_<i>A</i>_→_<i>B</i> = Is "0", the data can continuously from <i>B</i> after <i>A</i> be transmitted. In the same way exists in <b>Fig.</b> 8 (b) only the request for transport of <i>A</i> after <i>B</i>, In<b>Fig.</b> 8 (c) is the Requirement for transport of <i>A</i> after <i>B</i> and from <i>B</i> after <i>A</i>, The direction of the traffic of 1.472 Mbps Traffic channel changes from <i>A</i> after <i>B</i> and from <i>B</i> after <i>A</i> for each block.</li></ul>

As in <b>Fig.</b> 8, the continuous transmission is according to the present embodiment at 1.472 Mbps in the Half-duplex traffic achieved, and the full-duplex traffic at 0.736 Mbps is achieved without changing the hardware.

When the transfer direction is set to a direction is a 1.472 Mbps unilaterally-targeted traffic is achieved.

A configuration of the transmitter / receiver to the in <b>Fig.</b> 7 to implement the method shown, may be substantially be the same as those described in <b>Fig.</b> 3 and 4a to 4c shown. A particular configuration can vary depending upon the transmission rate and the number of bits vary.

Since the side-directional transfer period (<b>79</b> in <b>Fig.</b> 7) even exist in a transmission period and Although behind the two fixed direction-periods <b>106</b> and <b>107</b>, The configuration of the logic circuit of the Directional control of <b>Fig.</b> 2 different from that of the <b>Fig.</b> . 6

<b>Fig.</b> 9 shows an example of a signal in the embodiment of the <b>Fig.</b> . 7