Semiconductor device

IN RELATED US APPLICATION

0001This application claims the benefit of US Provisional Application 61 / 487.627, entitled "Semiconductor device with reduced gate charge and higher coefficient of performance", filed May 18, 2011, which is incorporated herein by reference in its entirety.

STATE OF THE ART

0002To achieve an energy-efficient power conversion system based power MOSFETs (Metalloxidhalbleiterfeldeffekttransistoren), which are used as the core switch to low gate charge and low on-state resistance. For example, in a DC-to-DC converter (DC), such as a synchronous buck converter uses two MOSFETs, one as the "high side" -MOSFET, and the other as the "low side" -MOSFET. The high-side MOSFET is controlled by an external enable signal and sources current to a load, while the low-side MOSFET connects the charge to ground or dissolved and thus subtracting current from the charge.

0003There are some specific characteristics and requirements for each of the Hochseiten- and low-side MOSFETs. For example, while lower resistances for the low-side MOSFET is desired, high-speed switching characteristics are desirable with low gate charge for the high-side MOSFET.

0004One of the metrics widely used for a power MOSFET is an FOM (Figure of Merit) is defined as the gate charge multiplied by the drain-to-source resistance at the specified gate voltages. A lower value for this coefficient of performance translates to better performance for high-side MOSFETs.

0005A MOSFET can achieve lower gate charge and thus a lower value for the coefficient of performance would be both useful and beneficial as, for example, a high-side MOSFET in a DC-to-DC converter.

SUMMARY

0006Embodiments according to the present invention provide efficient and novel metal / insulator / semiconductor (MIS) devices (eg. B. MOSFETs) having lower gate charge, and lower FOM values.

0007In one embodiment, a semiconductor device includes (z. B. a MOSFET), a first group of ridge-like structures and a second group of ridge-like structures (for simplicity, the ridge-like structures in the following be referred to as grooves). Each of the grooves in the first group includes a gate electrode, which is connected to gate metal in contact, and also includes a source electrode, which is connected to source metal contact and is insulated from the gate electrode. Each of the grooves in the second group is blocked.

0008In one embodiment, a layer of metal source passes through the first group of the (Utilized) grooves and the second group of the blocked furrows. In such an embodiment, each of the blocked groove includes a single polysilicon region. The polysilicon regions in each of the grooves are blocked substantially in the same plane as the source and gate electrodes in the furrows used. The polysilicon regions in each of the grooves are blocked in contact with the layer of the source metal within the active core region of the semiconductor device, and are also in contact with the gate metal. In contrast, in the furrows used, the gate electrode is disposed between the source electrode and the layer of source metal and insulated from the layer of source metal, but in contact with the gate metal.

0009Also, in the furrows used, the source electrode in contact with the source metal core outside the active region, but is insulated from the layer of the source metal within the active core region.

0010The second group of blocked furrows is interleaved with the first groups of grooves used. In one embodiment, the first group to set up furrows and the second group arenested in the blocked groove in an alternating fashion. That is, in one embodiment, each second groove being blocked. In other embodiments, every third groove is blocked or every fourth groove is blocked, and so on.

0011As an unexpected benefit when a half of the furrows is blocked, for example, then decreases the drain-to-source resistance by less than a factor of two, instead of a factor of two, as expected, while the gate charge by a factor of two decreases. As a result, the value of FOM is advantageously reduced by blocking selected grooves, as described above.

0012In one embodiment, the characteristics of the semiconductor device, as described above, implemented in a MOSFET. In such an embodiment, such characteristics in a high-side MOSFET, coupled to a low-side MOSFET in a DC-to-DC converter implemented.

0013These and other objects and advantages of the present invention will be appreciated by one skilled in the art upon review of the following detailed description, which are illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

0014The accompanying drawings, which are incorporated in and constitute a part of this specification illustrated embodiments of the invention and, together with the description, serve to explain the principles of the invention. Like reference numerals designate like elements throughout the drawings and the description.

0015<figref>1</figref> shows a view from top to bottom of a portion of a semiconductor device in an embodiment according to the present invention.

0016<figref>2</figref> is a cross-sectional view showing elements of a semiconductor device in accordance with embodiments of the present invention.

0017<figref>3</figref> shows a view from top to bottom of a portion of a semiconductor device in an embodiment according to the present invention.

0018<figref>4</figref> is a flow diagram listing masks that are used in a method for the manufacture of semiconductor devices in an embodiment according to the present invention.

DETAILED DESCRIPTION

0019In the following detailed description of the present invention, numerous specific details are set forth to allow a thorough understanding of the present invention. However it will be appreciated by those skilled in the art that the present invention without these specific details or with equivalents thereof may be practiced. In other instances, well known methods, procedures, components and circuits have not been described in detail so as not to obscure aspects of the present invention unnecessarily.

0020Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing and other symbolic representations of the operation of manufacturing and operation of semiconductor devices. These descriptions and illustrations are the means used by those skilled in the field of semiconductor device manufacturing, in order to convey the substance of their work to others skilled in effective manner. In the present application, a procedure, logic block, process or the like to be understood to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. It should be remembered, however, that all of these and similar terms with the appropriate physical quantities should be associated and only are suitable indicia that are applied to these quantities. Provided herein is not performed otherwise specifically, as will become apparent from the following discussion, it should be understood that in the entire application discussions regarding terms such as "form", "performing", "manufacturing", "depositing", "etching" or the like refer to actions and processes for semiconductor device manufacture or store operations.

0021Figures are not drawn to scale, and only portions of the structures, as well as the various layers that form those structures, may be shown in the figures. Furthermore, manufacturing processes and steps can be carried out together with the procedures and steps discussed herein; that is, it may be before a number of process steps, between and / or after the steps shown and described herein provide. Importantly, embodiments of the present invention in conjunction with these other (perhaps conventional) structures, methods and steps can be implemented without disturbing this much. Generally speaking, embodiments of the present invention, portions of a conventional device or method to replace, without significantly affecting peripheral structures, methods and steps.

0022The term "groove" when discussed in the context of a manufacture of a device, generally refers to an empty volume which is formed inside a material. Such groove may then be filled with other material or materials. The term "groove" when discussed in the context of a semiconductor device manufactured, generally refers to the structure formed within the previously empty furrow. A groove may also be referred to herein as a strip. The meaning of the term "groove" in the following discussion will be made clear in the context of the discussion.

0023Embodiments according to the present invention relate to new structures in order to achieve lower gate charge, and lower FOM values ​​in semiconductor devices such as MOSFET devices, which can be used as the high-side MOSFETs in, for example, DC-to-DC converters, as synchronous buck converters.

0024<figref>1</figref> is a view from top to bottom, the particular elements of a semiconductor device <figref>100</figref> in an embodiment according to the present invention. Not all elements that may be included in a semiconductor device are described in

0025<figref>1</figref> shown. Several levels are in<figref>1</figref> shown; that is, for example, the source metal layer<figref>125</figref> actually (upper side) of the strip <figref>111</figref>-<figref>116</figref>,

0026In the example of <figref>1</figref> the device includes <figref>100</figref> a number of strips (or cells <figref>111</figref>-<figref>116</figref> a, which are substantially parallel to each other in the active core region <figref>105</figref> are. The active core area<figref>105</figref> is the area which in the dotted lines <figref>1</figref> is limited.

0027As described further in connection with <figref>2</figref> will be described, each of the strips <figref>111</figref>-<figref>116</figref> a ridge-like structure. As also continue in connection with<figref>2</figref> will be described, some of the strips are blocked while others are not. The blocked strips are electrically and physically connected to the source metal layer<figref>125</figref> within the active core region <figref>105</figref> connected, and are also electrically and physically connected to the gate metal layer <figref>135</figref> via the gate contact <figref>137</figref> connected. The strips used (those that are not blocked) are relative to the source metal layer<figref>125</figref> within the active core region <figref>105</figref> isolated, however, include a source electrode (see <figref>2</figref>), Which electrically and physically connected to the source metal layer <figref>125</figref> over the source contact <figref>127</figref> are connected outside the active core region, and also include a gate electrode (see <figref>2</figref>), Which electrically and physically connected to the gate metal layer <figref>135</figref> via the gate contact <figref>137</figref> connected is.

0028<figref>2</figref> is a cross-sectional view (along the line AA in <figref>1</figref>) Of the device <figref>100</figref> in one embodiment according to the present invention. Not all elements that may be included in a semiconductor device are described in<figref>2</figref> shown.

0029Four furrow-like structures <figref>111</figref>-<figref>114</figref> are shown. For ease of discussion, the ridge-like structures may be simply referred to as furrows in the following discussion. In the orientation of the<figref>2</figref>As shown in the orientation of the <figref>1</figref>, The furrows are <figref>111</figref>-<figref>114</figref> parallel to each other.

0030In the example of <figref>2</figref> the device includes <figref>100</figref> a first epitaxial (or buffer) layer <figref>202</figref> and a second epitaxial layer <figref>204</figref> on. It may also include a drain region (not shown) below the first epitaxial layer<figref>202</figref> give. The furrows<figref>111</figref>-<figref>114</figref> extend into the second epitaxial layer <figref>204</figref>,

0031A body region <figref>206</figref> (Z. B. a p-doped region) is shown between adjacent furrows. Also are source regions<figref>208</figref> (Z. B. n + doped regions) shown between adjacent furrows. The source metal layer<figref>125</figref> covers (passes) the furrows <figref>111</figref>-<figref>114</figref>, As described below, theSource metal layer <figref>125</figref> relative to the electrodes in selected grooves (z. B. the furrows <figref>112</figref> and <figref>114</figref>) In the active region <figref>105</figref> (<figref>1</figref>) Of the device <figref>100</figref> isolated, however, (eg. B. is in contact with the electrodes in other selected furrows furrows <figref>111</figref> and <figref>113</figref>) In the active core region. Accordingly, in the example of<figref>2</figref> the furrows <figref>111</figref> and <figref>113</figref> blocked while the furrows <figref>112</figref> and <figref>114</figref> are used (not blocked).

0032The furrows <figref>112</figref> and <figref>114</figref> may be referred to as a split gate. Each of the grooves<figref>112</figref> and <figref>114</figref> includes a first Polysilizumbereich <figref>214</figref> (Poly-1), also referred to as a source electrode or a shield electrode. Each of the grooves<figref>112</figref> and <figref>114</figref> also includes a second polysilicon region <figref>216</figref> (Poly-2), also referred to as a gate electrode. The source electrodes<figref>214</figref> are from the adjacent epitaxial layer <figref>204</figref> by Shield oxide <figref>218</figref> separated, and the gate electrodes <figref>216</figref> are from the adjacent epitaxial layer <figref>204</figref> by a gate oxide <figref>220</figref> separated. The source electrodes<figref>214</figref> in the furrows <figref>112</figref> and <figref>114</figref> are offset from the gate electrodes <figref>216</figref> in the furrows <figref>112</figref> and <figref>114</figref> by an intermediate oxide <figref>222</figref> isolated. In the furrows<figref>112</figref> and <figref>114</figref> are the gate electrodes <figref>216</figref> between the source electrodes <figref>214</figref> and the source metal layer <figref>125</figref> arranged. The gate electrodes<figref>216</figref> are relative to the source metal layer <figref>125</figref> by Zwischenisolationsoxidschicht <figref>224</figref> isolated. Referring also to<figref>1</figref> are the source electrodes <figref>214</figref> in the furrows <figref>112</figref> and <figref>114</figref> electrically and physically in contact with the source metal layer <figref>125</figref> over the source contact <figref>127</figref>, And the gate electrodes <figref>216</figref> within the furrows <figref>112</figref> and <figref>114</figref> are electrically and physically in contact with the gate metal layer <figref>135</figref> via the gate contact <figref>137</figref> (<figref>1</figref>).

0033In the embodiment of <figref>2</figref> includes any of the blocked furrow <figref>111</figref> and <figref>113</figref> a standalone polysilicon region <figref>235</figref> (Poly-1) a connected to said source metal layer <figref>125</figref> and the gate metal layer <figref>135</figref> (<figref>1</figref>) Is in contact. The poly-1-areas<figref>235</figref> the blocked furrow <figref>111</figref> and <figref>113</figref> are substantially in the same plane as the source electrodes <figref>214</figref> and the gate electrodes <figref>216</figref> in the set furrow. That is, in the orientation by<figref>2</figref> covered the tops of the poly-1-areas <figref>235</figref> approximately with the upper sides of the gate electrodes <figref>216</figref> together and the lower sides of the poly-1-areas <figref>235</figref> fall broadly with the lower sides of the source electrodes <figref>214</figref> together. The poly-1-areas<figref>235</figref> are from the adjacent epitaxial layer <figref>204</figref> by an oxide layer <figref>238</figref> separated.

0034It is important that the poly-1-areas <figref>235</figref> not with respect to the source metal layer <figref>125</figref> are isolated; the source metal layer<figref>125</figref> is electrically and physically in contact with the poly-1-areas <figref>235</figref>, Furthermore, with reference also to<figref>1</figref>, The poly-1-Beriche <figref>235</figref> in the furrows <figref>111</figref> and <figref>113</figref> also electrically and physically in contact with the source metal layer <figref>125</figref> over the source contact <figref>127</figref> and to the gate metal layer <figref>135</figref> via the gate contact <figref>137</figref>,

0035Thus, according to the example <figref>2</figref> used half of the cells / strip / furrows (z. B. the furrows <figref>112</figref> and <figref>114</figref>) And half of the cells / strip / furrows is blocked (z. B. the furrows <figref>111</figref> and <figref>113</figref>). In other words, the cells used / strip / furrows with the blocked cells / strips / grooves are interleaved in an alternating manner so that every other cell / strip / groove is blocked. This is in<figref>3</figref> shown that a view from top to bottom of the device <figref>100</figref> shows. In other embodiments, a third of a quarter, a fifth, and so on of the core cells / strips can (every third cell / strip / furrow blocked), be blocked.

0036As mentioned above, a size widely used for a power MOSFET, a FOM, which is defined as the gate charge multiplied by the drain-to-source resistance at specific gate voltages. A lower value for these FOM means better performance for high-side MOSFETs.

0037Using a core area which is as large as before, it can be expected that if one half of the core cell / strips / grooves is used and the other half of the core cell / strips / grooves is blocked, then the gate charge by half would fall and the resistors by a factor of 2 would increase. However, because a current displacement in the drift region for cell high density devices, such as those described herein are, some resistors are experienced in this field. By blocking some (z. B. the half) of the core cells / strip / furrows use the carrier flowing through a side channel of the core cell / strip, the entire drift region, and thus a lower current displacement of the flow of carrier and less resistor from experienced this area. Thus, in fact, increase the total drain-to -source resistances. By a factor of less than 2, when half of the core cells / strip / furrows is blocked

0038On the other hand, the gate charge take proportionally according to the active core cell area. As a result of the combined effects of the drain-to-source resistance and the gate charge a better FOM can be achieved using the approach described in the present disclosure.

0039This is illustrated by the trapped in Table 1 results. "Rsp4.5V (core)" represents the resistivity between the drain and the source at a gate voltage of 4.5 V at a stand-alone core cell / strips. "Rds (on) @ 4.5V typical" demonstrates a final resistance between the drain and the source at a gate voltage of 4.5 V in a Power PAK^® 1212 package. "Qgsp4.5V" stands for the specific gate charge per active unit area at a gate voltage of 4.5 V. "Qg4.5V" shows a value of the total gate charge at a gate voltage of 4.5 V. the FOM is typically the product of Qg4.5V and Rds (on) @ 4.5V. improve embodiments of the present invention FOM levels by approximately 32% when half of the core cells / strip / furrows is blocked. Table 1 - Example results<tables><table frame="all"><tgroup cols="5" colsep="1" rowsep="1"><colspec colname="col1" colwidth="1*" /><colspec colname="col2" colwidth="1*" /><colspec colname="col3" colwidth="1*" /><colspec colname="col4" colwidth="1*" /><colspec colname="col5" colwidth="1*" /><tbody><row><entry colname="col1" /><entry colname="col2">units</entry><entry colname="col3">State of the art</entry><entry colname="col4">Embodiment of the present disclosure</entry><entry colname="col5">percent change</entry></row><row><entry colname="col1">Rsp4.5V (core)</entry><entry colname="col2">milliohms · mm²</entry><entry colname="col3">4.43</entry><entry colname="col4">6.22</entry><entry colname="col5">40%</entry></row><row><entry colname="col1">Rds (on) @ 4.5V (typical)</entry><entry colname="col2">milliohms</entry><entry colname="col3">2.2</entry><entry colname="col4">2.8</entry><entry colname="col5">28%</entry></row><row><entry colname="col1">Qgsp4.5V</entry><entry colname="col2">nC / mm²</entry><entry colname="col3">8.3</entry><entry colname="col4">4.4</entry><entry colname="col5">-47%</entry></row><row><entry colname="col1">Qg4.5V</entry><entry colname="col2">nC</entry><entry colname="col3">24.1</entry><entry colname="col4">12.8</entry><entry colname="col5">-47%</entry></row><row><entry colname="col1">FOM</entry><entry colname="col2">Qg4.5 * Rds4.5</entry><entry colname="col3">53</entry><entry colname="col4">36</entry><entry colname="col5">-32%</entry></row></tbody></tgroup></table></tables>

0040<figref>4</figref> is a flow diagram <figref>400</figref>Showing the sequence of masks that are used to form the blocked strips / grooves and the strips used / grooves in an embodiment according to the present invention. Other masks and manufacturing steps can be with the masks that are included in the following discussion, are used. The following discussion is intended to highlight changes in the manufacturing process that are introduced to form the above-identified blocked furrows.<figref>4</figref> is also with reference to <figref>2</figref> discussed.

0041In block <figref>401</figref> A furrow mask used to empty furrows <figref>111</figref>-<figref>114</figref> to build. In block<figref>402</figref> , after poly 1 has been deposited in the furrows, a shield (source) -Polyätzblockmaske configured so that the poly-1 blocked in the furrows <figref>111</figref> and <figref>113</figref> is not exposed to an etching, while the poly-1 furrows used in the <figref>112</figref> and <figref>114</figref> is exposed to the etching. Thus, the poly-1 is in the blocked furrow<figref>111</figref> and <figref>113</figref> not etched, but the Poly-1 is used in the furrows <figref>112</figref> and <figref>114</figref> etched back to the source electrodes <figref>214</figref> to build.

0042In block <figref>403</figref> an active mask is used to prevent the thick oxide layer <figref>238</figref>That the blocked furrow <figref>111</figref> and <figref>113</figref> lining, is diluted to prevent the poly-2 is deposited in the furrows blocked. The furrows<figref>112</figref> and <figref>114</figref> are not protected by the active mask so that the gate oxide <figref>220</figref> in front of a poly-2-deposition in the furrows <figref>112</figref> and <figref>114</figref> is thinned to the gate electrodes <figref>216</figref> to build.

0043In block <figref>404</figref> is used during a re-etching of the poly-2-regions, a gate Polyätzblockmaske. In block<figref>405</figref> is a source implant mask for the appropriate separation of the source regions <figref>208</figref> used. In block<figref>406</figref> A body implant mask used for proper separation of the body regions <figref>206</figref>, In blocks<figref>407</figref>. <figref>408</figref>. <figref>409</figref> and <figref>410</figref> Polykontakt-, Kernkontakt-, Metallätz- and pillow masks are used to the contacts <figref>135</figref> and <figref>137</figref> form and the electrodes <figref>214</figref>. <figref>216</figref> and <figref>235</figref> to bring to the source metal and gate metal contact.

0044Thus, the blocked furrow <figref>111</figref> and <figref>113</figref> to form a shield Polyätzblockmaske (block <figref>402</figref>) And an active mask (Block <figref>403</figref>) Introduced or modified. Consequently, the blocked furrows can be formed without substantially disturbing the manufacturing process.

0045In summary, embodiments of the semiconductor devices and embodiments of the methods of making such devices are described. Embodiments according to the invention can be used in furrows power MOS transistors and high density in the charge balance MOSFET family with a split gate structure. Embodiments according to the invention can be used in high-side DC-DC Umwandleranwendungen.

0046The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable those skilled in the art to best utilize the invention and various embodiments and various modifications to the best, as determined by the particular intended use adapted. It is intended that the scope of the invention is defined by the herein appended claims and their equivalents.

0047Generally speaking, this document discloses semiconductor devices. It also discloses a semiconductor device that includes a first group of ridge-like structures and a second group of ridge-like structures. Each ridge-like structure in the first group includes a gate electrode which is in contact with a gate metal, and a source electrode with a source metal contact. Each of the ridge-like structures in the second group is blocked. The second group of the blocked furrow-like structures is interleaved with the first set of ridge-like structures.

0048All the elements, components and steps described herein are preferably included. It is to be understood that each of these elements, parts and steps by other elements, parts and steps can be replaced or combined can be omitted, as it will be apparent to those skilled in the art.

CONCEPTS:

0049This document presents at least the following concepts.

0050Concept 1. A semiconductor device comprising: a first plurality of ridge-like structures, each ridge-like structure in the first plurality, a gate electrode with a gate metal contact, and a source electrode connected to source metal is in contact, comprising; and a second plurality of blocked ridge-like structures, which is interleaved with the first plurality of ridge-like structures.

0051Concept 2. The semiconductor device according to concept 1, wherein each of the blocked furrow-like structure comprises a stand-alone polysilicon region which is the source metal contact and is connected to the gate metal contact.

0052Concept 3. The semiconductor device according to concept 2, wherein the single polysilicon region substantially in the same plane as the source electrode and the gate electrode.

0053Concept 4. The semiconductor device according to concept 1, wherein the first plurality and the second plurality of ridge-like structures are interleaved in an alternating fashion.

0054Concept 5. The semiconductor device according to concept 1, wherein at least two successive ridge-like structures of the first plurality of another ridge-like structure of the first plurality being separated by a blocked groove-like structure.

0055Concept 6. The semiconductor device according to concept 1, comprising a layer of the source metal which passes through the first plurality of ridge-like structures and the second plurality of ridge-like structures, the source electrode connected to the source metal outside an active core region of the semiconductor device in contact, and wherein the source electrode is opposite to the layer of source metal isolated within the active core region, and wherein the blocked ridge-like elements are in contact with the layer of source metal within the active core region.

0056Concept 7. The semiconductor device according to concept 1, comprising a layer of the source metal which passes through the first plurality of ridge-like structures and the second plurality of ridge-like structures, wherein said gate electrode between the source electrode and the layer of source metal is disposed, and wherein the gate electrode is insulated from the layer of source metal.

0057Concept 8. The semiconductor device according to concept 1, wherein the first and second pluralities are arranged on ridge-like structures in a pattern that is selected from the group consisting of: one of two ridge-like structures is blocked; one of three ridge-like structures is blocked; one of four ridge-like structures is blocked.

0058Concept 9. The semiconductor device according to Concept 1 comprising a metal oxide semiconductor (MOSFET).

0059Concept 10. The semiconductor device according to concept 9, wherein said MOSFET includes a high-side MOSFET, the DC-to-DC converter is coupled to a low-side MOSFET in a.

0060Concept 11. A semiconductor device comprising: a first split-gate structure which includes a first electrode region and a second electrode region; a second structure parallel to the first split-gate structure and comprising a polysilicon region in contact with the gate metal; and a source metal layer, which is opposite to the first split-gate-structure isolated in an active region of the semiconductor device and is in contact with the polysilicon field within the active region.

0061Concept 12. The semiconductor device according to concept 11, wherein the first electrode portion includes a source electrode that is connected to source metal outside the active region in contact, and wherein the second electrode comprises a gate electrode of the MIT gate metal outside active Berichs in contact.

0062Concept 13. The semiconductor device according to concept 12, wherein the gate electrode between the source electrode and the source metal layer is disposed, and wherein the gate electrode is isolated from the source metal layer, and also with respect to the source electrode.

0063Concept 14. The semiconductor device according to concept 11, wherein the polysilicon region substantially in the same plane as the first electrode portion and the second electrode region.

0064Concept 15. The semiconductor device according to concept 11, further comprising a second split-gate structure comprising two electrode regions, wherein the second structure between the first split gate structure and the second split-gate structure is disposed on.

0065Concept 16. The semiconductor device according to concept 11 further comprising at least two successive split-gate structures, each comprising two electrode regions, wherein the second structure between the first split-gate structure and two consecutive split gate structures is arranged.

0066Concept 17. A semiconductor device comprising: a first furrow-like structure comprising a first polysilicon region and a second polysilicon region that are isolated from each other by an oxide region; a second ridge-like structure parallel to the first ridge-like structure and comprising a third polysilicon region; and a source metal layer, which passes through both the first furrow-like structure and the second ridge-like structure, said second polysilicon region between the first polysilicon region and said source metal layer is disposed, and wherein said source metal layer over the second polysilicon area is isolated and Contact with the third polysilicon area.

0067Concept 18. The semiconductor device according to concept 17, wherein said first polysilicon area includes a source electrode that is in contact with the source metal layer, said second polysilicon region comprises a gate electrode, which is connected to gate metal in contact, and wherein Furthermore, the third polysilicon area is in contact with the source metal layer and the gate metal.

0068Concept 19. The semiconductor device according to concept 17, wherein the third polysilicon area in the same plane as the first polysilicon region and the second polysilicon region.

0069Concept 20. The semiconductor device according to concept 17, further comprising a third ridge-like structure comprising two polysilicon regions, said second ridge-like structure between the first ridge-like structure and the third ridge-like structure is arranged.

0070Concept 21. The semiconductor device according to concept 17, further comprising at least two successive ridge-like structures parallel to the first ridge-like structure and said second ridge-like structure, each of the successive ridge-like structures comprising two electrode regions, wherein the second ridge-like structure between the first ridge-like structure, and two successive ridge-like structures arranged.