Semiconductor device

STATE OF THE ART

0001To realize an energy-efficient power conversion system, power MOSFETs (metal-oxide-semiconductor field-effect transistors) used as core switches rely on low gate charges and low on-state resistances. For example, in a DC-to-DC converter (direct current), such as a synchronous buck converter, two MOSFETs are used, one as the "high-side" MOSFET and the other as the "low-side" MOSFET. The high-side MOSFET is controlled by an external enable signal and source current to a load, while the low-side MOSFET connects or disconnects the load to ground, thus draining current from the load.

0002There are some specific features and requirements for each of the high-side and low-side MOSFETs. For example, while lower on-resistances are desired for the low-side MOSFET, high-speed switching characteristics with low gate charges are desirable for the high-side MOSFET.

0003One of the widely used metrics for MOSFET performance is FOM (Figure of Merit), defined as the gate charge multiplied by the drain-to-source resistance at the specified gate voltages. A lower value for this figure of merit translates to better performance for high-side MOSFETs.

0004A MOSFET that can achieve lower gate charges and thus a lower figure of merit would be both useful and beneficial as, for example, a high-side MOSFET in a DC-to-DC converter.

0005The printed matter<de-docref CY="WO" DNUM="2011050115" KI="A2">WO 2011 / 050 115 A2</de-docref> discloses a semiconductor device comprising: a plurality of trench structures extending into an epitaxial layer, the plurality of trench structures comprising: a first plurality of the plurality of trench structures, each trench structure in the first plurality of trench structures having a gate electrode in contact with gate metal and insulated from source metal by an intervening oxide layer, each trench structure in the first plurality further comprising a source electrode of polysilicon material in contact with the source metal, wherein the gate electrode is separated from the epitaxial layer by a gate oxide, wherein the source electrode is separated from the epitaxial layer by a shield oxide, and wherein each trench structure in the first plurality is adjacent to both a respective first source region and a respective second source region, a second plurality of the plurality of trench structures, each of the trench structures being adjacent to a source region, wherein each trench structure of the blocked trench structures is filled with the polysilicon material to form only a single polysilicon region within each trench structure, each single polysilicon region being in contact with the source metal and separated from the epitaxial layer by the shield oxide, and wherein a lower side of the single polysilicon region and a lower side of the source electrode are aligned substantially in a same horizontal plane.

0006The printed matter<de-docref CY="EP" DNUM="0717450" KI="A2">EP 0 717 450 A2</de-docref> discloses a semiconductor device comprising: a plurality of trench structures extending into an epitaxial layer, the plurality of trench structures comprising: a first plurality of the plurality of trench structures, wherein each trench structure in the first plurality of trench structures comprises a gate electrode insulated from source metal by an intermediate oxide layer, wherein each trench structure of a first plurality further comprises a source electrode in contact with the source metal, the gate electrode being separated from the epitaxial layer by a gate oxide, wherein each trench structure in the first plurality is adjacent to both a respective first source region and a respective second source region, a second plurality of the plurality of trench structures comprising blocked trench structures interleaved with the first plurality of trench structures in an alternating manner such that each further trench structure of the plurality of trench structures is blocked, wherein each blocked trench structure of the blocked trench structures is filled with the polysilicon material such that only a single polysilicon region is formed within each blocked trench structure, each single polysilicon region being in contact with the source metal and being separated from the epitaxial layer by shield oxide.

0007The printed matter<de-docref CY="US" DNUM="20050167742" KI="A1">US 2005 / 0 167 742 A1</de-docref> discloses a trench filled with polysilicon and a gate trench. The gate trench and the trench are arranged alternately. Furthermore, the aforementioned document discloses a split-gate trench and a trench filled with polysilicon in contact with source metal, with the two trench types being arranged alternately.

SUMMARY

0008Embodiments according to the present invention provide efficient and novel metal/insulator/semiconductor (MIS) devices (e.g., MOSFETs) with lower gate charges and lower FOM values.

0009In one embodiment, a semiconductor device (e.g., a MOSFET) includes a first group of trench structures and a second group of trench structures (for simplicity, the trench structures may be referred to as trenches hereinafter). Each of the trenches in the first group includes a gate electrode in contact with gate metal and also includes a source electrode in contact with source metal and insulated from the gate electrode. Each of the trenches in the second group is blocked.

0010In one embodiment, a layer of source metal extends through the first group of utilized trenches and the second group of blocked trenches. In such an embodiment, each of the blocked trenches encloses a single polysilicon region. The polysilicon regions in each of the blocked trenches are substantially in the same plane as the source and gate electrodes in the utilized trenches. The polysilicon regions in each of the blocked trenches are in contact with the source metal layer within the active core region of the semiconductor device and are also in contact with the gate metal. In contrast, in the inserted trenches, the gate electrode is disposed between the source electrode and the source metal layer, insulated from the source metal layer but in contact with the gate metal.

0011Also, in the trenches used, the source electrode is in contact with the source metal outside the active core region, but is insulated from the layer of source metal within the active core region.

0012The second group of blocked trenches is interleaved with the first group of inserted trenches. In one embodiment, the first group of inserted trenches and the second group of blocked trenches are interleaved in an alternating manner. That is, in one embodiment, every second trench is blocked. In other embodiments, every third trench is blocked or every fourth trench is blocked, and so on.

0013As an unexpected benefit, if one half of the trenches are blocked, for example, the drain-to-source resistance increases by less than a factor of two, instead of a factor of two as expected, while the gate charge decreases by a factor of two. As a result, the value of the FOM is advantageously reduced by blocking selected trenches, as described above.

0014In one embodiment, the features of the semiconductor device as described above are implemented in a MOSFET. In such an embodiment, such features are implemented in a high-side MOSFET coupled to a low-side MOSFET in a DC-to-DC converter.

BRIEF DESCRIPTION OF THE DRAWINGS

0015The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Like reference characters refer to like elements throughout the drawings and the description.<ul id="ul_0001" list-style="none"><li id="ul_0001_0001"><figref>1</figref> shows a top-down view of a portion of a semiconductor device in an embodiment according to the present invention.</li><li id="ul_0001_0002"><figref>2</figref> is a cross-sectional view showing elements of a semiconductor device in embodiments according to the present invention.</li><li id="ul_0001_0003"><figref>3</figref> shows a top-down view of a portion of a semiconductor device in an embodiment according to the present invention.</li><li id="ul_0001_0004"><figref>4</figref> is a flowchart listing masks used in a method of manufacturing semiconductor devices in one embodiment according to the present invention.</li></ul>

DETAILED DESCRIPTION

0016Some sections of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of the operation for fabricating and operating semiconductor devices. These descriptions and illustrations are the means used by those skilled in the art of semiconductor device fabrication to effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logical block, method, or the like is understood to be a self-consistent sequence of steps or instructions that lead to a desired result. The steps are those that require physical manipulation of physical quantities. It should be remembered, however, that all these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated herein, as will become apparent from the following discussion, it should be understood that throughout this application, discussions regarding terms such as "forming," "performing," "manufacturing," "depositing," "etching," or the like refer to acts and methods of semiconductor device fabrication or operation.

0017Figures are not to scale, and only portions of the structures and the various layers forming such structures may be shown in the figures. Furthermore, manufacturing methods and steps may be performed in conjunction with the methods and steps discussed herein; that is, there may be a number of process steps before, between, and/or after the steps shown and described herein. Importantly, embodiments according to the present invention can be implemented in conjunction with these other (possibly conventional) structures, methods, and steps without significantly disrupting them. Generally speaking, embodiments according to the present invention can replace portions of a conventional device or method without significantly affecting peripheral structures, methods, and steps.

0018The term "trench," when discussed in the context of device fabrication, generally refers to an empty volume formed within a material. Such a trench can subsequently be filled with another material or materials. The term "trench," when discussed in the context of a fabricated semiconductor device, generally refers to the structure formed within the previously empty trench. A ditch may also be referred to herein as a strip. The meaning of the term "ditch" in the following discussion will become clear in the context of the discussion.

0019Embodiments according to the present invention relate to novel structures to achieve lower gate charges and lower FOM values ​​in semiconductor devices, such as MOSFET devices, which can be used as high-side MOSFETs in, for example, DC-to-DC converters, such as synchronous buck converters.

0020<figref>1</figref> is a top-down view showing certain elements of a semiconductor device 100 in an embodiment according to the present invention. Not all elements that may be included in a semiconductor device are shown in<figref>1</figref> Several levels are shown in<figref>1</figref> shown; that is, for example, the source metal layer 125 is actually above (top of) the stripes 111-116.

0021In the example of<figref>1</figref> The device 100 includes a number of stripes (or cells 111-116) that are substantially parallel to each other in the active core region 105. The active core region 105 is the region defined by the dashed lines in<figref>1</figref> is limited.

0022How to continue in connection with<figref>2</figref> As will be described, each of the strips 111-116 is a trench structure. As will also be further described in connection with<figref>2</figref> As will be described, some of the stripes are blocked, while others are not. The blocked stripes are electrically and physically connected to the source metal layer 125 within the active core region 105, and are also electrically and physically connected to the gate metal layer 135 via the gate contact 137. The inserted strips (those that are not blocked) are insulated from the source metal layer 125 within the active core region 105, but include a source electrode (see<figref>2</figref>) which are electrically and physically connected to the source metal layer 125 via the source contact 127 outside the active core region, and also include a gate electrode (see<figref>2</figref>) which is electrically and physically connected to the gate metal layer 135 via the gate contact 137.

0023<figref>2</figref> is a cross-sectional view (along the line AA in<figref>1</figref>) of the device 100 in an embodiment according to the present invention. Not all elements that can be included in a semiconductor device are<figref>2</figref> shown.

0024Four trench structures 111-114 are shown. For ease of discussion, the trench structures may be referred to simply as trenches in the following discussion. In the orientation of the<figref>2</figref>, as in the orientation of the<figref>1</figref>, trenches 111-114 are parallel to each other.

0025In the example of<figref>2</figref> Device 100 includes a first epitaxial (or buffer) layer 202 and a second epitaxial layer 204. There may also be a drain region (not shown) beneath first epitaxial layer 202. Trenches 111-114 extend into second epitaxial layer 204.

0026A body region 206 (e.g., a p-doped region) is shown between adjacent trenches. Also shown are source regions 208 (e.g., n+-doped regions) between adjacent trenches. The source metal layer 125 extends across (traverses) the trenches 111-114. As described below, the source metal layer 125 is exposed from the electrodes in selected trenches (e.g., the trenches 112 and 114) in the active region 105 (<figref>1</figref>) of the device 100, but is in contact with the electrodes in other selected trenches (e.g., trenches 111 and 113) in the active core region. Accordingly, in the example of<figref>2</figref> Trenches 111 and 113 are blocked, while trenches 112 and 114 are deployed (not blocked).

0027Trenches 112 and 114 may be referred to as split gates. Each of trenches 112 and 114 includes a first polysilicon region 214 (Poly-1), also referred to as a source electrode or a shield electrode. Each of trenches 112 and 114 also includes a second polysilicon region 216 (Poly-2), also referred to as a gate electrode. The source electrodes 214 are separated from the adjacent epitaxial layer 204 by a shield oxide 218, and the gate electrodes 216 are separated from the adjacent epitaxial layer 204 by a gate oxide 220. The source electrodes 214 in the trenches 112 and 114 are insulated from the gate electrodes 216 in the trenches 112 and 114 by an interlayer oxide layer 222. In the trenches 112 and 114, the gate electrodes 216 are arranged between the source electrodes 214 and the source metal layer 125. The gate electrodes 216 are insulated from the source metal layer 125 by an interlayer insulating oxide layer 224. Also referring to<figref>1</figref> the source electrodes 214 in the trenches 112 and 114 are electrically and physically in contact with the source metal layer 125 via the source contact 127, and the gate electrodes 216 within the trenches 112 and 114 are electrically and physically in contact with the gate metal layer 135 via the gate contact 137 (<figref>1</figref>).

0028In the embodiment according to<figref>2</figref> Each of the blocked trenches 111 and 113 includes a standalone polysilicon region 235 (Poly-1) connected to the source metal layer 125 and the gate metal layer 135 (<figref>1</figref>) is in contact. The poly-1 regions 235 of the blocked trenches 111 and 113 are substantially in the same plane as the source electrodes 214 and the gate electrodes 216 in the inserted trenches. That is, in the orientation<figref>2</figref> The upper sides of the poly-1 regions 235 roughly coincide with the upper sides of the gate electrodes 216, and the lower sides of the poly-1 regions 235 roughly coincide with the lower sides of the source electrodes 214. The poly-1 regions 235 are separated from the adjacent epitaxial layer 204 by an oxide layer 238.

0029It is significant that the poly-1 regions 235 are not isolated from the source metal layer 125; the source metal layer 125 is electrically and physically in contact with the poly-1 regions 235. Furthermore, also referring to<figref>1</figref>, the poly-1 regions 235 in the trenches 111 and 113 are also electrically and physically in contact with the source metal layer 125 via the source contact 127 and with the gate metal layer 135 via the gate contact 137.

0030Thus, in the example according to<figref>2</figref> Half of the cells/strips/trenches are deployed (e.g., trenches 112 and 114) and half of the cells/strips/trenches are blocked (e.g., trenches 111 and 113). In other words, the deployed cells/strips/trenches are interleaved with the blocked cells/strips/trenches in an alternating manner, so that every second cell/strip/trench is blocked. This is<figref>3</figref> , which shows a top-down view of device 100. In other embodiments, one-third (every third cell/stripe/trench blocked), one-quarter, one-fifth, and so on of the core cells/stripes may be blocked.

0031As mentioned above, a widely used metric for MOSFET performance is FOM, which is defined as the gate charge multiplied by the drain-to-source resistance at specific gate voltages. A lower value for this FOM indicates better performance for high-side MOSFETs.

0032Using a core area as large as before, it can be expected that if one half of the core cells/stripes/trenches are deployed and the other half of the core cells/stripes/trenches are blocked, then the gate charges would decrease by half and the resistances would increase by a factor of 2. However, since there is current displacement in the drift region for high-density cell devices such as those described herein, some series resistances from this region are experienced. By blocking some (e.g. When half of the core cells/stripes/trenches are blocked, the carriers flowing through a side channel of the core cell/stripe utilize the entire drift region, and thus, less current displacement for carrier flow and less series resistance are experienced from this region. Consequently, in reality, the total drain-to-source resistances increase by a factor of less than 2 when half of the core cells/stripes/trenches are blocked.

0033On the other hand, the gate charges decrease proportionally according to the core cell active area. As a result of the combined effects on the drain-to-source resistance and the gate charge, a better FOM can be achieved using the approach described in the present disclosure.

0034This is illustrated by the results included in Table 1. "Rsp4.5V(core)" represents the resistivity between the drain and source at a gate voltage of 4.5V for a standalone core cell/strip. "Rds(on) @4.5V typical" demonstrates a final product resistance between the drain and source at a gate voltage of 4.5V in a Power PAK.^® 1212 package. "Qgsp4.5V" represents the specific gate charges per unit active area at a gate voltage of 4.5V. "Qg4.5V" indicates a value of the total gate charges at a gate voltage of 4.5V. The FOM is the product of Qg4.5V and Rds(on) @4.5V typically. Embodiments according to the present invention improve FOM values ​​by approximately 32% when half of the core cells/stripes/trenches are blocked.<de-tables num="0000"><de-objecttitle>Table 1 - Example results</de-objecttitle><table frame="all"><tgroup cols="5" colsep="1" rowsep="1"><colspec colname="col1" colsep="1" rowsep="1" colnum="1" colwidth="40.371263152941175mm" /><colspec colname="col2" colsep="1" rowsep="1" colnum="2" colwidth="24.627259247058824mm" /><colspec colname="col3" colsep="1" rowsep="1" colnum="3" colwidth="27.996035011764707mm" /><colspec colname="col4" colsep="1" rowsep="1" colnum="4" colwidth="45.46338875294118mm" /><colspec colname="col5" colsep="1" rowsep="1" colnum="5" colwidth="31.542053835294116mm" /><thead><row rowsep="1"><entry align="center" colname="col1" valign="top" colsep="1" rowsep="1" /><entry align="center" colname="col2" valign="top" colsep="1" rowsep="1">units</entry><entry align="center" colname="col3" valign="top" colsep="1" rowsep="1">State of the art</entry><entry align="center" colname="col4" valign="top" colsep="1" rowsep="1">Embodiment of the present disclosure</entry><entry align="center" colname="col5" valign="top" colsep="1" rowsep="1">Percentage change</entry></row></thead><tbody><row rowsep="1"><entry align="center" colname="col1" valign="top" colsep="1" rowsep="1">Rsp4.5V (core)</entry><entry align="center" colname="col2" valign="top" colsep="1" rowsep="1">mΩ·mm²</entry><entry align="center" colname="col3" valign="top" colsep="1" rowsep="1">4,43</entry><entry align="center" colname="col4" valign="top" colsep="1" rowsep="1">6,22</entry><entry align="center" colname="col5" valign="top" colsep="1" rowsep="1">40%</entry></row><row rowsep="1"><entry align="center" colname="col1" valign="top" colsep="1" rowsep="1">Rds(on) @4.5V (typical)</entry><entry align="center" colname="col2" valign="top" colsep="1" rowsep="1">mΩ</entry><entry align="center" colname="col3" valign="top" colsep="1" rowsep="1">2,2</entry><entry align="center" colname="col4" valign="top" colsep="1" rowsep="1">2,8</entry><entry align="center" colname="col5" valign="top" colsep="1" rowsep="1">28%</entry></row><row rowsep="1"><entry align="center" colname="col1" valign="top" colsep="1" rowsep="1">Qgsp4.5V</entry><entry align="center" colname="col2" valign="top" colsep="1" rowsep="1">nC/mm²</entry><entry align="center" colname="col3" valign="top" colsep="1" rowsep="1">8,3</entry><entry align="center" colname="col4" valign="top" colsep="1" rowsep="1">4,4</entry><entry align="center" colname="col5" valign="top" colsep="1" rowsep="1">-47%</entry></row><row rowsep="1"><entry align="center" colname="col1" valign="top" colsep="1" rowsep="1">Qg4.5V</entry><entry align="center" colname="col2" valign="top" colsep="1" rowsep="1">nC</entry><entry align="center" colname="col3" valign="top" colsep="1" rowsep="1">24,1</entry><entry align="center" colname="col4" valign="top" colsep="1" rowsep="1">12,8</entry><entry align="center" colname="col5" valign="top" colsep="1" rowsep="1">-47%</entry></row><row rowsep="1"><entry align="center" colname="col1" valign="top" colsep="1" rowsep="1">FOM</entry><entry align="center" colname="col2" valign="top" colsep="1" rowsep="1">Qg4.5*Rds4.5</entry><entry align="center" colname="col3" valign="top" colsep="1" rowsep="1">53</entry><entry align="center" colname="col4" valign="top" colsep="1" rowsep="1">36</entry><entry align="center" colname="col5" valign="top" colsep="1" rowsep="1">-32%</entry></row></tbody></tgroup></table></de-tables>

0035<figref>4</figref> 400 is a flowchart illustrating the sequence of masks used to form the blocked stripes/trenches and the inserted stripes/trenches in one embodiment according to the present invention. Other masks and manufacturing process steps may be used with the masks included in the following discussion. The following discussion is intended to highlight changes in the manufacturing process that are introduced to form the blocked trenches referred to above.<figref>4</figref> is also made with reference to<figref>2</figref> discussed.

0036In block 401, a trench mask is used to form empty trenches 111-114. In block 402, after Poly-1 is deposited in the trenches, a shield (source) poly etch block mask is configured so that the Poly-1 in the blocked trenches 111 and 113 is not exposed to etching, while the Poly-1 in the inserted trenches 112 and 114 is exposed to etching. Thus, the poly-1 in the blocked trenches 111 and 113 is not etched back, but the poly-1 in the inserted trenches 112 and 114 is etched back to form the source electrodes 214.

0037In block 403, an active mask is deployed to prevent the thick oxide layer 238 lining blocked trenches 111 and 113 from thinning to prevent poly-2 from being deposited into the blocked trenches. Trenches 112 and 114 are not protected by the active mask, so the gate oxide 220 is thinned prior to poly-2 deposition into trenches 112 and 114 to form gate electrodes 216.

0038In block 404, a gate poly etch block mask is used during an etchback of the poly 2 regions. In block 405, a source implant mask is used to properly deposit the source regions 208. In block 406, a body implant mask is used to properly deposit the body regions 206. In blocks 407, 408, 409 and 410, poly contact, core contact, metal etch and pad masks are used to form contacts 135 and 137 and to contact electrodes 214, 216 and 235 to the source metal and gate metal.

0039Thus, to form the blocked trenches 111 and 113, a shield poly etch block mask (block 402) and an active mask (block 403) are introduced or modified. Consequently, the blocked trenches can be formed without significantly disrupting the manufacturing process.

0040In summary, embodiments of semiconductor devices and embodiments of methods for fabricating such devices are described. Embodiments according to the invention can be used in high-density trench power MOS transistors and in the charge-balancing MOSFET family with a split-gate structure. Embodiments according to the invention can be used in high-side DC-DC converter applications.

0041Generally speaking, this document discloses semiconductor devices. It further discloses a semiconductor device including a first group of trench structures and a second group of trench structures. Each trench structure in the first group includes a gate electrode in contact with a gate metal and a source electrode in contact with a source metal. Each of the trench structures in the second group is blocked. The second group of blocked trench structures is nested with the first group of trench structures.