Power efficient voltage level translator circuit

High Efficiency Power Voltage Level Shifter Circuit Technical Field

[0001] The disclosed aspects relate to voltage power supplies for processing systems. More specifically, the exemplary aspects are directed to a high-efficiency power voltage level shifter circuit for voltage level translation between a first voltage domain and a second voltage domain.

Background technique

[0002] Modern processing systems (eg, system-on-a-chip or "SOC") may contain a variety of subsystems or components, which may have different frequency and power considerations. Accordingly, different parts of the SOC may have different supply voltages. For example, a memory system may include memory cells (eg, static random access memory or "SRAM" cells), which may be supplied with higher supply voltages, while central processing units (CPUs) or processor cores Logic cells may support lower supply voltages. Thus, an SOC may be designed with two or more than two voltage islands or voltage domains (eg, logic voltage domains, memory voltage domains, etc.), each voltage domain having components tailored to fit within the voltage domain (eg, logic cells, Corresponding voltage supply considering the voltage of memory cells, etc.

[0003] There may be signals that span two voltage domains, eg, a read or write command issued by a CPU in the logic voltage domain to a memory system in the memory voltage domain. For such signals, a conversion circuit, known in the art as a "voltage level shifter", may be provided to convert the signal from the first voltage domain to the second voltage domain. However, in some cases, the voltages of one or more voltage domains may be dynamically scaled, which may result in the supply voltages of the first and second voltage domains being equal or substantially the same (eg, in "acceleration mode", as in It is known in the art where the previously low supply voltage of the logic voltage domain can be scaled to a higher supply voltage to operate logic cells at higher frequencies, and where the higher supply voltage of the logic voltage domain can be substantially the same as the memory voltage domain with the same supply voltage). In that case, a voltage level shifter between the first and second voltage domains would not be required, since the supply voltages of the first and second voltage domains are substantially the same.

[0004] However, in conventional designs, the voltage level shifters may still be active and perform voltage translation of signals between the first and second voltage domains unnecessarily, even though the power supply of the first and second voltage domains The voltages are roughly the same. By remaining active and in the signal path, the voltage level shifter always consumes power and adds delay in the signal path, even when the voltage level shifter is not needed.

SUMMARY OF THE INVENTION

[0005] Exemplary aspects of the invention are directed to systems and methods for high-efficiency power voltage level translators. In a normal mode in which the first supply voltage of the first voltage domain is different from the second supply voltage of the second voltage domain, a voltage level translator converts the input signal in the first voltage domain to the second voltage domain output signal. In bypass mode where the first supply voltage is substantially the same as the second supply voltage, a bypass circuit is configured to bypass the voltage level shifter and provide the first voltage domain The input signal is used as the output signal, thereby avoiding the delay introduced by the voltage level shifter in the bypass mode. Further, a power down circuit is configured to power down the voltage level shifter in the bypass mode, but not in the normal mode.

[0006] For example, one exemplary aspect is directed to an apparatus comprising: a voltage level shifter configured to provide a first supply voltage in a first voltage domain and a second supply in a second voltage domain voltage differs from normal mode, the conversion

The input signal in the first voltage domain is the output signal in the second voltage domain; a bypass circuit configured to bypass the first supply voltage and the second supply voltage substantially the same in a bypass mode, the voltage level shifter is bypassed and the input signal is provided in the first voltage domain as the output signal; and a power down circuit configured to be in the bypass mode , but not in the normal mode, power down the voltage level translator.

Another exemplary aspect is a method for voltage level shifting, the method comprising: in a normal mode in which a first supply voltage of a first voltage domain is different from a second supply voltage of a second voltage domain, at a voltage converting an input signal in the first voltage domain into an output signal in the second voltage domain in a level shifter; in a bypass mode where the first supply voltage is substantially the same as the second supply voltage , bypassing the voltage level shifter and providing the input signal as the output signal in the first voltage domain; and in the bypass mode, but not in the normal mode, powering down all The voltage level shifter.

[0008] Yet another exemplary aspect is directed to an apparatus comprising: in a normal mode in which a first supply voltage of a first voltage domain is different from a second supply voltage of a second voltage domain, converting the first supply voltage means for an input signal in a voltage domain to be an output signal in the second voltage domain; means for bypassing the first supply voltage in a bypass mode in which the first supply voltage is substantially the same as the second supply voltage means for converting, and providing the input signal in the first voltage domain as the output signal; and for in the bypass mode, but not in the normal mode, power down all The device for the voltage level shifter.

Description of drawings

[0009] The drawings are presented to assist in describing aspects of the present invention, and are provided solely to illustrate the aspects and not to limit the aspects.

[0010] Figures 1A-B illustrate a conventional voltage level shifter.

[0011] Figures 2A-D illustrate circuits relating to voltage level shifters according to exemplary aspects of the invention.

[0012] FIG. 3 illustrates a block diagram corresponding to a method of performing voltage level translation in accordance with an exemplary aspect of the disclosure.

[0013] FIG. 4 illustrates an exemplary computing device in which aspects of the present invention may be advantageously utilized.

detailed description

[0014] Aspects of the invention are disclosed in the following description and related drawings directed to specific aspects of the invention. Alternative aspects may be devised without departing from the scope of the present invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the invention" does not require that all aspects of the invention include the discussed feature, advantage or mode of operation.

[0016] The terminology used herein is for the purpose of describing particular aspects only and is not intended to limit aspects of the invention. As used herein, the singular forms "a (a/an)" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprising" and/or "comprising" when used herein designate the presence of recited features, integers, steps, operations, elements and/or components, but do not exclude one or more other features , an integer, a step, an operation, an element, a component, and/or the presence or addition of a group thereof.

[0017] Apart from the above, many aspects are described in terms of the order of actions to be performed by elements of, eg, a computing device. It will be appreciated that the various actions described herein may be implemented by specific circuits (eg, application specific integrated circuits).

integrated circuit; ASIC)), executed by program instructions being executed by one or more processors or by a combination of the two. In addition, these sequences of actions described herein may all be considered to be embodied within any form of computer-readable storage medium in which a corresponding set of computer instructions is stored, the computer instructions being executed upon execution will cause the associated processor to perform the functionality described herein. Accordingly, various aspects of the inventions may be embodied in several different forms, all of which are intended to be within the scope of the claimed subject matter. Additionally, for each of the aspects described herein, a corresponding form of any such aspect may be described herein as, for example, "logic" that is "configured to" perform the described actions.

[0018] Exemplary aspects of the present disclosure are directed to a voltage level translator configured to convert a signal from a first voltage domain to a second voltage domain. In the case where the first voltage domain is equal to the second voltage domain, a selective bypass circuit is included to bypass the voltage level shifter to avoid voltage level shifting in the signal path between the first and second voltage domains delay introduced by the device. Furthermore, in an exemplary aspect, a power control circuit may be included to power down or shut down the voltage level shifter when the voltage level shifter is skipped in the manner described above. Thus, in an exemplary aspect, power consumption and delays associated with voltage level shifters may be avoided when voltage level shifters are not required in the signal path. These and related aspects will now be elucidated in the following sections with reference to the drawings.

[0019] First, with reference to FIGS. 1A to B, a conventional voltage level shifter 100 will be described. Voltage level shifter 100 is configured to convert complementary input signals a 114 and a_n 116 in a first voltage domain powered by first supply voltage VDD1 to output signal z 120 in a second voltage domain powered by second supply voltage VDD2. Without loss of generality, under normal operating conditions, the first supply voltage VDD1 may be less than the second voltage source VDD2, while in some examples, the first and second voltage sources VDD1 and VDD2 may be substantially the same voltage value. While the particular conditions under which the first and second voltage sources VDD1 and VDD2 may take different values or the manner in which these voltage sources are generated are not closely related to this discussion, one example may involve a processor core or the like including a processing system with logic cells A first voltage domain of , where the first voltage source VDD1 may be referred to as a logic supply voltage; and a second voltage domain including a memory system having memory cells, where the second voltage source VDD2 may be referred to as a memory supply voltage.

1A-B, the voltage level shifter 100 includes: pull-up transistors 102 and 104, which may be configured with p-channel metal oxide semiconductor (p-channel metal oxide semiconductor; PMOS) device or p-channel field effect transistor (PFET); pull-down transistors 108 and 112, which may be configured with n-channel metal oxide semiconductor (NMOS) devices or n-channel field an n-channel field effect transistor (NFET); and pull-up transistors 106 and 110, which may be configured as PMOS devices or PFETs. The voltage level shifted outputs of complementary input signals a 114 and a_n 116 may be derived from node 122 , which pass through inverter 118 to provide output signal z 120 . While the operational details of voltage level shifter 100 as illustrated in Figures 1A-B are well known, some brief details will be provided in the following sections, bearing in mind that various other configurations of voltage level shifters may apply to the present invention Exemplary Aspects of the Disclosure.

1A, it is illustrated that input signal a 114 rises or transitions from a low logic state (eg, binary "0") to a high logic state (eg, binary "1"), and correspondingly, and input signal a_n 116 falls Case. Accordingly, in the first stage, pull-up transistor 106 will begin to turn off and pull-down transistor 108 will begin to turn on, which begins to discharge node 122 . On the other side, the input signal a_n 116 falls while turning on the pull-up transistor 110 and turning off the pull-down transistor 112 . Once node 122 falls to a sufficiently low value, in the second stage, pull-up transistor 104 turns on, and pull-up transistors 104 and 110 begin to charge node 123 to the second supply voltage VDD2.

[0022] As node 123 charges, pull-up transistor 102 begins to turn off, and its auxiliary pull-down transistor 108 further pulls down the node

Point 122. Pull-down node 122 assists in the process of pull-up transistor 104 being turned on, which further charges node 123 . Eventually, pull-up transistor 102 is fully turned off, node 122 transitions to logic state "0", and node 123 transitions to logic "1" in the second voltage domain. Nodes 122 and 123 maintain their logic states "0" and "1" , until the complementary input signals a 114 and a_n 116 continuously change in value.

Thus, after passing through inverter 118, the inverted value of node 122 appears as output signal z 120, which rises in the second voltage domain, corresponding to the rise and input of input signal a 114 in the first voltage domain Fall of signal a_n 116. The above-identified stages of voltage level shifter 100 introduce corresponding delays or delays in the paths between complementary input signals one 114 and a_n 116 and output signal z 120 .

[0024] Referring now to FIG. 1B, the opposite scenario will now be described, where the input signal a 114 falls and a_n 116 rises. In this case, pull-up transistor 110 will begin to turn off and pull-down transistor 112 will begin to turn on, thereby discharging node 123 . On the other hand, when the pull-up transistor 106 is turned on, the pull-down transistor 108 is turned off as the input signal a 114 falls. Once node 123 drops to a sufficiently low value, in the second stage, pull-up transistor 102 turns on, and pull-up transistors 102 and 106 begin to charge node 122 to the second supply voltage VDD2. As node 122 charges, pull-up transistor 104 begins to turn off, and its auxiliary pull-down transistor 112 further pulls down node 123 . Pull-down node 123 assists in the process of pull-up transistor 102 being turned on, which further charges node 122 . Eventually, pull-up transistor 104 is fully turned off and node 123 transitions to logic state "0", while node 122 transitions to logic state "1" in the second voltage domain. The logic state of node 122 is inverted by inverter 118 to appear as falling output signal z 120 in the second voltage domain. Nodes 122 and 123 maintain their logic states "1" and "0", respectively, until successive transitions of complementary input signals a 114 and a_n 116 occur. As can be seen, the above-identified stages involved in the operation of the voltage level shifter 100 also cause significant delays in this situation.

[0025] For situations where the difference between the voltage values of the first and second supply voltages VDD1 and VDD2 is large, the stack of pull-up transistors 102 and 106 on the left side of the voltage level shifter 100 may be thinned to The pull-down transistor 108 is allowed, for example, to effectively pull down the node 122 if the input signal a 114 rises (or transitions from low to high) and the corresponding input signal a_n 116 falls (or transitions from high to low). Similarly, the stack of pull-up transistors 104 and 110 on the right side of voltage level shifter 100 can be thinned to allow pull-down transistor 112 to be effective when input signal a 114 falls and input signal a_n 116 rises accordingly Pull down the node 123 down. This relative size of the pull-down and pull-up transistors can further increase the delay from complementary input signals a 114 and a_n 116 and output signal z 120 .

[0026] From the above discussion of the voltage level shifter 100, it can be appreciated that in the two cases shown in FIGS. 1A-B, a considerable delay is introduced. In addition, the multiple stages of turning on and off the various pull-up and pull-down transistors consume power. Where the first voltage source VDD1 of the first voltage domain is substantially the same as the second voltage source VDD2 of the second voltage domain, in an exemplary aspect, which will now be discussed with reference to FIGS. 2A-B, with the voltage level shifter 100 related delays and power can be avoided.

2A, a circuit 200 is shown, which includes a voltage level shifter 250 and a bypass circuit 252. The voltage level shifter 250 may be configured to work with the conventional voltage level shifter 100 described with reference to FIGS. 1A-B, or any other suitable for converting the complementary input signal a in the first voltage domain powered by the first voltage source VDD1 214 and a_n 216 are similar in voltage level shifter configurations for the intermediate output signal y_n derived at node 222 in the second voltage domain supplying the second voltage source VDD2. In an example aspect, the first voltage domain corresponds to a logic voltage domain that includes logic cells, and the second voltage domain corresponds to a memory voltage domain that includes memory cells.

In aspects where the configuration of voltage level shifter 250 is similar to that of voltage level shifter 100, the components of voltage level shifter 250 may have similar functions as the corresponding components of voltage level shifter 100 sex, and therefore will

The operational details of voltage level shifter 250 are not repeated for the sake of brevity. Briefly, the pull-up transistors 202 , 204 , 206 , 210 and pull-down transistors 208 , 212 of the voltage level shifter 250 may be configured to match the corresponding pull-up transistors 102 , 104 , 106 , 110 and Pull-down transistors 108, 112 are similar. Thus, nodes 222 and 223 may be based on complementary input signals a 214 and a_n 216 in a similar manner as nodes 122 and 123 are based on the rise and fall of complementary input signals a 114 and a_n 116 as described in FIGS. 1A to B Rise and fall, receive the voltage converted to the second voltage domain.

[0029] Further, the circuit 200 may involve several modes of operation. For example, a normal mode of operation may be defined to include a situation where the first voltage source VDD1 is different (eg, less than or greater than) the second voltage source VDD2, and complementary input signals a 214 and a_n 216 are expected from the first voltage domain to Voltage level translation of the second voltage domain. In the normal mode, the functionality of voltage level shifter 250 may be substantially similar to that of voltage level shifter 100 .

[0030] The second mode of operation of the circuit 200 is defined as a bypass mode, wherein the first voltage source VDD1 is substantially the same as the second voltage source VDD2, and thus the complementary input signals a 214 and a_n 216 go from the first voltage domain to the second voltage source VDD2. Two-voltage domain voltage level translation can be avoided in bypass mode. The bypass mode may, for example, correspond to the previously mentioned acceleration mode, wherein the supply voltages of the first voltage domain (eg, the logic voltage domain) and the second voltage domain (eg, the memory voltage domain) may be equal or substantially the same. In this case, substantially equal should be understood by those skilled in the art to mean that the voltage difference between the first voltage domain and the second voltage domain is sufficiently small that the devices in the higher voltage domain that should be disconnected are not sufficiently turn on to cause unnecessary leakage current. In bypass mode, bypass circuit 252 may be employed to bypass voltage level shifter 250 and thereby avoid delays caused by complementary input signals a 214 and a_n 216 crossing voltage level shifter 250.

In some aspects, bypass circuit 252 may be implemented as a multiplexer or selector for: in bypass mode, selecting input signal a_n 216 as the output of bypass circuit 252; and in bypass mode In the normal mode, the node 222 presented as the intermediate signal y_n is selected as the output of the bypass circuit 252. To this end, bypass circuit 252 may include two emitter gate circuits 234 and 236, each formed by the parallel coupling of PFET and NFET devices. If the circuit 200 is to be operated in the bypass mode, then it can be asserted that the signal bypass 2320 is the complement of the bypass 232 shown as the signal bypass_n 230 . If bypass 232 is high, bypass_n 230 is low and transmit gate circuit 234 is turned on to pass a_n 216 to the output of bypass circuit 252 . On the other hand, if bypass 232 is low, bypass_n 230 is high and transmit gate circuit 236 is turned on to pass intermediate signal y_n (ie, node 222 ) to the output of bypass circuit 252 . The output of bypass circuit 252 is inverted by inverter 218 to appear as output signal z 220 of circuit 200 . Thus, in bypass mode, (eg, when bypass 232 is asserted based on the first and second supply voltages VDD1 and VDD2 being substantially the same), a_n 216 may be selected as the output of bypass circuit 252 while completely bypassing voltage level shifter 250 and corresponding delays.

[0032] FIGS. 2B-D illustrate exemplary aspects regarding a power down circuit that may be used for power conservation in bypass mode. As explained in detail in the following sections, the power down circuit may be selectively deployed when bypass 232 is asserted and voltage level shifter 250 is bypassed.

[0033] Referring first to FIG. 2B, a circuit 270 is illustrated according to an exemplary aspect of power saving in bypass mode. Circuit 270 includes a power down circuit 275 added to circuit 200 of Figure 2A. In more detail, circuit 270 also includes voltage level shifter 250 and bypass circuit 252 as discussed above with reference to FIG. 2A , and power down circuit 275 is coupled to voltage level shifter 250 as shown. In bypass mode, power down circuit 275 is configured to selectively power down voltage level shifter 250 when bypass 232 is asserted. But in normal mode, when bypass 232 is not asserted (or in other words, when bypass_n 230 is asserted), power down circuit 275 keeps voltage level shifter 250 active for normal operation. The power down circuit 275 will be explained in further detail below.

[0034] As shown, the power-down circuit 275 includes a first pull-down transistor 240 (eg, an NMOS transistor or NFET). With the gate of the first pull-down transistor 240 controlled by bypass_n 230, the first pull-down transistor 240 is connected in series to each of the pull-down transistors 208 and 212 of the voltage level shifter 250 and to ground. Thus, in normal mode, when bypass 232 is not asserted and bypass_n 230 is asserted, first pull-down transistor 240 is turned on, connecting the sources of pull-down transistors 208 and 212 to ground, thereby maintaining voltage level shifting The normal configuration of the regulator 250, or in other words, causes the voltage level shifter 250 to remain active. On the other hand, in bypass mode, bypass 232 is asserted, causing bypass_n 230 to be driven low and turn off the first pull-down transistor 240, which in turn, turns off the paths of pull-down transistors 208 and 212 to ground and causes the voltage Flat shifter 250 is powered down.

[0035] The power-down circuit 275 may also include a first pull-up transistor 242 (eg, a PMOS transistor or PFET), but this may be optional. When included in the power-down circuit 275, the first pull-up transistor 242 is connected to the intermediate signal y_n (or node 222) of the voltage level shifter 250 and the second supply voltage VDD2, along with the gate of the first pull-up transistor 242 Still controlled by bypass_n 230. In normal mode, bypass 232 is low and bypass_n 230 is asserted, thereby turning off the first pull-up transistor 242, which does not affect the normal configuration of the voltage level shifter 250. On the other hand, in bypass mode, bypass 232 is asserted, causing bypass_n 230 to be driven low and turn on first pull-up transistor 242, thereby connecting node 222 to the second supply voltage VDD2 and turning off the pull-up transistor 204. Thus, it can be seen that, when included, the first pull-up transistor 242 does not cause the node 222 to float in bypass mode (by connecting the node 222 to the second supply voltage VDD2 ), which results in a back-coupled in the bypass circuit 252 reduced, thereby improving the performance of circuit 270 in bypass mode. Accordingly, the power supply from the second voltage source VDD2 to the pull-up transistor 210 and the pull-down transistor 212 is also cut off in the bypass mode.

Thus, in bypass mode when bypass_n 230 is asserted, the combined effect of turning off the first pull-down transistor 240 and turning on the first pull-up transistor 242 is to connect all switching transistors of the voltage level shifter 250 to The power supplies are isolated, thereby powering down the voltage level shifter 250 . Therefore, when the voltage level shifter 250 is bypassed (eg, when the first supply voltage VDD1 and the second VDD2 are substantially the same), the voltage level shifter 250 is also powered down, resulting in power savings.

In the case where the power-down circuit 275 does not include the first pull-up transistor 242, the intermediate signal y_n coupled to the node 222 will be caused to float during bypass mode, but the voltage level shifter 250 will remain powered down, This is because the first pull-down transistor 240 will be turned off as previously described. Not including the first pull-up transistor 242 in the power-down circuit 275 may reduce the area associated with the power-down circuit 275 .

[0038] Subsequently, with reference to FIG. 2C, a circuit 280 is illustrated according to another exemplary aspect of power saving in bypass mode. Similar to circuit 270, circuit 280 also includes a power-down circuit added to circuit 200 of FIG. 2A, which in this case is identified as power-down circuit 285. In more detail, circuit 280 also includes voltage level shifter 250 and bypass circuit 252 as discussed above with reference to FIG. 2A , and power down circuit 285 is coupled to voltage level shifter 250 as shown. In bypass mode, power down circuit 285 is configured to selectively power down voltage level shifter 250 when bypass 232 is asserted. But in normal mode, when bypass 232 is not asserted (or in other words, when bypass_n 230 is asserted), power down circuit 285 keeps voltage level shifter 250 active for normal operation. The power down circuit 285 will be explained in further detail below.

[0039] As shown, the power-down circuit 285 includes a second pull-up transistor 282 coupled between the second supply voltage VDD2 and the voltage level shifter 250 (eg, to pull up the voltage power as shown) transistors 202 and 204 of the flat shifter 250 ), along with the gate of the second pull-up transistor 282 is controlled by the bypass 232 . In bypass mode, when bypass 232 is high, second pull-up transistor 282 is turned off, thereby turning off the voltage supply from second supply voltage VDD2 to voltage level shifter 250 and causing node 222 and signal y_n float. Additionally, in the normal mode, bypass 232 is low causing the second pull-up transistor 282 to be turned on and the second supply voltage VDD2 to be connected to the voltage level shifter 250 normally.

The power-down circuit 285 may optionally include a second pull-down transistor 284 (eg, an NMOS transistor or NFET) connected to the node 222 of the voltage level shifter 250, with the gate of the second pull-down transistor 284 being bypassed 232 controls. When second pull-down transistor 284 is configured in this way, in bypass mode, when bypass 232 is high, second pull-down transistor 284 is turned on, connecting node 222 or signal y_n to ground or a logic "0". Thus, second pull-down transistor 284 may also prevent node 222 from floating in bypass mode, reducing backside coupling in bypass circuit 252, thereby improving the performance of circuit 280 in bypass mode. In normal mode, bypass 232 is low causing second pull-down transistor 284 to be turned off, removing any effect on node 222 or signal y_n.

[0041] Referring now to FIG. 2D, a circuit 290 is illustrated according to yet another exemplary aspect of power conservation in bypass mode. Similar to circuits 270 and 280 , circuit 290 also includes a power-down circuit added to circuit 200 of FIG. 2A , which in this case is identified as power-down circuit 295 . In more detail, circuit 290 also includes voltage level shifter 250 and bypass circuit 252 as discussed above with reference to FIG. 2A , and power down circuit 295 is coupled to voltage level shifter 250 as shown. In bypass mode, power down circuit 295 is configured to selectively power down voltage level shifter 250 when bypass 232 is asserted. But in normal mode, when bypass 232 is not asserted (or in other words, when bypass_n 230 is asserted), power down circuit 295 keeps voltage level shifter 250 active for normal operation. The power down circuit 295 will be explained in further detail below.

[0042] As shown, the power-down circuit 295 also includes a second pull-up transistor 282 configured similarly to the power-down circuit 285 described above, and is coupled at the second supply voltage VDD2 and a voltage level shifter A second pull-up transistor 282 between 250 (eg, to the pull-up transistors 202 and 204 of the voltage level shifter 250 as shown), with the gate of the second pull-up transistor 282 controlled by the bypass 232. In bypass mode, when bypass 232 is high, second pull-up transistor 282 is similarly turned off, thereby turning off the voltage supply from second supply voltage VDD2 to voltage level shifter 250, resulting in node 222 and Signal y_n floats. Additionally, in normal mode, bypass 232 is low, causing second pull-up transistor 282 to be turned on, and causing second supply voltage VDD2 to be normally coupled to voltage level shifter 250.

[0043] The power-down circuit 295 also includes a third pull-down transistor 294 coupled between the voltage level shifter 250 and ground, with the gate of the third pull-down transistor 294 being controlled by the bypass_n 230. In bypass mode, when bypass_n 230 is low, the third pull-down transistor 294 is turned off, thereby turning off the ground path of the voltage level shifter 250 . Additionally, bypass_n 230 is high in normal mode, causing the third pull-down transistor 294 to be turned on, and causing the voltage level shifter 250 to be normally coupled to ground.

The power-down circuit 295 may optionally include one of the following two: a fourth pull-down transistor 296 or a fourth pull-up transistor 298 (but not both) connected to the node of the voltage level shifter 250 222. If the fourth pull-down transistor 296 is included in the power-down circuit 295 , the gate of the fourth pull-down transistor 296 is controlled by the bypass 232 . In bypass mode, when bypass 232 is high, fourth pull-down transistor 296 is turned on, thereby connecting node 222 to ground or a logic "0". In normal mode, bypass 232 is low causing fourth pull-down transistor 296 to be turned off, removing any effect on node 222 or signal y_n.

[0045] On the other hand, if the fourth pull-up transistor 298 is included in the power-down circuit 295, the gate of the fourth pull-up transistor 298 is controlled by the bypass_n 230. In bypass mode, when bypass_n 230 is low, the fourth pull-up transistor 298 is turned on, thereby connecting the AND node 222 to the second supply voltage VDD2 or a logic "1". In normal mode, bypass_n 230 is high, causing fourth pull-up transistor 298 to be turned off, removing any effect on node 222 or signal y_n. As should be appreciated, when either fourth pull-down transistor 296 or fourth pull-up transistor 298 is included in power-down circuit 295, as configured above, node 222 is prevented from floating in bypass mode, which creates a bypass circuit The backside coupling in 252 is reduced, thereby improving the performance of circuit 290 in bypass mode.

Thus, in an exemplary aspect, circuits such as circuits 270, 280, or 290 may be configured with power-down circuits 275, 285, or 295, respectively, to avoid when voltage level shifter 250 is not used in bypass mode Power consumption. Circuits 270, 280 and 290 also include bypass circuit 252 to avoid delays across the voltage level shifters in bypass mode.

[0047] Entry into bypass mode, for example, to assert bypass 232, may involve detecting that the first and second voltage sources VDD1 and VDD2 become substantially the same voltage value. This detection can be performed by methods and systems known in the art. For example, the battery level or state of charge of a battery-operated mobile device can be used to enter or exit bypass mode. To illustrate, if the mobile device is plugged into an external power source, or the battery level is high (or above a certain level), the mobile device can be programmed to support a high-efficiency or boost mode, where the first and second voltage sources VDD1 and VDD2 can be become substantially the same. However, if the battery power falls below a predetermined level to the low battery power mode, then, for example, the separated voltage levels of the first and second voltage sources VDD1 and VDD2 may be maintained and the bypass mode may be exited. The digital and/or analog circuitry may be configured to detect battery charge or connection to an external power source to accordingly provide an indication of whether bypass mode can be selected or whether normal operating conditions apply to the voltage level shifter. In some instances, the programmer or operating system may also provide software controls that can be used to enter or exit bypass mode. Those skilled in the art will recognize various other options for detection or determination of bypass modes (eg, assert bypass 232 ), and thus will not discuss them in greater detail here.

[0048] It should be appreciated that the exemplary aspects include various methods for performing the processes, functions and/or algorithms disclosed herein. For example, as illustrated in FIG. 3, exemplary aspects may include a method (300) of performing voltage level translation. The method 300 may include block 302, which may, for example, pertain to the normal mode of operation of the circuit 270, 280 or 290, and block 303, which may, for example, pertain to the bypass mode of operation of the circuit 270, 280 or 290. Figure 3 shows a bidirectional arrow between blocks 302 and 303 to indicate that a transition from normal mode to bypass mode or from bypass mode to normal mode is possible as the case may be. These blocks 302 and 303 will be elaborated further below.

[0049] As mentioned, block 302 may relate to a normal mode of operation, wherein the first supply voltage VDD1 of the first voltage domain is different from the second supply voltage VDD2 of the second voltage domain. In the normal mode, block 302 may include, in the normal mode, eg, in the voltage level shifter 250, converting an input signal, eg, the input signal a 214 in the first voltage domain, to an output signal, eg, a second voltage The output signal z 220 in the domain.

[0050] Block 303 may relate to a bypass mode of operation in which the first and second supply voltages VDD1 and VDD2 are substantially the same. Block 303 may include blocks 304 and 306, which may be performed concurrently.

[0051] As such, block 304 may include in bypass mode, bypassing the voltage level shifter, and providing the input signal as the output signal in the first voltage domain. For example, block 304 may include bypassing the voltage level shifter 250 using the bypass circuit 252 when the bypass 232 is asserted, and providing the input signal as the output signal in the first voltage domain.

[0052] Block 306 may include selectively powering down the voltage level shifter in bypass mode. For example, block 306 may include power-down voltage level shifter 250 (eg, power-down circuit 275, 285, or 295 is used, depending on whether an implementation is selected for circuit 270, 280, or 290 in the exemplary aspect). In particular, using any of the power down techniques discussed herein, voltage level shifter 250 may be powered down in bypass mode (when bypass 232 is high and bypass_n 230 is low), and the voltage level Converter 250 may remain active in normal mode (when bypass 232 is low and bypass_n 230 is high). In this manner, method 300 can be used to avoid delays and power associated with voltage level shifter 250 in circuits 270 , 280 or 290 when bypass 232 is asserted in bypass mode.

[0053] Referring now to FIG. 4, a block diagram of certain illustrative aspects of a computing device is depicted that includes circuits for efficient power voltage level translation, such as circuits 270, 280, or 290, and is generally designated 400. Computing device 400 may include a

The functionality of the method 300 discussed above with reference to FIG. 3 is performed. Furthermore, in some aspects, computing device 400 may be configured as a wireless communication device.

Computing device 400 is shown as including processor 464 and memory 432. In some aspects, processor 464 may belong to a first or logic voltage domain having a first supply voltage VDD1, while memory 432 may belong to a second or memory voltage domain having a second supply voltage VDD2. Accordingly, the schematic diagrams of the circuits 270 , 280 or 290 described above with reference to FIGS. 2B-D are shown configured between the processor 464 and the memory 432 . Circuitry 270/280/290, for example, may use voltage level shifter 250 in the normal mode to perform the processing of input signal a 214 (eg, corresponding to a read/write command from processor 464 to memory 432) to output signal z 220. Voltage level translation. Circuits 270/280/290 may be configured to bypass and power down voltage level shifters 250 using bypass circuits 252 and corresponding power down circuits 275/285/295 to provide complementary inputs from processor 464 in bypass mode Signals a 214 and a_n 216 are output as signal z 220 (without voltage level shifting) to memory 432, where the first and second supply voltages VDD1 and VDD2 are substantially the same in bypass mode. As mentioned previously, the bypass mode may correspond to an acceleration mode known in the art. It should be noted that for clarity, circuit 270/ The representation of 280/290 omits various details corresponding to those shown in FIGS. 2B-D.

Computing device 400 may also include a display controller 426 coupled to processor 464 and display 428. FIG. 4 also illustrates optional aspects that may be provided in computing device 400 . For example, a computing device may optionally include an encoder/decoder (codec) 434 (eg, an audio and/or speech codec) coupled to the processor 464 , along with the codec 434 and a wireless controller 440 (which may include a modem) coupled to the processor 464, along with a wireless controller 440 coupled to a wireless antenna 442.

In example aspects in which one or more of the above-described optional features exist, a processor 464, circuits 270/280/290, memory 432, codec 434, display controller 426, and wireless controller 440 may be included in the system in a package-at-a-package or system-on-chip device 422 . In some aspects, the input device 430 and the power supply 444 may be coupled to the system-on-chip device 422 (where it should also be noted that the first and second voltage sources VDD1 and VDD2 may in some cases originate from or be supplied by the power supply 444), while in some aspects display 428, input device 430, speaker 436, microphone 438, wireless antenna 442, and power supply 444 may be external to system-on-chip device 422. However, each of display 428, input device 430, speaker 436, microphone 438, wireless antenna 442, and power supply 444 may be coupled to a component of system-on-chip device 422, such as an interface or controller.

It should be noted that although FIG. 4 generally depicts a computing device, the processor 464 and memory 432 may also be integrated into set-top boxes, music players, video players, entertainment units, navigation devices, communication devices, personal digital assistants ; PDA), fixed location data units, mobile phones, servers and computers.

[0058] Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and information that may be referenced throughout the foregoing description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Chip.

[0059] Additionally, those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0060] The methods, sequences and/or algorithms described in the aspects disclosed herein may be directly in hardware, to be executed by a processor

The software modules or the combination of hardware and software modules are embodied. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral with the processor. [0061] Accordingly, one aspect of the present invention can include a computer-readable medium embodying a method for efficient power voltage level translation. Thus, the present invention is not limited to the illustrated examples and any means for performing the functionality described herein is included in aspects of the present invention.

[0062] While the foregoing disclosure shows illustrative aspects of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the aspects of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.