Power efficient voltage level translator circuit

High-efficiency power voltage level converter circuit technology field

[0001] The disclosed aspects relate to voltage power supplies for processing systems. More specifically, the exemplary aspect is directed to a high-efficiency power voltage level shifter circuit for voltage level conversion between a first voltage domain and a second voltage domain.

Background technique

[0002] A modern processing system (for example, a system-on-chip or "SOC") may include a variety of subsystems or components, which may have different frequency and power considerations. Correspondingly, different parts of the SOC can have different supply voltages. For example, a memory system may include a memory unit (for example, a static random access memory or "SRAM" unit), which may be supplied with a higher power supply voltage, and a central processing unit (CPU) or processor core The logic unit may support a lower supply voltage. Therefore, the SOC can be designed to have two or more than two voltage islands or voltage domains (for example, logic voltage domain, memory voltage domain, etc.), and each voltage domain has components (for example, logic cells, The corresponding voltage power supply considering the voltage of the memory cell, etc.).

[0003] There may be a signal across two voltage domains, for example, a read or write command issued by the CPU in the logic voltage domain to the memory system in the memory voltage domain. For such a signal, a conversion circuit, which is called a "voltage level converter" in the art, may be provided to convert the signal from the first voltage domain to the second voltage domain. However, in some cases, the voltages of one or more voltage domains can be dynamically scaled, which can result in the supply voltages of the first and second voltage domains being equal or substantially the same (for example, in "acceleration mode", as in It is known in the art, where the previous low supply voltage of the logic voltage domain can be scaled to a higher supply voltage to operate the logic unit at a higher frequency, and where the higher supply voltage of the logic voltage domain can be substantially equal to the memory voltage The power supply voltage of the domain is the same). In this case, there will be no need for a voltage level shifter between the first and second voltage domains, because the supply voltages of the first and second voltage domains are substantially the same.

[0004] However, in a conventional design, the voltage level shifter may still be activated, and the voltage conversion of the signal between the first and second voltage domains may be performed unnecessarily, even if the power supply of the first and second voltage domains is The voltages are roughly the same. By remaining active and in the signal path, the voltage level shifter always consumes power and adds delay in the signal path, even when voltage level shifting is not needed.

Summary of the invention

[0005] Exemplary aspects of the present invention are directed to systems and methods for high-efficiency power voltage level shifters. In the normal mode where the first supply voltage of the first voltage domain is different from the second supply voltage of the second voltage domain, the voltage level converter converts the input signal in the first voltage domain into the first voltage domain The output signal. In a bypass mode where the first supply voltage and the second supply voltage are substantially the same, the bypass circuit is configured to bypass the voltage level shifter and provide the The input signal is used as the output signal, thereby avoiding the delay introduced by the voltage level shifter in the bypass mode. Further, the power down circuit is configured to power down the voltage level shifter in the bypass mode, but not to do so in the normal mode.

[0006] For example, an exemplary aspect is directed to a device that includes: a voltage level shifter configured to provide a first supply voltage in a first voltage domain and a second power supply in a second voltage domain In normal mode with different voltages, switch

The input signal in the first voltage domain is an output signal in the second voltage domain; and a bypass circuit is configured to provide a bypass circuit where the first power supply voltage and the second power supply voltage are substantially the same. In the bypass mode, bypassing the voltage level shifter, and providing the input signal as the output signal in the first voltage domain; and a power-down circuit configured to be in the bypass mode , But not in the normal mode, power off the voltage level converter.

[0007] Another exemplary aspect is a method for voltage level conversion. The method includes: in a normal mode in which a first supply voltage of a first voltage domain is different from a second supply voltage of a second voltage domain, In the level shifter, the input signal in the first voltage domain is converted into an output signal in the second voltage domain; in the bypass mode where the first supply voltage and the second supply voltage are substantially the same , Bypassing the voltage level shifter and providing the input signal as the output signal in the first voltage domain; and in the bypass mode, but not in the normal mode, power off the station The voltage level converter.

[0008] Yet another exemplary aspect is directed to a device, which includes: a method for converting the first power supply voltage in a first voltage domain in a normal mode that is different from a second power supply voltage in a second voltage domain. A device in which an input signal in a voltage domain is an output signal in the second voltage domain; a device for bypassing the bypass mode in which the first supply voltage and the second supply voltage are substantially the same And a device for providing the input signal as the output signal in the first voltage domain; and for turning off the power station in the bypass mode but not in the normal mode The voltage level converter device.

Description of the drawings

[00091 The accompanying drawings are presented to assist in describing aspects of the present invention, and the accompanying drawings are provided only to illustrate the aspects and not to limit the aspects.

[0010] Figures 1A to B illustrate a conventional voltage level shifter.

[0011] FIGS. 2A to D illustrate circuits related to voltage level shifters according to exemplary aspects of the present invention.

[0012] FIG. 3 illustrates a block diagram corresponding to a method of performing voltage level conversion according to an exemplary aspect of the present invention.

[0013] FIG. 4 illustrates an exemplary computing device in which aspects of the present invention may be advantageously utilized.

Detailed ways

[0014] Various aspects of the present invention are disclosed in the following description and related drawings for specific aspects of the present invention. Alternative aspects can be devised without departing from the scope of the invention. In addition, well-known elements of the present invention will not be described in detail or omitted so as not to obscure relevant details of the present invention.

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" need not be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the invention" does not require that all aspects of the invention include the discussed feature, advantage, or mode of operation.

[0016] The terms used herein are only for the purpose of describing specific aspects, and are not intended to limit aspects of the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms "aAn" and "the" are also intended to include the plural forms. It will be further understood that the terms "including" and/or "including" when used herein designate the existence of the recited features, integers, steps, operations, elements, and/or components, but do not exclude one or more other features The existence or addition of, integers, steps, operations, elements, components, and/or groups thereof.

[0017] In addition, many aspects are described in terms of the order of actions to be performed by, for example, the elements of a computing device. It will be recognized that the various actions described herein can be implemented by specific circuits (eg, application specific integrated circuits (application specific integrated circuits)).

integrated circuit; ASIC)), executed by program instructions being executed by one or more processors or by a combination of the two. In addition, the sequence of actions described herein can be regarded as all embodied in any form of computer-readable storage medium, in which a corresponding set of computer instructions is stored, and the computer instructions are being executed. This time will cause the associated processor to perform the functionality described herein. Therefore, the various aspects of the present invention can be embodied in several different forms, and all forms are expected to fall within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspect may be described herein as, for example, "logic" that is "configured to" perform the described action.

[0018] Exemplary aspects of the present disclosure are directed to a voltage level shifter configured to convert a signal from a first voltage domain to a second voltage domain. In the case that the first voltage domain is equal to the second voltage domain, a selective bypass circuit is included to bypass the voltage level shifter to avoid voltage level shifting in the signal path between the first and second voltage domains Delay introduced by the device. Furthermore, in an exemplary aspect, a power control circuit may be included to power down or turn off the voltage level shifter when the voltage level shifter is skipped in the above-described manner. Therefore, in an exemplary aspect, when the voltage level shifter is not needed in the signal path, the power consumption and delay associated with the voltage level shifter can be avoided. These and related aspects will now be explained in the following sections with reference to the diagrams.

[0019] First, referring to FIGS. 1A to B, a conventional voltage level shifter 100 will be described. The voltage level shifter 100 is configured to convert the complementary input signals a 114 and a_n 116 in the first voltage domain supplied by the first supply voltage VDD1 to the output signal ζ 120 in the second voltage domain supplied by the second supply voltage VDD2. Without loss of generality, under normal operating conditions, the first supply voltage VDD1 may be less than the second voltage source VDD2, and in some examples, the first and second voltage sources VDD1 and VDD2 may be substantially the same voltage value. Although the first and second voltage sources VDD1 and VDD2 may adopt different values of specific conditions or the manner in which these voltage sources are generated is not closely related to this discussion, an example may involve a processor core including a processing system with logic units, etc. The first voltage domain in which the first voltage source VDD1 may be referred to as a logic supply voltage; and the second voltage domain including a memory system with memory cells, where the second voltage source VDD2 may be referred to as a memory supply voltage.

[0020] In the configuration illustrated in FIGS. 1A to B, the voltage level shifter 100 includes: pull-up transistors 102 and 104, which may be configured with a P-channel metal oxide semiconductor (P^_channel metal oxide semiconductor; PMOS) device or p-channel field effect transistor (PFET); pull-down transistors 108 and 112, which may be configured with n-channel metal oxide semiconductor (n-channel metal oxide semiconductor; NMOS) devices or n-channel field effect transistors (NFETs); and pull-up transistors 106 and 110, which can be configured as PMOS devices or PFETs. The output of the voltage level conversion of the complementary input signals a 114 and a_n 116 can be derived from the node 122, which passes through the inverter 118 to provide an output signal ζ 120. Although the operational details of the voltage level shifter 100 as illustrated in FIGS. 1A to B are well known, some brief details will be provided in the following sections, keeping in mind that various other configurations of the voltage level shifter may be applied to this Exemplary aspects of the disclosure.

[00211 Referring to FIG. 1A, it is illustrated that the input signal a 114 rises or transitions from a low logic state (e.g., binary "0") to a high logic state (e.g., binary "1"), and correspondingly, and the input signal a__n 116 cases of decline. Correspondingly, in the first stage, the pull-up transistor 106 will start to turn off, and the pull-down transistor 108 will start to turn on, which starts to discharge the node 122. On the other side, the input signal a_n 116 drops at the same time when the pull-up transistor 110 is turned on, and the pull-down transistor 112 is turned off. Once the node 122 drops to a sufficiently low value, then in the second stage, the pull-up transistor 104 is turned on, and the pull-up transistors 104 and 110 begin to charge the node 123 to the second supply voltage VDD2.

[0022] As the node 123 is charged, the pull-up transistor 102 starts to turn off, and its auxiliary pull-down transistor 108 further pulls down the node.

Point 122. The pull-down node 122 assists the process in which the pull-up transistor 104 is turned on, which further charges the node 123. Finally, the pull-up transistor 102 is completely turned off, the node 122 transitions to the logic state "0", and the node 123 transitions to the logic "Γ" in the second voltage domain. The nodes 122 and 123 maintain their logic states "0" and "Γ, Until the values of the complementary input signals a 114 and a_n 116 continuously change.

[0023] Therefore, after passing through the inverter 118, the inverted value of the node 122 appears as the output signal ζ 120, which rises in the second voltage domain, corresponding to the rise and input of the input signal a 114 in the first voltage domain. The signal a_n 116 falls. The above-identified stage of the voltage level shifter 100 introduces a corresponding delay or delay in the path between the complementary input signals 114 and a_n 116 and the output signal ζ 120.

[0024] Referring now to FIG. 1B, the reverse scenario will now be described in which the input signal a 114 falls and a_n 116 rises. In this case, the pull-up transistor 110 will start to turn off, and the pull-down transistor 112 will start to turn on, thereby discharging node 123. On the other side, when the pull-up transistor 106 is turned on, as the input signal a 114 drops, the pull-down transistor 108 is turned off. Once the node 123 drops to a sufficiently low value, in the second stage, the pull-up transistor 102 is turned on, and the pull-up transistors 102 and 106 start to charge the node 122 to the second supply voltage VDD2. As the node 122 is charged, the pull-up transistor 104 starts to turn off, and its auxiliary pull-down transistor 112 further pulls down the node 123. The pull-down node 123 assists the process in which the pull-up transistor 102 is turned on, which further charges the node 122. Finally, the pull-up transistor 104 is completely turned off, and the node 123 transitions to the logic state "0", and the node 122 transitions to the logic state "1" in the second voltage domain. The logic state of the node 122 is inverted by the inverter 118 to appear as a falling output signal ζ 120 in the second voltage domain. The nodes 122 and 123 maintain their logic states "Γ and "0", respectively, until the complementary input signals a 114 and a_n 116 undergo continuous transitions. As can be seen, the above-identified stages involved in the operation of the voltage level shifter 100 are the same in this situation Causes a significant delay.

[0025] For the case where the difference between the voltage values of the first and second supply voltages VDD1 and VDD2 is large, the stack of the pull-up transistors 102 and 106 on the left side of the voltage level shifter 100 can be thinned to The pull-down transistor 108 is allowed, for example, to effectively pull down the node 122 when the input signal a 114 rises (or transitions from low to high) and the input signal a_n 116 falls (or transitions from high to low) accordingly. Similarly, the stack of pull-up transistors 104 and 110 on the right side of the voltage level shifter 100 can be thinned to allow the pull-down transistor 112 to effectively fall in the input signal a 114 and correspondingly the input signal a_n 116 rises. Pull down node 123. This relative size of the pull-down and pull-up transistors can further increase the delay from the complementary input signals a 114 and a_n 116 and the output signal ζ 120.

[0026] From the above discussion of the voltage level shifter 100, it can be understood that in the two cases shown in FIGS. 1A to B, a considerable delay is introduced. In addition, the various stages of turning on and off of various pull-up and pull-down transistors also consume power. In the case where the first voltage source VDD1 of the first voltage domain is substantially the same as the second voltage source VDD2 of the second voltage domain, in the exemplary aspects that will now be discussed with reference to FIGS. 100 related delays and power can be avoided.

[0027] Referring to FIG. 2A, a circuit 200 is shown, which includes a voltage level shifter 250 and a bypass circuit 252. The voltage level shifter 250 can be configured to be compatible with the conventional voltage level shifter 100 described with reference to FIGS. 1A to B, or any other complementary input signal in the first voltage domain that is suitable for converting the first voltage source VDD1. 214 and a_n 216 supply the second voltage source VDD2 for the voltage level converter of the intermediate output signal y_n derived from the node 222 in the second voltage domain. In an example aspect, the first voltage domain corresponds to a logic voltage domain including logic cells, and the second voltage domain corresponds to a memory voltage domain including memory cells.

[0028] In aspects where the configuration of the voltage level converter 250 is similar to that of the voltage level converter 100, the components of the voltage level converter 250 may have similar functions to the corresponding components of the voltage level converter 100 Sex, and therefore will

The operational details of the voltage level converter 250 are not repeated for the sake of brevity. Briefly, the pull-up transistors 202, 204, 206, 210 and the pull-down transistors 208, 212 of the voltage level shifter 250 can be configured to correspond to the corresponding pull-up transistors 102, 104, 106, 110 and 110 of the voltage level shifter 100. The pull-down transistors 108 and 112 are similar. Therefore, the nodes 222 and 223 can be used in a similar manner to the nodes 122 and 123 based on the rise and fall of the complementary input signals a 114 and a_n 116 as described in FIGS. 1A to IjB. Rise and fall, receive the voltage converted to the second voltage domain.

[0029] Further, the circuit 200 may involve several modes of operation. For example, the normal operating mode can be defined as including the case where the first voltage source VDD1 is different from (for example, less than or greater than) the second voltage source VDD2, and it is expected that the complementary input signals a 214 and a_n 216 are from the first voltage domain to The voltage level conversion of the second voltage domain. In the normal mode, the functionality of the voltage level shifter 250 may be substantially similar to that of the voltage level shifter 100.

[0030] The second operation mode of the circuit 200 is defined as a bypass mode, in which the first voltage source VDD1 is substantially the same as the second voltage source VDD2, and therefore the complementary input signals a 214 and a_n 216 go from the first voltage domain to the first voltage source VDD2. The voltage level conversion of the two voltage domains can be avoided in the bypass mode. The bypass mode may for example correspond to the previously mentioned acceleration mode, in which the supply voltages of the first voltage domain (for example, the logic voltage domain) and the second voltage domain (for example, the memory voltage domain) may be equal or substantially the same. In this case, substantially equal should be understood by those skilled in the art as the voltage difference between the first voltage domain and the second voltage domain is sufficiently small, so that the device that should be disconnected in the higher voltage domain is not sufficiently grounded. Turn on to cause unnecessary leakage current. In the bypass mode, the bypass circuit 252 can be used to bypass the voltage level shifter 250 and thereby avoid the delay caused by the complementary input signals a 214 and a_n 216 crossing the voltage level shifter 250.

[00311 In some aspects, the bypass circuit 252 can be implemented as a multiplexer or selector for: in the bypass mode, select the input signal a_n 216 as the output of the bypass circuit 252; and in the normal In the mode, the node 222 presented as the intermediate signal y_n is selected as the output of the bypass circuit 252. To this end, the bypass circuit 252 may include two emission gate circuits 234 and 236, each formed by the parallel coupling of PFET and NFET devices. If the circuit 200 is to be operated in bypass mode, then the signal bypass 232 can be asserted_oThe complement of bypass 232 is shown as signal bypass_n 230. If bypass 232 is high, then bypass_n 230 is low, and transmit gate circuit 234 is turned on to pass the output of a_n 216 to bypass circuit 252. On the other hand, if bypass 232 is low, bypass_n 230 is high, and transmit gate circuit 236 is turned on to pass intermediate signal y_n (ie, node 222) to the output of bypass circuit 252. The output of the bypass circuit 252 is inverted by the inverter 218 to appear as the output signal ζ 220 of the circuit 200. Therefore, in the bypass mode, (for example, when the bypass 232 is asserted based on the first and second supply voltages VDD1 and VDD2 being substantially the same), a_n 216 can be selected as the output of the bypass circuit 252 while completely bypassing Overvoltage level shifter 250 and corresponding delay.

[0032] FIGS. 2B to D illustrate exemplary aspects regarding a power down circuit that can be used for power saving in bypass mode. As explained in detail in the following sections, the power-down circuit can be selectively deployed when bypass 232 is asserted and voltage level shifter 250 is bypassed.

[0033] Referring first to FIG. 2B, the circuit 270 is illustrated according to an exemplary aspect of power saving in the bypass mode. The circuit 270 includes a power-down circuit 275 added to the circuit 200 of FIG. 2A. In more detail, the circuit 270 also includes a voltage level shifter 250 and a bypass circuit 252 as discussed above with reference to FIG. 2A, and as shown, the power down circuit 275 is coupled to the voltage level shifter 250. In the bypass mode, when bypass 232 is asserted, the power down circuit 275 is configured to selectively power down the voltage level converter 250. But in the normal mode, when the bypass 232 is not asserted (or in other words, when the bypass_n 230 is asserted), the power-down circuit 275 keeps the voltage level shifter 250 active for normal operation. The power-down circuit 275 will be described in further detail below.

[0034] As shown, the power-down circuit 275 includes a first pull-down transistor 240 (eg, NMOS transistor or NFET). Accompanying the gate of the first pull-down transistor 240 is_SS_n 230 control, the first pull-down transistor 240 is connected in series to each of the pull-down transistors 208 and 212 of the voltage level shifter 250 and grounded. Therefore, in normal mode, when bypass 232 is not asserted and bypass_SSWhen _n 230 is asserted, the first pull-down transistor 240 is turned on, which connects the source terminals of the pull-down transistors 208 and 212 to ground, thereby maintaining the normal configuration of the voltage level shifter 250, or in other words, causing the voltage level The level converter 250 remains activated. On the other hand, in the bypass mode, bypass232 is asserted, causing bypass_n 230 to be driven low, and turning off the first pull-down transistor 240, which in turn turns off the path of pull-down transistors 208 and 212 to ground, and causes the voltage to flow. The level converter 250 is powered off.

[0035] The power-down circuit 275 may also include a first pull-up transistor 242 (for example, a PMOS transistor or a PFET), but this may be optional. When included in the power-down circuit 275, the first pull-up transistor 242 is connected to the intermediate signal y_n (or node 222) of the voltage level shifter 250 and the second supply voltage VDD2, accompanied by the gate of the first pull-up transistor 242 It is still controlled by bypass_n 230. In the normal mode, the bypass 232 is low and the bypass_n 230 is asserted, thereby turning off the first pull-up transistor 242, which does not affect the normal configuration of the voltage level converter 250. On the other hand, in the bypass mode, bypass 232 is asserted, resulting in bypass_n 230 being driven low, and turning on the first pull-up transistor 242, thereby connecting node 222 to the second supply voltage VDD2 and turning off the pull-up transistor 204. Therefore, it can be seen that when included, the first pull-up transistor 242 does not cause the node 222 to float in the bypass mode (by connecting the node 222 to the second supply voltage VDD2), which results in the backside coupling of the bypass circuit 252 Reduction, thereby improving the performance of circuit 270 in bypass mode. Accordingly, the power supply from the second voltage source VDD2 to the pull-up transistor 210 and the pull-down transistor 212 is also cut off in the bypass mode. [0036] Therefore, in bypa_SSIn the bypass mode when _n 230 is asserted, the combined effect of turning off the first pull-down transistor 240 and turning on the first pull-up transistor 242 is to isolate all the switching transistors of the voltage level converter 250 from the power supply. Thus, the voltage level converter 250 is powered off. Therefore, when the voltage level shifter 250 is bypassed (for example, when the first supply voltage VDD1 and the second VDD2 are substantially the same), the voltage level shifter 250 is also powered off, resulting in power saving.

[0037] In the case that the power-down circuit 275 does not include the first pull-up transistor 242, the intermediate signal y_n coupled to the node 222 will float during the bypass mode, but the voltage level converter 250 will still remain powered down. This is because the first pull-down transistor 240 will be turned off as previously described. Not including the first pull-up transistor 242 in the power-down circuit 275 can reduce the area related to the power-down circuit 275.

[0038] Subsequently, referring to FIG. 2C, the circuit 280 is illustrated according to another exemplary aspect of power saving in the bypass mode. Similar to the circuit 270, the circuit 280 also includes a power-down circuit added to the circuit 200 of FIG. 2A, which in this case is identified as the power-down circuit 285. In more detail, the circuit 280 also includes a voltage level shifter 250 and a bypass circuit 252 as discussed above with reference to FIG. 2A, and as shown, the power down circuit 285 is coupled to the voltage level shifter 250. In the bypass mode, when bypass 232 is asserted, the power-down circuit 285 is configured to selectively power down the voltage level shifter 250. But in the normal mode, when the bypass 232 is not asserted (or in other words, when the bypass_n 230 is asserted), the power-down circuit 285 keeps the voltage level shifter 250 active for normal operation. The power-down circuit 285 will be described in further detail below.

[0039] As shown, the power-down circuit 285 includes a second pull-up transistor 282 coupled between the second supply voltage VDD2 and the voltage level shifter 250 (for example, to pull up the voltage as shown The transistors 202 and 204 of the level converter 250), along with the gate of the second pull-up transistor 282, are controlled by the bypass 232. In bypass mode, when bypa_SSWhen 232 is high, the second pull-up transistor 282 is turned off, thereby shutting off the voltage supply from the second supply voltage VDD2 to the voltage level shifter 250, and causing the node 222 and the signal y_n to float. In addition, in normal mode, bypa_SSWhen 232 is low, the second pull-up transistor 282 is turned on, and the second supply voltage VDD2 is normally connected to the voltage level converter 250.

[0040] The power-down circuit 285 may optionally include a second pull-down transistor 284 (eg, NMOS transistor or NFET) connected to the node 222 of the voltage level shifter 250, with the gate of the second pull-down transistor 284 being bypassed. 232 control. When the second pull-down transistor 284 is configured in this way, in the bypass mode, when the bypass 232 is high, the second pull-down transistor 284 is turned on, connecting the node 222 or the signal y_n to ground or logic "0". Therefore, the second pull-down transistor 284 can also prevent the node 222 from floating in the bypass mode, reducing the backside coupling in the bypass circuit 252, thereby improving the performance of the circuit 280 in the bypass mode. In the normal mode, the bypass 232 is low causing the second pull-down transistor 284 to be turned off, removing any influence on the node 222 or the signal y_n.

[00411 Now referring to FIG. 2D, the circuit 290 is illustrated according to yet another exemplary aspect of power saving in the bypass mode. Similar to the circuits 270 and 280, the circuit 290 also includes a power-down circuit added to the circuit 200 of FIG. 2A, which in this case is identified as the power-down circuit 295. In more detail, the circuit 290 also includes a voltage level shifter 250 and a bypass circuit 252 as discussed above with reference to FIG. 2A, and as shown, the power down circuit 295 is coupled to the voltage level shifter 250. In the bypass mode, when bypass 232 is asserted, the power down circuit 295 is configured to selectively power down the voltage level converter 250. But in the normal mode, when the bypass 232 is not asserted (or in other words, when the bypass_n230 is asserted), the power-down circuit 295 keeps the voltage level shifter 250 active for normal operation. The power-down circuit 295 will be described in further detail below.

[0042] As shown, the power-down circuit 295 also includes a configuration similar to the second pull-up transistor 282 of the power-down circuit 285 described above, and is coupled to the second supply voltage VDD2 and the voltage level converter The second pull-up transistor 282 between 250 (for example, to the pull-up transistors 202 and 204 of the voltage level converter 250 as shown), and the gate of the second pull-up transistor 282 is controlled by the bypass 232. In the bypass mode, when bypass 232 is high, the second pull-up transistor 282 is similarly turned off, thereby shutting off the voltage supply from the second supply voltage VDD2 to the voltage level shifter 250, resulting in nodes 222 and The signal y_n floats. In addition, in the normal mode, the bypass 232 is low, which causes the second pull-up transistor 282 to be turned on, and causes the second supply voltage VDD2 to be normally coupled to the voltage level shifter 250.

[0043] The power-down circuit 295 also includes a third pull-down transistor 294 coupled between the voltage level shifter 250 and the ground, and the gate of the third pull-down transistor 294 is controlled by the bypass_n 230. In the bypass mode, when bypass_n 230 is low, the third pull-down transistor 294 is turned off, thereby turning off the ground path of the voltage level shifter 250. In addition, in the normal mode, bypass_n 230 is high, causing the third pull-down transistor 294 to be turned on, and causing the voltage level shifter 250 to be normally coupled to ground.

[0044] The power-down circuit 295 may optionally include one of the following two: a fourth pull-down transistor 296 or a fourth pull-up transistor 298 (but not both), which is connected to the node of the voltage level shifter 250 222. If the fourth pull-down transistor 296 is included in the power-down circuit 295, the gate of the fourth pull-down transistor 296 is controlled by the bypass 232. In the bypass mode, when bypass 232 is high, the fourth pull-down transistor 296 is turned on, thereby connecting node 222 to ground or logic "0". In the normal mode, the bypass 232 is low causing the fourth pull-down transistor 296 to be turned off, removing any influence on the node 222 or the signal y_n.

[0045] On the other hand, if the fourth pull-up transistor 298 is included in the power-down circuit 295, the gate of the fourth pull-up transistor 298 is controlled by the bypass_n 230. In the bypass mode, when bypass_n 230 is low, the fourth pull-up transistor 298 is turned on, thereby connecting the node 222 to the second supply voltage VDD2 or logic "Γ. In the normal mode, bypa_SS_ η 230 is high, causing the fourth pull-up transistor 298 to be turned off, removing any influence on the node 222 or the signal y_n. As should be understood, when either of the fourth pull-down transistor 296 or the fourth pull-up transistor 298 is included in the power-down circuit 295, as configured above, the node 222 is prevented from floating in the bypass mode, which creates a bypass circuit The back coupling in the 252 is reduced, thereby improving the performance of the circuit 290 in the bypass mode.

[0046] Therefore, in an exemplary aspect, circuits such as circuits 270, 280, or 290 may be configured with power-down circuits 275, 285, or 295, respectively, to avoid when the voltage level shifter 250 is not used in bypass mode Power consumption. Circuits 270, 280, and 290 also include a bypass circuit 252 to avoid the delay through the voltage level shifter in bypass mode.

[0047] In the case of entering the bypass mode, for example, in order to assert the bypass 232, it may involve detecting that the first and second voltage sources VDD1 and VDD2 become substantially the same voltage value. This detection can be performed by methods and systems known in the art. For example, the battery level or charging state of a battery-operated mobile device can be used to enter or exit the bypass mode. To illustrate, if the mobile device is plugged into an external power source, or the battery level is high (or higher than a certain level), then the mobile device can be programmed to support high-efficiency or acceleration mode, where the first and second voltage sources VDD1 and VDD2 can be It becomes substantially the same. However, if the battery power drops below a predetermined level to the low battery power mode, for example, the separated voltage levels of the first and second voltage sources VDD1 and VDD2 can be maintained, and the bypass mode can be exited. The digital and/or analog circuits can be configured to detect battery power or connection to an external power source to provide an indication of whether the bypass mode can be selected or whether the normal operating state is applicable to the voltage level shifter accordingly. In some instances, the programmer or operating system may also provide software controls that can be used to enter or exit bypass mode. Those skilled in the art will recognize various other options for detection or determination of bypass mode (eg, assert bypass 232), and therefore will not discuss them in more detail here.

[0048] It should be understood that exemplary aspects include various methods for performing the processes, functions, and/or algorithms disclosed herein. For example, as illustrated in FIG. 3, exemplary aspects may include a method of performing voltage level conversion (300). The method 300 may include a block 302, for example, regarding the normal operating mode of the circuit 270, 280, or 290, and a block 303, which may, for example, regarding the bypass operating mode of the circuit 270, 280, or 290. FIG. 3 shows the two-way arrow between the boxes 302 and 303 to indicate that it is possible to transit from the normal mode to the bypass mode, or from the bypass mode to the normal mode, as the case may be. These blocks 302 and 303 will be described in further detail below.

[0049] As mentioned, block 302 may be related to a normal operating mode, where the first supply voltage VDD1 of the first voltage domain is different from the second supply voltage VDD2 of the second voltage domain. In the normal mode, block 302 may include, in the normal mode, for example in the voltage level converter 250, converting the input signal, for example, the input signal a 214 in the first voltage domain, to the output signal, for example, the second voltage. The output signal ζ 220 in the domain.

[0050] Block 303 may be related to a bypass mode of operation, where the first and second supply voltages VDD1 and VDD2 are substantially the same. Block 303 may include blocks 304 and 306, which may be performed simultaneously.

[00511 As such, block 304 may include in the bypass mode, bypassing the voltage level shifter, and providing the input signal as the output signal in the first voltage domain. For example, block 304 may include bypassing the voltage level converter 250 using the bypass circuit 252 when the bypass 232 is asserted, and providing the input signal as the output signal in the first voltage domain.

[0052] Block 306 may include selectively powering down the voltage level shifter in bypass mode. For example, block 306 may include power-down voltage level shifter 250 (eg, power-down circuit 275, 285, or 295 is used depending on whether the implementation for circuit 270, 280, or 290 is selected in an exemplary aspect). Specifically, using any of the power-off techniques discussed in this article, the voltage level converter 250 can be powered off in the bypass mode (when bypass 232 is high and bypass_n 230 is low), and the voltage level The converter 250 can remain active in the normal mode (when bypass 232 is low and bypass_SS_n 230 is high). In this way, the method 300 can be used in bypass mode, when bypass 232 is asserted, avoiding the delay and power associated with the voltage level shifter 250 in the circuit 270, 280, or 290.

[0053] Referring now to FIG. 4, a block diagram of a specific illustrative aspect of a computing device is depicted, which includes circuits for efficient power voltage level conversion, such as circuits 270, 280, or 290, and is generally denoted as 400. The computing device 400 may include

The functionality of the method 300 discussed above with reference to FIG. 3 is performed. Furthermore, in some aspects, the computing device 400 may be configured as a wireless communication device.

[0054] The computing device 400 is shown as including a processor 464 and a memory 432. In some aspects, the processor 464 may belong to a first or logical voltage domain with a first supply voltage VDD1, and the memory 432 may belong to a second or memory voltage domain with a second supply voltage VDD2. Therefore, the schematic diagrams of the circuits 270, 280, or 290 described with reference to FIGS. 2B to D above are shown as being configured between the processor 464 and the memory 432. The circuit 270/280/290, for example, can use the voltage level converter 250 in the normal mode to execute the input signal a 214 (for example, corresponding to the read/write command from the processor 464 to the memory 432) to the output signal ζ 220. Voltage level conversion. Circuits 270/280/290 can be configured to use bypass circuit 252 and corresponding power-down circuits 275/285/295 to bypass and power-down voltage level converter 250 to provide complementary input from processor 464 in bypass mode The signals a 214 and a_n 216 are used as the output signal ζ 220 (without voltage level conversion) to the memory 432, wherein the first and second supply voltages VDD1 and VDD2 are substantially the same in the bypass mode. As mentioned previously, the bypass mode may correspond to an acceleration mode known in the art. It should be noted that for clarity, the circuit 270/ in Figure 4 The representation of 280/290 is omitted corresponding to the various details shown in FIGS. 2B to D.

[0055] The computing device 400 may also include a display controller 426 coupled to the processor 464 and the display 428. FIG. 4 also shows optional aspects that may be provided in the computing device 400. For example, the computing device may optionally include an encoder/decoder (codec) 434 (eg, an audio and/or speech codec) coupled to the processor 464, along with being coupled to the codec 434 A speaker 436 and a microphone 438; and a wireless controller 440 (which may include a modem) coupled to the processor 464, accompanied by a wireless controller 440 coupled to the wireless antenna 442.

[0056] In an example aspect where one or more of the above optional features exist, the processor 464, the circuit 270/280/290, the memory 432, the codec 434, the display controller 426, and the wireless controller 440 may be included in the system In-level packaging or system-on-chip device 422. In some aspects, the input device 430 and the power supply 444 may be coupled to the system-on-chip device 422 (wherein it should also be noted that the first and second voltage sources VDD1 and VDD2 may be derived from or by the power supply in some cases 444 power supply), and in some aspects, the display 428, input device 430, speaker 436, microphone 438, wireless antenna 442, and power supply 444 may be external to the system-on-chip device 422. However, each of the display 428, input device 430, speaker 436, microphone 438, wireless antenna 442, and power supply 444 may be coupled to a component of the system on chip device 422, such as an interface or a controller.

[0057] It should be noted that although FIG. 4 roughly depicts a computing device, the processor 464 and the memory 432 may also be integrated in a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, and a personal digital assistant (personal digital assistant). ;PDA), fixed location data units, mobile phones, servers and computers.

[0058] Those skilled in the art should understand that any of a variety of different techniques and techniques can be used to represent information and signals. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles or any combination thereof can be used to represent data, instructions, commands, information, signals, bits, symbols, and symbols that may be referred to throughout the above description. Chip.

[0059] In addition, those skilled in the art should understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have generally been described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of the present invention.

[0060] The methods, sequences and/or algorithms described in the aspects disclosed herein may be directly executed by hardware or by a processor

The software module or the combination of hardware and software modules. The software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. [0061] Accordingly, an aspect of the present invention may include a computer-readable medium embodying a method for efficient power voltage level conversion. Therefore, the present invention is not limited to the illustrated examples, and any means for performing the functionality described herein is included in the aspects of the present invention.

[0062] Although the foregoing disclosure shows illustrative aspects of the invention, it should be noted that various changes and modifications can be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims according to the aspects of the invention described herein need not be performed in any specific order. In addition, although the elements of the present invention may be described or claimed in the singular form, the plural form is also encompassed unless it is explicitly stated that they are limited to the singular form.