Chip having four filters operating with surface acoustic waves

Chip with four filters operating with surface acoustic waves

[0001] This application is a divisional application of the invention patent application with the application number 201180053281.1, the filing date 2011-11-3, and the title of the invention "a chip with four filters operated by surface acoustic waves".

Technical field

[0002] The present invention relates to a chip having four filters that operate with surface acoustic waves.

Background technique

[0003] A module is known that has four SAW (Surface Acoustic Wave) filters, and also has a duplexer at its input and output ports, so that in each case two input ports and two Output port to drive four filters.

Summary of the invention

[0004] The purpose of the present invention is to simplify the known modules and optimize them for cost and space requirements.

[0005] This is achieved by a chip as described below and by a package as described below. The advantageous embodiments of the present invention can be found in other records of this application.

[0006] According to the present invention, a chip is proposed that has four filters that operate with surface acoustic waves and input and output ports. Each filter covers a different frequency band. Each of the input and output ports is connected to one or two filters. The four filters are arranged on the chip as follows: two filters form the left column, and the remaining two filters form the right column; two of the four filters each from one column And two relatively positioned filters are each connected to an output port provided between two filters opposite to each other, the two input ports including a first input port and a second input port, the Each of the two input ports is connected to one of the four filters connected to the first output port of the two output ports and to the second output port of the two output ports The other one of the four filters connected; and the two filters are coupled to the first of the two input ports, and the remaining two filters are coupled to the two The second one of the input ports, one of the two filters and one of the remaining two filters are used to respectively come from one of the low frequency bands, and in the two filters One of and one of the remaining two filters are used for one frequency band from the high frequency band; and each of the four filters is The receiving filter of the receiving circuit. The present invention also provides a package including: four filters operated by surface acoustic waves, and the four filters are arranged in such a way that two of the four filters form a left column, and the remaining The two filters form the right column, where two of the four filters each from one column are arranged to face each other, and the filters are arranged on two or more chips; each of the four filters One covers a different frequency band; each of the four filters is a receiving filter of the receiving circuit, and two relatively positioned filters are each connected to an output port arranged between two filters opposite to each other; The chip has two input ports and two output ports, the two input ports include a first input port and a second input port, and the two output ports include a first output port and a second output port; Each of the input ports is connected to one of the four filters connected to the first output port and the other of the four filters connected to the second output port ;

And the two filters are coupled to the first of the two input ports, the remaining two filters are coupled to the second of the two input ports, the two filters One of the filters and one of the remaining two filters are used to respectively come from one of the low frequency bands, and one of the two filters and one of the remaining two filters One is used for each frequency band from the high frequency band.

[0007] Furthermore, a particularly advantageous arrangement of filters on the chip can be selected. For this purpose, four filters are arranged on the chip as follows: two filters form the left column, and the remaining two filters form the right column, and two filters from different columns are arranged opposite to each other .

[0008] The input and/or output ports can be connected to two filters. In this case, they form a duplexer.

[0009] If the chip has two input ports connected to two filters each forming a duplexer in each case, the two filters in the left column can be connected to the first input port, and the two filters in the right column Two filters can be connected to the second input port.

[0010] If the chip has two output ports connected to two filters each forming a duplexer in each case, the two relatively positioned filters can each be connected to two filters arranged opposite to each other. The output port between the converters.

[0011] If the duplexer functionality of four filters operating with surface acoustic waves is integrated in one chip, it is possible to achieve distinct advantages for space requirements in this way.

[0012] This chip can be used in the transmission and reception circuits of mobile phones. If the input and/or output ports of the chip are then set as duplexers, the remaining components of the transmission and reception circuit can be simplified. For example, if the input ports of the four filters are set as duplexers, the component has only two input ports instead of four input ports. The input port is usually connected to the antenna separately, optionally via a switch. Setting the chip to have only two input ports makes it possible to use less complicated and correspondingly more advantageous switches for distinguishing the received frequency bands. On the output side, the number of signal lines between the chip and the receiving circuit is reduced by half due to the duplex output port.

[0013] Each of the two input ports is advantageously connected to a filter connected to the first output port and a filter connected to the second output port.

[0014] In the first embodiment of the present invention, four SAW filters are arranged in a row on a common chip substrate.

[0015] In the second embodiment, four filters are arranged in the form of a 2×2 matrix on the chip. In this arrangement, the two filters form the left column and the remaining two filters form the right column, the two filters in the left column are connected to the first input port, and the two filters in the right column are connected to the second input port. Two filters each from a different column are arranged to face each other in this case, and the two filters facing each other are each connected to an output port arranged between the two filters facing each other.

[0016] Compared with the first embodiment, this second embodiment has some advantages. On the one hand, it is possible to avoid the crossing of signal lines on the chip. In addition, the arrangement of the filter according to the second embodiment makes it possible to construct a chip whose length and width ratio has more favorable characteristics. The chip according to the first embodiment only has a large length, but on the other hand has a small width. In the case of the chip according to the second embodiment, the ratio of the length to the width is close to one.

[0017] The aspect ratio of the second embodiment corresponds to, for example, a standard form used in the case of a 2-in-1 (2 in 1) filter chip. In the market, many dual-band mobile phones are known in which a 2-in-1 filter chip with two SAW filters for two different frequency bands is used. The chip according to the second embodiment of the present invention has the same size and thus the same aspect ratio as the known 2-in-1 filter chip. Therefore, it is possible to replace the 2-in-1 filter chip with the 4-in-1 filter chip according to the present invention without much expense, and thus upgrade the dual-band mobile phone to form a quad-band mobile

Telephone. In contrast, if a 4-in-1 filter chip having a large length and a small width according to the first illustrative embodiment is used, a greater change in circuit board design is required.

[0018] Since the size of the second illustrative embodiment corresponds to a standard form, existing tools can be used for production as well as for testing chips.

[0019] In addition, the second embodiment has better mechanical stability due to the changed length to width ratio. Since the chip according to the second embodiment has a length to width ratio close to one, it is specifically less sensitive to deformation caused by temperature fluctuations. In the chip according to the first illustrative elastic embodiment, the mechanical stress can be increased. Since in the chip according to the second embodiment, the absolute size has been reduced in terms of length, the mechanical stress that can rise due to thermal deformation is reduced. Improved mechanical stability leads to better reliability and reduced failure probability.

[0020] Therefore, the advantages of the chip according to the second embodiment are a more compact layout, improved reliability, and the possibility of using existing tools.

[0021] The frequency space can be divided into a high frequency band and a low frequency band. The definition of high and low frequency bands depends on the standard used in each case and is completely arbitrary at first. One possible definition is to allocate frequencies below 1 GHz to the low frequency band, and frequencies above 1 GHz to the high frequency band. In the following, this definition is used as a basis, but the present invention is not limited to this definition.

[0022] Two of the four SAW filters each cover a frequency band in the high frequency band, and the remaining two SAW filters each cover a frequency band in the low frequency band. In this case, the first input port can be connected to a filter covering the first frequency band in the high frequency band and a filter covering the first frequency band in the low frequency band. Accordingly, the second input port can be connected to a filter covering the second frequency band in the high frequency band and a filter covering the second frequency band in the low frequency band.

[0023] On the output side, the first output port can be connected to two filters covering two frequency bands in the high frequency band, and the second output port can be connected to two filters covering two frequency bands in the low frequency band .

[0024] The filter can cover, for example, four GSM frequency bands. These can be the GSM 850 and GSM 900 frequency bands in the low frequency band and the GSM 1800 and GSM 1900 frequency bands in the high frequency band. However, the present invention is not limited to filters used in the GSM band. The invention can also include, for example, filters for frequency bands defined in accordance with the UMTS standard.

[0025] The output ports can be balanced or single-ended. The filter can be a ladder or DMS filter or a mixture of the two.

[0026] The chip can also have matching elements, which make it possible to match the frequency characteristics of the filters with each other. Especially when two filters form a duplexer, this is decisive. In this case, each filter should reflect signals that are within the passband range of the other filter in each case.

[0027] For the purpose of matching, an inductor and a capacitor can be arranged between the two filters on the chip. It is possible to realize this inductance and capacitance through resonators. In addition, the input port can be connected to an external coil. In addition, for example, by using an inductor made of copper, other matching components can be implemented on the chip.

[0028] The chip substrate can be quartz, lithium niobate or lithium tantalate.

[0029] The invention also relates to a package with a chip according to the invention. This package preferably also presents one or more inductances, especially copper coils, for improved duplexer separation. The inductor can be provided on the surface of the package or integrated into the substrate of the package.

[0030] The present invention also relates to a package in which four filters operating with surface acoustic waves are provided in the second embodiment described above, and each filter covers a different frequency band. In this arrangement, the four filters are arranged in such a way that two filters form the left column, and the remaining two filters form the right column. Two filters each from one column

Each is set to face each other.

[0031] The filter can be provided on two or more chips. The chip can include different substrate materials. The filters are preferably distributed on two chips. The filters forming the left column are arranged on the first chip, and the filters forming the right column are arranged on the second chip. The two chips are positioned opposite to each other.

[0032] Furthermore, each of the two chips can have an input port connected to the two filters of the chip. These two chips form a duplexer. This arrangement corresponds to the illustrative embodiment described above, in which two filters each form an input duplexer. However, in contrast to the above illustrative embodiment, the four filters are now distributed on two separate chip substrates.

[0033] The package can have two output ports, and each of the output ports can be individually connected to one filter on each of the two chips. In this case, the two filters each form a duplexer, the first filter is provided on one chip, and the second filter is provided on the other chip.

[0034] Therefore, the package according to the current claim 18 substantially corresponds to the chip according to the current claim 2, with only the filter distributed over two or more chips.

Description of the drawings

[0035] Hereinafter, the present invention will be explained in more detail with reference to illustrative embodiments and associated drawings. The drawings illustrate different illustrative embodiments of the invention by graphical representations that are not full scale.

[0036] Figure 1 shows a graphical representation of a transmitting and receiving circuit.

[0037] FIG. 2 shows a graphical representation of a first illustrative embodiment of a chip.

[0038] FIG. 3 shows a graphical representation of a second illustrative embodiment of a chip.

[0039] FIG. 4 shows the insertion loss and the standing wave ratio of the first filter F1.

[0040] FIG. 5 shows the insertion loss and the standing wave ratio of the second filter F2.

[0041] FIG. 6 shows the insertion loss and the standing wave ratio of the third filter F3.

[0042] FIG. 7 shows the insertion loss and the standing wave ratio of the fourth filter F4.

[0043] FIG. 8 shows the package.

[0044] Figure 9 shows an advantageous package.

[0045] FIG. 10 shows a graphical representation of another variation of the second illustrative embodiment of the chip.

Detailed ways

[0046] FIG. 1 shows a graphical representation of a transmitting and receiving circuit connecting an antenna 1 to an RF circuit 2 in a mobile phone. The transmitting and receiving circuit has four signal paths SP1, SP2, SP3, SP4, the upper two signal paths SP1, SP2 form a receiving circuit, and the lower two signal paths SP3, SP4 form a transmitting circuit. The two signal paths SP1 and SP2 of the receiving circuit are respectively connected to one input port EP1 and EP2 of the chip CH.

[0047] The chip CH has four SAW filters F1, F2, F3, F4, two input ports EP1, EP2, and two output ports AP1, AP2. At the input ports EP1, EP2, two filters are interconnected in each case to form a duplexer. Therefore, each of the two input ports EP1, EP2 is respectively connected to the two SAW filters F1, F3 and F2, F4 in each case. The output ports AP1, AP2 are also embodied as duplexers, and in each case are cross-connected to two SAW filters F1, F2 and F3, F4, respectively. In addition, the output ports AP1 and AP2 are balanced here, so that the chip has a total of four output terminals AP1a, AP1b, AP2a, AP2b, and two output terminals AP1a, AP1b and AP2a, AP2b form one in each case.

Two output terminals DAP1 and AP2.

[0048] The antenna 1 can optionally be connected to one of the two signal paths SP1 and SP2 of the receiving circuit via the switch S, and each of the two signal paths SP1 and SP2 leads to one of the input terminals DEPhEPZ of the chip. one. On the output side, the output terminal DAPhAPZ of the chip is connected to two low noise amplifiers LNA1 and LNA2.

[0049] In addition, the antenna 1 can be connected to one of the two transmission paths SP3 and SP4 of the transmission circuit via the switch S. Each transmission path SP3, SP4 has preamplifiers VV1 and VV2, main amplifiers HV1 and HV2, and low-pass amplifiers LPF1 and LPF2.

[0050] FIG. 2 shows the arrangement of SAW filters F1, F2, F3, F4 in the chip CH according to the present invention according to the first illustrative embodiment. The two input terminals DEP1 and EP2 are located on the input side. The first input terminal DEP1 is connected to filters F1 and F3. The second input terminal DEP2 is connected to filters F2 and F4. The filters F1 and F2 are filters for the frequency band in the high frequency band, and the filters F3 and F4 are filters for the frequency band in the low frequency band. These can be, for example, frequency bands defined in accordance with the GSM standard. Filter F1 is designed for the GSM frequency band of 1960 MHz, and filter F2 is designed for the GSM frequency band of 1842.5 MHz. Correspondingly, these two frequency bands are both in the high frequency band. The filters F3 (942.5 MHz) and F4 (881.5 MHz) cover the frequency band according to the GSM standard and are located in the low frequency band.

[0051] However, the present invention is by no means limited to the frequency band according to the GSM standard. The four filters F1, F2, F3, F4 can also be designed for four frequency bands according to the UMTS standard, for example.

[0052] According to the first illustrative embodiment shown in FIG. 2, the four filters F1-F4 are DMS structures. In this context, each of the four filters F1-F4 is composed of a combination of two filter structures FS1a, DMS1b, FS2a, DS2b, FS3a, DMS3b, FS4a, and DMS4b, one of which can be a DMS structure. composition.

[0053] The configuration of this filter consisting of two filter structures is discussed by the first filter F1. Other filters F2, F3, F4 can have similar filter structures.

[0054] The first filter structure FS1a of the first filter F1 is a series resonator. The output of the first filter structure FS1a is here simultaneously connected to the structural unit of the second filter structure DMS1b via three parallel signal lines SL1, SL2, SL3.

[0055] The second filter structure DMS1b is a DMS structure, and has three coupling converters and two output converters. The signal lines SL1, SL2, SL3 connected to the output of the first filter structure FS1 are connected to the coupling converter in each case. The outputs AO1, AO2 of the two output converters of the DMS structure DMS1b are connected to one output terminal AP1, AP2 of the chip CH in each case. In this arrangement, the first output terminal DAP1 is each connected to one of the filters F1 and F2. The first output terminal DAP1 has two output terminals AP1a, AP1b, and is set to be balanced. The second output terminal DAP2, which also has two output terminals AP2a and AP2b and is set to be balanced, is connected to the filters F3 and F4.

[0056] The arrangement shown here represents a simplification of the actual filter structure. The filter for the GSM 1900 MHz band can be formed by a series circuit of a resonator and a DMS filter structure having six IDTs. The resonator and the DMS filter respectively represent the first and second filter structures. The filter for the GSM 1800 MHz band can have series and parallel resonators as a first filter structure and a DMS filter structure with six IDTs as a second filter structure. The filter for the GSM 850 and 950 MHz frequency bands can have a DMS structure with three IDTs on the output side as the second filter structure and series and parallel resonators as the first filter structure. In addition, a further resonator can be used at the input between the duplex filters in order to provide improved matching.

[0057] If two filters form a duplexer, the frequency characteristics of the two filters must be matched with each other through a matching element. Signals located in the passband of one filter should be reflected by the other filter. On the input side of the chip, other components that provide corresponding matching of the filter can therefore be provided.

[0058] For example, an external coil connected to one of the input ports EP1'EPZ may be used. In addition, inductance and capacitance can be arranged between the two filters forming the duplexer. This combination of inductance and capacitance can also be achieved through resonators. The copper coil mounted on the chip CH can be used as a further matching element.

[0059] The present invention is by no means limited to the arrangement of SAW filters F1-F4 shown here. In addition to the DMS structure, the filters F1-F4 can also be configured as ladder-type filters, or a mixture of ladder-type and DMS filters is conceivable. In these contexts, the ladder structure is cascaded with the DMS structure.

[0060] The input terminals DEP1 and EP2 are respectively connected in each case to the filters F1 and F2 for the frequency band in the high frequency band and the filters F1 and F4 for the frequency band in the low frequency band, while one output The terminal DAP1 is connected to filters F1, F2 for one frequency band each from the high frequency band, and the other output terminal DAP2 is connected to filters F3, F4 for one frequency band each from the low frequency band. Correspondingly, in the chip CH according to this first embodiment, the crossing of the signal lines on the input side or the output side cannot be avoided.

[0061] FIG. 3 shows a second illustrative embodiment of the chip CH according to the present invention. The second illustrative embodiment differs from the illustrative embodiment shown in FIG. 2 specifically in the arrangement of the SAW filters F1-F4 on the chip substrate. The four filters F1F4 are now set in the form of a 2X2 matrix with two rows and two columns. The filters F1 and F2 form the first row, the filters F3 and F4 form the second row, and the filters F1 and F3 and the filters F2 and F4 respectively form a row U in each case. The filters F1 and F3 are arranged on the left side of the chip CH, and are connected to the first input terminal DEP1. The filters F2 and F4 are arranged on the right side and connected to the second input terminal DEPZ.

[0062] The terminals AP1a, AP1b, AP2a, and AP2b of the output terminal DAPjia APZ are respectively arranged between the filters F1-F4. The terminals AP1a and AP1b of the first output end DAP1 are arranged between the filter F1 and the filter F2. The terminals AP2a and AP2b of the second output terminal DAP2 are arranged between the filters F3 and F4, and are connected to the two filters F3 and F4. Here, the output ports AP1, AP2 are set to be balanced in each case.

[0063] Compared with the arrangement shown in FIG. 2, the arrangement of the filters F1-F4 according to the second illustrative embodiment presents some advantages. The chip CH is generally more compact, resulting in a more favorable ratio of length to width. This allows standard tools to be used to install and test the chip CH. In addition, no signal line crossing is required on the input side. There is also no signal crossing on the output side.

[0064] Therefore, signal crossing is avoided at the chip level. Only when the chip is connected to the pad of the package, the line crossing may occur on the output side.

[0065] The present invention is not limited to the embodiment of the chip shown here. Thus, for example, the acoustic tracks of each individual SAW filter F1F4 can be rotated 90 about their respective center points in the arrangement according to FIG. 3. . Correspondingly, the output of SAW filters F1-F4 will also rotate to different positions. In this case, it is possible to generate a shorter signal path for connecting the output terminals AP1a/b and AP2a/b to the terminals of the package.

[0066] FIG. 10 shows a graphical representation of one possible embodiment of the second illustrative embodiment. Therefore, this representation is described in more detail, specifically, the filter structure is more accurately decomposed.

[0067] The four SAW filters F1, F2, F3, and F4 are again arranged in a square shape on the chip. The filters F1-F4 form a 2X2 matrix, which are two filters F1 and F3 and F2 and F4 each arranged in a column. In addition, the filters F1 and F2 and the filters F3 and F4 respectively from different columns are arranged to face each other.

[0068] The two input terminals DEP1 and EP2 are located on the input side. The first input terminal DEP1 is connected to filters F1 and F3 forming a duplexer. The second input terminal DEP2 is connected to filters F2 and F4. The filters F1 and F2 are filters for the frequency band in the high frequency band, and the filters F3 and F4 are filters for the frequency band in the low frequency band. These can be, for example, frequency bands defined in accordance with the GSM standard. For example, the filter F1 is designed for the GSM frequency band of 1960MHz, and the filter F2 is designed for the 1842.5MHz frequency band.

GSM frequency band. Accordingly, both frequency bands are located in the high frequency band. The filters F3 (942.5MHz) and F4 (881.5MHz) cover the frequency band according to the GSM standard and are located in the low frequency band.

[0069] Each of the filters F1-F4 is composed of multiple filter structures. The filter F1 for the GSM band of 1900 MHz has a DMS structure DMS1a connected in series with the second filter structure FS1b. The first DMS structure DMS1a has two input converters and four coupling converters. The second filter structure FS1b has two resonators implemented as four-port resonators in this case. The output of the second filter structure FS1b of the first filter F1 is connected to the output terminals AP1a, AP1b of the first output terminal DAP1. The first output DAP1 is balanced. The two signal paths of the balancing operation are performed via the two-port resonator FS1b.

[0070] The second filter F2 for the GSM band of 1800 MHz is arranged opposite to the first filter F1. The second filter has three filter structures DMS2a, FS2b, and FS2c. The first filter structure of the second filter F2 is the DMS structure DMS2a, and has a total of six IDTs, two input converters, and four coupling converters. The DMS structure DMS2a is connected in series with the second filter structure FS2b. The second filter structure FS2b has two resonators here again implemented as four-port resonators. The third filter structure FS2c, which also has two resonators composed of four-port resonators, is connected in parallel with the second filter structure FS2b. The parallel two-port resonator FS2c is actually connected to ground, and on the input side, two balanced signals are connected to it. The output terminals AP1a and AP1b of the first output end DAP1 are connected in series with the second filter structure FS2b and connected in parallel with the third filter structure FS2c of the second filter F2.

[0071] The third filter F3 for the GSM band of 942.5 MHz forms a duplexer together with the first filter F1. The third filter F3 has three resonators FS3a, FS3b, FS3c and a DMS structure DMS3d. The first resonator FS3a is directly connected to the first input terminal DEP1. The third resonator FS3c is connected in series with the first resonator FS3a. In addition, the second resonator FS3b is connected to the ground in parallel between the first and third resonators. The third resonator FS3c is connected to the DMS structure DMS3d via three parallel signal lines, and the DMS3d has three coupling converters and two output converters. The two outputs of the DMS structure DMS3d are connected to one of the output terminals AP2a, AP2b of the second output terminal DAP2 in each case, and the second output terminal DAP2 is balanced.

[0072] The fourth filter F4 for the GSM band of 850 MHz is constructed similarly to the third filter F3. The fourth filter F4 also has three resonators FS4a, FS4b, FS4c and a DMS structure DMS4d. The first resonator FS4a is directly connected to the second input terminal DEP2. The output of the first resonator FS4a is also connected to the third resonator FS4c. The second resonator FS4b is connected in parallel to the ground between the first and third resonators. The third resonator FS4c is connected to the DMS structure DMS3d via three parallel signal lines, and the DMS3d has three coupling converters and two output converters. The two outputs of the DMS structure DMS4d are connected to one of the output terminals AP2a, AP2b of the second output terminal DAP2 in each case.

[0073] The present invention is by no means limited to the arrangement of the filters F1-F4 shown in FIG. 10 and the precise configuration of the filters F1-F4 shown here. Therefore, it is also possible within the scope of the present invention that the chip has four input ports and four output ports, and each filter F1-F4 is connected to exactly one input port and exactly one output port. Furthermore, each of the two filters can be interconnected so as to form a duplexer only on the input side or only on the output side.

[0074] FIG. 4 shows the insertion loss and the standing wave ratio of the first filter F1. The first filter F1 is designed for the GSM frequency band of 1960 MHz. The upper graph shows the insertion loss. It can be seen here that there is a very slight insertion loss in the passband between 1930 and 1990 MHz. In contrast, in the stop band, the insertion loss exceeds 35dB.

[0075] In the two lower graphs, the standing wave ratio is shown. The figure on the left shows the standing wave ratio on the input side of the filter. This diagram shows that the reflected signal becomes very low in the passband. The figure on the right shows the standing wave ratio on the output side. Here too, only very small signal components are reflected in the passband.

[0076] FIGS. 5 to 7 correspondingly show the insertion loss and the standing wave ratio of the input side and the output side of the filters F2, F3, and F4. The filter F2 is designed for the GSM band of 1842.5MHz. The filter F3 is designed for the GSM low frequency band of 942.5MHz. Filter F4 is designed for the GSM low frequency band of 881.5MHz.

[0077] FIG. 8 shows a graphical representation of a package PA with a chip CH according to the invention. The package PA has a rectangular basic shape with two long sides and two short sides, and the short sides form 90 with the long sides in each case. Horn.

[0078] The package PA also has eight pins Pin1-Pin8, which can be connected to the circuit board and other components via these pins. Four pins Pin1-Pin4 are arranged on the first long side, and four other pins Pin5-Pin8 are arranged on the opposite second long side.

[0079] Pin1 is generally used for the first input terminal DEP1, and Pin4 is used for the second input terminal DEP2. In addition, if the output terminal DAPjia APZ is single-ended, Pin5 and Pin8 are used to connect the two output ports AP1 and AP2. In the case of balanced output ports AP1 and AP2, Pin5 and Pin6 are used for the first output port DAP1, and Pin7 and Pin8 are used for the second output port AP2.

[0080] Pin2 and Pin3 can be used as a ground supply source.

[0081] FIG. 9 shows an improved arrangement of the package PA. Additionally, this package PA has two other pins Pin9 and Pin10 arranged on the short side of the package and two other pins Pin11 and Pin12 arranged on the opposite second short side.

<td>[0082]</td><td colspan="2">Pin9-Pin12 are used to connect the output ports AP1 and AP2 at this time. This configuration provides the following advantages: the output of the chip CH</td>

<td colspan="3">The outlet ports AP1 and AP2 can be connected to the terminals Pin9-Pin12 of the package PA via short symmetrical signal lines.</td>

<td>[0083]</td><td colspan="2">Reference number</td>

<td>[0084]</td><td>1 -</td><td>antenna</td>

<td>[0085]</td><td>2 -</td><td>RF circuit</td>

<td>[0086]</td><td>SP1</td><td>-The first signal pathway</td>

<td>[0087]</td><td>SP2</td><td>-Second signal pathway</td>

<td>[0088]</td><td>SP3</td><td>-Third signal pathway</td>

<td>[0089]</td><td>SP4</td><td>-The fourth signal path</td>

<td>[0090]</td><td>CH-</td><td>chip</td>

<td>[0091]</td><td>EP1</td><td>-The first input port</td>

<td>[0092]</td><td>EP2</td><td>-Second input port</td>

<td>[0093]</td><td>F1-</td><td>First filter</td>

<td>[0094]</td><td>F2-</td><td>Second filter</td>

<td>[0095]</td><td>F3-</td><td>Third filter</td>

<td>[0096]</td><td>F4-</td><td>Fourth filter</td>

<td>[0097]</td><td>AP1</td><td>-The first output port</td>

<td>[0098]</td><td>AP2</td><td>-Second output port</td>

<td>[0099]</td><td>AP1a</td><td>-The first terminal of AP1</td>

<td>[0100]</td><td>AP1b</td><td>-The second terminal of AP1</td>

<td>[0101]</td><td>AP2a</td><td>-The first terminal of AP2</td>

<td>[0102]</td><td>AP2b</td><td>-The second terminal of AP2</td>

<td>[0103]</td><td>S-</td><td>switch</td>

<td>[0104]</td><td>LNA1</td><td>-The first low noise amplifier</td>

<td>[0105]</td><td>LNA2</td><td>-Second Low Noise Amplifier</td>

<td>[0106]</td><td>VV1-</td><td>First preamplifier</td>

<td>[0107]</td><td>VV2-</td><td>Second preamplifier</td>

<td>[0108]</td><td>HV1-</td><td>First main amplifier</td>

<td>[0109]</td><td>HV2-</td><td>Second main amplifier</td>

<td>[0110]</td><td>LPF1</td><td>-The first low pass filter</td>

<td>[0111]</td><td>LPF2</td><td>-Second low pass filter</td>

<td>[0112]</td><td>FS1a</td><td>-F1's first filter structure</td>

<td>[0113]</td><td>DMS1b</td><td>-F1's second DMS structure</td>

<td>[0114]</td><td>FS2a</td><td>-F2's first filter structure</td>

<td>[0115]</td><td>DMS2b</td><td>-F2's second DMS structure</td>

<td>[0116]</td><td>FS3a</td><td>-F3's first filter structure</td>

<td>[0117]</td><td>DMS3b</td><td>-F3's second DMS structure</td>

<td>[0118]</td><td>FS4a</td><td>-F4's first filter structure</td>

<td>[0119]</td><td>DMS4b</td><td>-F4's second DMS structure</td>

<td>[0120]</td><td>SL1-</td><td>The first signal line</td>

<td>[0121]</td><td>SL2-</td><td>Second signal line</td>

<td>[0122]</td><td>SL3-</td><td>Third signal line</td>

<td>[0123]</td><td>AO1-</td><td>The first output of DMS1b</td>

<td>[0124]</td><td>AO2-</td><td>The second output of DMS1b</td>

<td>[0125]</td><td>PA-</td><td>Encapsulation</td>

<td>[0126]</td><td>Pin1</td><td>-The first pin.</td>