Chip having four filters operating with surface acoustic waves

Chip with four filters operating with surface acoustic waves

[0001] This application is a divisional application of an invention patent application with application number 201180053281.1, application date 2011-11-3, and the title of the invention “a chip with four filters operating with surface acoustic waves”.

Technical field

[0002] The present invention relates to a chip having four filters operating with surface acoustic waves.

Background technique

[0003] A module is known which has four SAW (surface acoustic wave) filters and also has diplexers at its input and output ports so that in each case it is possible to pass via two input ports and two Output port to drive four filters.

Summary of the Invention

[0004] It is an object of the present invention to simplify known modules and to optimize them for cost and space requirements.

This object is achieved by a chip as described below and by a package as described below. Advantageous embodiments of the present invention are found in other descriptions of this application.

According to the present invention, a chip is proposed that has four filters operating with surface acoustic waves and input and output ports. Each filter covers a different frequency band. Each of the input and output ports is connected to one or two filters. The four filters are arranged on the chip in such a way that two filters form the left column and the remaining two filters form the right column; two of the four filters each coming from a column Disposed opposite to each other; and two oppositely positioned filters are each connected to an output port disposed between two mutually opposing filters, the two input ports including a first input port and a second input port. Each of the two input ports is connected to one of the four filters connected to the first output port of the two output ports and to the second output port of the two output ports The other of the four filters connected; and the two filters are coupled to the first one of the two input ports, and the remaining two filters are coupled to the two a second one of the input ports, one of the two filters and one of the remaining two filters are used to respectively come from one of the low frequency bands, and the two filters One and One of said remaining two filters are used, respectively, in a frequency band from the high frequency band; and each of the four filter is a reception filter of the reception circuit. The present invention also provides a package including four filters that operate using surface acoustic waves, the four filters being arranged in such a way that two of the four filters form a left column and the remaining The two filters form the right column, where two of the four filters each from a column are arranged opposite to each other, the filters being arranged on two or more chips; each of the four filters One covers different frequency bands; Each of the four filters is a receiving filter of a receiving circuit, and two oppositely positioned filters are each connected to an output port disposed between two mutually opposing filters; the chip has two input ports And two output ports, the two input ports including a first input port and a second input port, the two output ports including the first output port and a cockpit outfall; and two of the input copper ports Each input port is connected to one of the four filters connected to the first output port and the other of the four filters connected to the second output port; and Two filters are coupled to the first one of the two input ports and the remaining two filters are coupled to a second one of the two input ports, of the two filters One of the sum of the two remaining filters is used for one of the bands from the low frequency band respectively, and one of the two filters and one of the remaining two filters are used From high frequency One frequency band in the band.

[0007] In addition, a particularly advantageous arrangement of filters on a chip can be selected. For this purpose, four filters are arranged on the chip in such a way that two filters form the left column, and the remaining two filters form the right column, and two filters each from different columns are arranged opposite to each other .

[0008] The input and/or output ports can be connected to two filters. In this case, they form a duplexer. [0009] If the chip has two input ports connected in each case to two filters each forming a duplexer, the two filters in the left column can be connected to the first input port and the right column Two filters can be connected to the second input port.

[0010] If the chip has two output ports connected in each case to two filters each forming a duplexer, the two oppositely located filters can each be connected to two mutually opposite filters. The output port between the devices.

[0011] If the diplexer functionality of the four filters operating with surface acoustic waves is integrated in one chip, it is possible to achieve distinct advantages for space requirements in this way.

[0012] This chip can be used in the transmission and reception circuits of mobile phones. If the chip's input and/or output ports are then set to diplexers, the remaining components of the transmit and receive circuits can be simplified. For example, if the input ports of the four filters are set to diplexers, the component has only two input ports instead of four input ports. The input port is usually connected to the antenna individually via a switch. Setting the chip with only two input ports makes it possible to use less complex and correspondingly more advantageous switches for distinguishing the received frequency band. On the output side, the number of signal lines between the chip and the receiving circuit is reduced by half due to the duplex output port.

Each of the two input ports is advantageously connected to a filter connected to the first output port and a filter connected to the second output port.

In a first embodiment of the invention, four SAW filters are arranged in rows on a common chip substrate.

In the second embodiment, four filters are set on the chip in the form of a 2×2 matrix. In this arrangement, two filters form the left column and the remaining two filters form the right column, two filters in the left column are connected to the first input port, and two filters in the right column are connected to the second input port. Two filters, each from a different column, are arranged opposite each other in this case, and two mutually opposing filters are each connected to an output port provided between two mutually opposing filters.

Compared with the first embodiment, this second embodiment has some advantages. On the one hand, the crossing of signal lines on the chip can be avoided. In addition, the arrangement of the filter according to the second embodiment makes it possible to construct a chip whose ratio of length and width has more favorable characteristics. The chip according to the first embodiment has only a very large length, but on the other hand has a small width. In the case of the chip according to the second embodiment, the ratio of length to width is close to one.

The aspect ratio of the second embodiment corresponds to a standard form used in the case of a 2 in 1 filter chip, for example. On the market, many dual-band mobile phones are known, in which a 2-in-1 filter chip with two SAW filters for two different frequency bands is used. The chip according to the second embodiment of the invention has the same dimensions as the known 2 in 1 filter chip and thus has the same aspect ratio. Therefore, it is possible to replace the 2 in 1 filter chip with the 4 in 1 filter chip according to the present invention without much cost, and thus upgrade the dual band mobile phone to form a quad-band mobile phone. In contrast, if a 4in1 filter chip with a large length and a small width according to the first illustrative embodiment is used, a larger change in circuit board design is required.

[0018] Since the dimensions of the second illustrative embodiment correspond to the standard form, existing tools can be used for production as well as for testing chips.

[0019] In addition, the second embodiment has better mechanical stability due to the changed ratio of length to width. Since the chip according to the second embodiment has a ratio of length to width of nearly one, specifically, it is less sensitive to deformation due to temperature fluctuations. In the chip according to the first illustrative elastic embodiment, the mechanical stress can rise. Since in the chip according to the second embodiment, the absolute size has been reduced in length, the mechanical stress that can rise due to thermal deformation is reduced. The improved mechanical stability leads to better reliability and reduced probability of failure.

[0020] Therefore, the advantages of the chip according to the second embodiment are a more compact layout, improved reliability, and the possibility of using existing tools.

[0021] The frequency space can be divided into a high frequency band and a low frequency band. The definition of high and low frequency bands depends on the criteria used in each case and is initially completely arbitrary. One possible definition is to assign frequencies below 1 GHz to the low band and frequencies above 1 GHz to the high band. In the following, this definition is used as a basis, but the invention is not limited to this definition.

[0022] Two of the four SAW filters each cover the frequency band in the high frequency band, and the remaining two SAW filters each cover the frequency band in the low frequency band. In this case, the first input port can be connected to a filter that covers a first frequency band in a high frequency band and a filter that covers a first frequency band in a low frequency band. Accordingly, the second input port can be connected to a filter that covers the second frequency band in the high frequency band and a filter that covers the second frequency band in the low frequency band.

[0023] On the output side, the first output port can be connected to two filters covering two frequency bands in the high frequency band, and the second output port can be connected to two filters covering two frequency bands in the low frequency band .

The filter can cover, for example, four GSM bands. These can be the GSM 850 and GSM 900 bands in the low band and the GSM 1800 and GSM 1900 bands in the high band. However, the invention is not limited to filters for the GSM band. The invention can also include a filter for eg a frequency band defined according to the UMTS standard.

The output port can be balanced or single-ended. The filter can be a ladder or DMS filter or a mixture of both.

[0026] The chip can also have matching elements that make it possible to match the frequency characteristics of the filters with each other. This is decisive especially when two filters form a duplexer. In this case, each filter should reflect the signal within the passband range of the other filter in each case.

[0027] For matching purposes, inductors and capacitors can be placed between the two filters on the chip. It is possible to implement this inductance and capacitance through a resonator. In addition, the input port can be connected to an external coil. In addition, other matching elements can be implemented on the chip, for example by using an inductor made of copper.

The chip substrate can be quartz, lithium niobate, or lithium niobate.

[0029] The invention also relates to a package with a chip according to the invention. Such a package preferably also presents one or more inductors, particularly copper coils, for improved duplexer separation. The inductor can be placed on the surface of the package or integrated into the packaged substrate.

[0030] The present invention also relates to a package in which four filters operating using surface acoustic waves are disposed in the above-described second embodiment, each filter covering a different frequency band. In this arrangement, four filters are set in such a way that two filters form the left column, and the remaining two filters form the right column. Two filters, one from each column, are each disposed opposite each other.

[0031] The filter can be disposed on two or more chips. The chip can include different substrate materials. The filters are preferably distributed on two chips. The filters forming the left column are disposed on the first chip, and the filters forming the right column are disposed on the second chip. The two chips are positioned opposite each other.

[0032] In addition, each of the two chips can have one input port, which is connected to the two filters of the chip. These two chips form a duplexer. This arrangement corresponds to the above illustrative embodiment, where the two filters each form an input duplexer. However, in contrast to the illustrative embodiment described above, the four filters are now distributed over two separate chip substrates.

[0033] The package can have two output ports, and each of the output ports can be individually connected to one filter on each of the two chips. In this case, the two filters each form a duplexer, the first filter is disposed on one chip, and the second filter is disposed on the other chip.

Accordingly, the package as claimed in the current claim 18 substantially corresponds to the chip as claimed in the current claim 2, only filters are distributed over two or more chips.

Description of the drawings

[0035] Hereinafter, the present invention will be described in more detail with reference to illustrative embodiments and associated drawings. The drawings show different illustrative embodiments of the invention by way of a pictorial representation that is not a solid scale.

[0036] FIG. 1 shows a graphical representation of a transmission and reception circuit.

[0037] FIG. 2 shows a graphical representation of a first illustrative embodiment of a chip.

[0038] FIG. 3 shows a graphical representation of a second illustrative embodiment of a chip.

FIG. 4 shows the insertion loss and the standing wave ratio of the first filter F1.

FIG. 5 shows the insertion loss and the standing wave ratio of the second filter F2.

[0041] FIG. 6 shows the insertion loss and the standing wave ratio of the third filter F3.

[0042] FIG. 7 shows the insertion loss and the standing wave ratio of the fourth filter F4.

[0043] FIG. 8 shows a package.

[0044] FIG. 9 shows an advantageous package.

[0045] FIG. 10 shows in a graphical representation another variation of a second illustrative embodiment of a chip.

DETAILED DESCRIPTION [0046] FIG. 1 shows a graphical representation of a transmit and receive circuit for connecting an antenna 1 to an RF circuit 2 in a mobile phone. The transmission and reception circuit has four signal paths 8?1, 3?2, 3?3, 3?4, the upper two signal paths 3?1, 3?2 form a receiving circuit, and the following two signal paths SP3, SP4 Form a transmission circuit. The two signal paths Spi, SP2 of the receiving circuit are each connected to one input port EP1, EP2 of the chip CH.

[0047] The chip CH has four SAW filters 1 {2/3,? 4 and two input ports 1 and 2 and two output ports API, AP2. At the input port EPKEP2, two filters are interconnected in each case to form a duplexer. Therefore, each of the two input ports EP1, EP2 is respectively connected to two SAW filters FI, F3 and F2, F4 in each case. The output ports AP1, AP2 are also embodied as duplexers and are respectively cross-connected in each case to two SAW filters F1, F2 and F3, F4. In addition, the output ports AP1, AP2 are balanced here, so that the chip has a total of four output terminals eight? 1&^?113^?2&, eight?213, two output terminals eight? 13, 4? 11) and eight? 23, 4? 21) Each output port API and AP2 is formed separately in each case.

The antenna 1 can be optionally connected to one of the two signal paths SP1, SP2 of the receiving circuit via the switch S, each of the two signal paths SP1, SP2 leads to the input port EP1, EP2 of the chip one of them. On the output side, the chip's output ports AP1, AP2 are connected to two low noise amplifiers LNAULNA2.

[0049] In addition, the antenna 1 can be connected to one of the two transmission paths SP3, SP4 of the transmission circuit via the switch S. Each transmission path SP3, SP4 has preamplifiers VV1 and VV2, main amplifiers HV1 and HV2, and low pass amplifiers LPF1 and LPF2.

[0050] FIG. 2 shows an arrangement of SAW filters n, F2, F3, F4 in a chip CH according to the present invention according to the first illustrative embodiment. The two input ports EP1 and EP2 are on the input side. The first input port EP1 is connected to filters F1 and F3. The second input port EP2 is connected to filters F2 and F4. The filters F1 and F2 are filters for the frequency band in the high frequency band, and the filters F3 and F4 are filters for the frequency band in the low frequency band. These can be, for example, frequency bands defined according to the GSM standard. Filter F1 is designed for the 1960 MHz GSM band and filter F2 is designed for the 1842 • 5 MHz GSM band. Correspondingly, both frequency bands are in the high frequency band. Filters F3 (942 • 5 MHz) and F4 (881 • 5 MHz) cover the band according to the GSM standard and are located in the low band.

However, the present invention is by no means limited to the frequency band according to the GSM standard. The four filters "1/2/3" and "4" can also be designed, for example, for four frequency bands according to the UMTS standard.

According to the first illustrative embodiment shown in FIG. 2, the four filters F1-F4 are DMS structures. In this context, each of the four filters F1-F4 is composed of a combination of two filter structures FS1a, DMS1b, FS2a, DS2b, FS3a, DMS3b, FS4a, DMS4b, one of which can be a DMS structure. composition.

The configuration of such a filter consisting of two filter structures is discussed by the first filter FI. The other filters F2, F3, F4 can have a similar filter structure.

The first filter structure FS1a of the first filter F1 is a series resonator. The output of the first filter structure FS1a is here simultaneously connected via three parallel signal lines SL1, SL2, SL3 to the structural unit of the second filter structure DMS1b. [0055] The second filter structure DMS1b is a DMS structure and has three coupled converters and two output converters. The signal lines SL1, SL2, SL3 connected to the output of the first filter structure FS1 are connected to the coupling converter in each case. The outputs A01, A02 of the two output converters of the DMS structure DMS1b are in each case connected to one output port API, AP2 of the chip CH. In this arrangement, the first output port APIs are each connected to one of the filters F1 and F2. The first output port API has two output terminals AP1a, AP1b, and is set to be balanced. The second output port AP2, which also has two output terminals AP2a, AP2b and is set to be balanced, is connected to filters F3 and F4.

The arrangement shown here represents a simplification of the actual filter structure. The filter for the GSM 1900 MHz band can be formed by a series circuit of a resonator and a DMS filter structure with six IDTs. Resonators and DMS filters correspond to the first and second filter structures. Filters for the GSM 1800 MHz band can have series and parallel resonators as the first filter structure and DMS filter structures with six IDTs as the second filter structure. Filters for the GSM 850 and %0 MHz bands can have the DMS structure with three IDTs on the output side as the second filter structure and the series and parallel resonators as the first filter structure. In addition, further resonators can be used at the input between the duplex filters in order to provide improved matching.

If two filters form a duplexer, the frequency characteristics of these two filters must be matched to each other by matching elements. The signal in the passband of one filter should be reflected by another filter. On the input side of the chip, it is therefore possible to set other elements that provide corresponding matching of the filter.

[0058] For example, an external coil connected to one of the input ports EP1, EP2 may be used. In addition, inductance and capacitance can be set between the two filters forming the duplexer. This combination of inductance and capacitance can also be achieved with a resonator. Copper coils mounted on the chip CH can be used as further matching elements.

The present invention is in no way limited to the arrangement of the SAW filter FI-F4 shown here. In addition to the DMS structure, filters F1-F4 can also be provided as ladder filters, or a mixture of ladder and DMS filters is conceivable. In these contexts, the ladder structure is cascaded with the DMS structure.

The input ports EP1 and EP2 are respectively connected in each case to the filters F1 and F2 for the frequency band in the high frequency band and the filters H and F4 for the frequency band in the low frequency band, respectively, with one output at the same time The port AP1 is connected to the filters F1, F2 for one frequency band each coming from the high frequency band, and the other output port AP2 is connected to the filters F3, F4 for one frequency band each coming from the low frequency band. Correspondingly, in the chip CH according to this first embodiment, it is not possible to avoid the crossing of the signal line on the input side or on the output side.

[0061] FIG. 3 shows a second illustrative embodiment of a chip CH according to the present invention. The second illustrative embodiment differs from the illustrative embodiment shown in FIG. 2 specifically in the arrangement of the SAW filters F1-F4 on the chip substrate. The four filters FIFA are now set in the form of a 2×2 matrix with two rows and two columns. Filters F1 and F2 form a first row, filters F3 and F4 form a second row, and filters F1 and F3 and filters F2 and F4 form a column in each case. Filters F1 and F3 are provided on the left side of the chip CH and are connected to the first input port EP1. Filters F2 and F4 are disposed on the right side and are connected to the second input port EP2.

[0062] The output port 4?1, terminal 6?? 13^?113 4?23, 々?213 each set in the filter? Between 1-?4. The terminals AP1a, AP1b of the first output port AP1 are arranged between the filter F1 and the filter F2. The terminals AP2a, AP2b of the second output port AP2 are disposed between the filters F3 and F4 and are connected to the two filters F3, F4. Here, the output port API, AP2 is set to be balanced in each case.

[0063] Compared to the arrangement shown in FIG. 2 , the arrangement of the filters F1-F4 according to the second illustrative embodiment presents some advantages. The chip CH is generally more compact, resulting in a more favorable length and width ratio. This allows standard tools for installing and testing the chip CH. In addition, no crossing of signal lines is required on the input side. There is also no signal crossing on the output side.

[0064] Therefore, signal crossing is avoided at the chip level. Line crossings may occur on the output side only when the chip is connected to the package's pad.

[0065] The invention is not limited to the embodiments of the chip shown here. Thus, for example, the acoustic tracks of each individual SAW filter F1-F4 can be rotated by 90° about their respective center points in the arrangement according to FIG. 3. Correspondingly, the outputs of the SAW filters F1-F4 also rotate to different positions. In this case, a shorter signal path for connecting the output terminals AP1a/b and AP2a/b to the packaged terminals can be generated.

[0066] FIG. 1A shows a graphical representation of one possible embodiment of a second illustrative embodiment. Therefore, this representation is described in more detail, specifically, the filter structure is more accurately decomposed.

[0067] The four SAW filters H, F2, F3, and F4 are again set to square on the chip. The filters F1 - F4 form a 2×2 matrix, respectively two filters F1 and F3 and F2 and F4 which are each arranged in a column. In addition, filters F1 and F2 and filters F3 and F4 from different columns, respectively, are arranged opposite to each other.

[0068] The two input ports EP1 and EP2 are located on the input side. The first input port EP1 is connected to filters F1 and F3 forming a diplexer. The second input port EP2 is connected to filters F2 and F4. The filters F1 and F2 are filters for the frequency band in the high frequency band, and the filters F3 and F4 are filters for the frequency band in the low frequency band. These can be, for example, frequency bands defined according to the GSM standard. The filter F1 is for example designed for the i960 MHz GSM band and the filter F2 is designed for the 1842.5 MHz GSM band. Correspondingly, both frequency bands are located in the high frequency band. The filters F3 (942.5MHz) and F4 (881.5fflz) cover the frequency band according to the GSM standard and are located in the low frequency band.

Each of the filters F1-F4 is composed of a plurality of filter structures. The filter F1 for the 1900 MHz GSM band has a DMS structure DMS1a connected in series with the second filter structure FS1b. The first DMS structure DMS1a has two input converters and four coupled converters. The second filter structure FS1 b has two resonators implemented in this case with a four-port resonator. The output of the second filter structure FS1b of the first filter F1 is connected to the output terminals AP1a, AP1b of the first output port API. The first output port API is balanced. The two signal paths of the balanced operation are conducted via the two-port resonator FS1b.

A second filter F2 for the GSM frequency band of 1800 MHz is disposed opposite to the first filter F1. The second filter has three filter structures DMS2a, FS2b and FS2c. The first filter structure of the second filter F2 is a DMS structure DMS2a and has a total of six IDTs, two input converters and four coupled converters. The DMS structure DMS2a is connected in series with the second filter structure FS2b. The second filter structure FS2b has two resonators here implemented again as four-port resonators. The third filter structure FS2c, which also has two resonators consisting of four-port resonators, is connected in parallel with the second filter structure FS2b. The parallel two-port resonator FS2c is actually connected to ground, and on the input side, two balanced signals are connected thereto. The output terminals APIa, AP1b of the first output port API are connected in series with the second filter structure FS2b and connected in parallel with the third filter structure FS2c of the second filter F2.

[0071] The third filter F3 for the GSM band of 942.5 MHz together with the first filter F1 forms a duplexer. The third filter F3 has three resonators FS3a, FS3b, FS3c and a DMS structure DMS3d. The first resonator FS3a is directly connected to the first input port EP1. The third resonator FS3c is connected in series with the first resonator FS3a. In addition, the second resonator FS3b is connected to ground in parallel between the first and third resonators. The third resonator FS3c is connected to the DMS structure DMS3d via three parallel signal lines, DMS3d having three coupling converters and two output converters. The two outputs of the DMS structure DMS 3d are in each case connected to one of the output terminals AP2a, AP2b of the second output port AP2, the second output port AP2 being balanced.

[0072] A fourth filter F4 for the 850 MHz GSM band is constructed similarly to the third filter F3. The fourth filter F4 also has three resonators FS4a, FS4b, FS4c and a DMS structure DMS4d, the first resonator FS4a being directly connected to the second input port EP2. The output of the first resonator FS4a is also connected to the third resonator FS4c. The second resonator FS4b is connected to ground in parallel between the first and third resonators. The third resonator FS4c is connected to the DMS structure DMS3d via three parallel signal lines, DMS3d having three coupled converters and two output converters. The two outputs of the DMS structure DMS 4d are in each case connected to one of the output terminals AP2a, AP2b of the second output port AP2.

[0073] The present invention is in no way limited to the arrangement of the filters F1-F4 shown in FIG. 10 and the precise configuration of the filters F1-F4 shown here. Therefore, it is also possible within the scope of the invention that the chip has four input ports and four output ports, each filter F1-F4 being connected exactly to one input port and just to one output port. In addition, each of the two filters may be interconnected so that only one duplexer is formed on the input side or only on the output side.

[0074] FIG. 4 shows the insertion loss and the standing wave ratio of the first filter F1. The first filter F1 is designed for the 1960 MHz GSM band. The upper figure shows the insertion loss. It can be seen here that there is a very slight insertion loss in the passband between 193 〇 and 1990 MHz. In contrast, the insertion loss exceeds 35dB in the stopband.

In both of the following figures, the standing wave ratio is shown. The left figure shows the standing wave ratio at the input side of the filter. This diagram shows that the reflected signal becomes very low in the passband. The right side shows the standing wave ratio on the output side. Here too only very fine signal components are reflected in the passband.

[0076] FIGS. 5 to 7 correspondingly show the insertion loss and the standing wave ratio of the input side and the output side of the filters F2, F3, and F4. Filter F2 is designed for the 1842-5MHz GSM band. Filter F3 is designed for the GSM low band of M2 • 5MHz. Filter F4 is designed for the 881 • 5MHz GSM low band.

[0077] FIG. 8 shows a graphical representation of a package PA with a chip CH according to the invention. The package PA has a rectangular basic shape with two long sides and two short sides, which in each case form a 90[deg.] angle with the long sides.

[0078] The package PA also has eight pins, Pin1-Pin8, which can be connected to the circuit board and other components via these pins. The four pins Pin1-Pin4 are disposed on the first long side, and the four other pins Pin5-Pin8 are disposed on the opposite second long side.

[0079] Pinl is generally available for the first input port EP1, and Pin4 is used for the second input port EP2. In addition, if the output ports AP1, AP2 are single-ended, Pin5 and Pin8 are used to connect the two output ports AP1, AP2. In the case of balanced output ports AP1, AP2, Pin5 and Pin6 are used for the first output port AP1, and Pin7 and Pin8 are used for the second output port AP2.

Pin2 and Pin3 can be used as a ground supply source.

[0081] FIG. 9 shows a modified arrangement of a package PA. Additionally, this package PA has two additional pins Pin9 and Pin10 disposed on the short side of the package and two additional pins Pinii and Pinl2 disposed on the opposite second short side.

[0082] Pin9_Pinl2 is used to connect the output ports AP1 and AP2. This configuration provides the advantage that the output ports API, AP2 of the chip CH can be connected to the terminals Pin9-Pinl2 of the package PA via a short symmetrical signal line.

[0083] Reference Sign 1 - Antenna 2 - RF Circuit SP1 - First Signal Path SP2 - Second Signal Path SP3 - Third Signal Path SP4 - Fourth Signal Path CH - Chip EP1 - First Input Port EP2 - Second Input Port F1 - First filter F2 - Second filter F3 - Third filter F4 - Fourth filter API - First output port AP2 - Second output port AP1 a - API first terminal AP1b - API second Terminals AP2a - AP2 First Terminal AP2b - AP2 Second Terminal S_ Switch LNA1 - First Low Noise Amplifier LNA2 - Second Low Noise Amplifier VV1 - First Preamplifier VV2 - Second Preamplifier HV1 - First Main amplifier HV2 - second main amplifier LPF1 - first low-pass filter LPF2 - second low-pass filter FS1a - first filter structure of F1 DMS1b - second structure of F1 FS2a - first filter structure of F2 DMS2b - F2 second DMS structure FS3a - F3 first filter structure DMS3b - F3 second DMS structure FS4a - F4 first filter structure DMS4b - F4 second DMS structure SL1 - first signal line SL2 - The second signal line SL3 - The third signal line A01 - The first output A02 of the DMS1b - The second output of the DMS1b PA - Package Pin l - the first pin.