N-phase polarity output pin mode multiplexer

N-phase polarity output pin mode multiplexer

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application requires the N-Phase Polarity Output Pin Mode Multiplexer (N-Phase Polarity Output Pin Mode Multiplexer) which was filed on June 29, 2012 and assigned to the assignee of this application and is expressly incorporated herein by reference. Pin mode multiplexer)" provisional application No. 61/666,197 priority.

[0003] Background

[0004] Field

[0005] The present disclosure generally relates to high-speed data communication interfaces, and more specifically, to multiplexing input and output pins of an application processor embedded in a cellular phone.

[0006] Background

[0007] Manufacturers of mobile devices, such as cellular phones, can obtain mobile device components from a variety of sources, including different manufacturers. For example, the application processor and the cell phone can be obtained from a first manufacturer, and the display of the cell phone can be obtained from a second manufacturer. In addition, multiple standards are defined for interconnecting certain components of mobile devices. For example, there are multiple types of interfaces defined for communication between the application processor and the display in the mobile device. Some displays provide interfaces that comply with the Display System Interface (DSI) specified by the Mobile Industry Processor Interface Alliance (MIPI). Other displays can use other kinds of physical interfaces, which may be more efficient than conventional DSI. It would be economical for the same application processor to be configured for use with more than one display interface.

[0008] Overview

[0009] The various embodiments disclosed herein provide systems, methods, and devices that enable an application processor to use any of a number of interface standards to communicate with a display. According to certain aspects described herein, two or more integrated circuit (IC) devices can be co-located in an electronic device and communicatively coupled through one or more data links, which can be configured as required To be compatible with one of multiple interface standards.

[0010] In an aspect of the present disclosure, a data transmission method includes determining a type of physical interface to be used for communication between two devices in a wireless mobile terminal, selecting an encoder to generate and use for the two The type of the physical interface for communication between the devices matches the encoded data, and a plurality of drivers are configured to receive the encoded data from the encoder and according to the value of the physical interface used for the communication between the two devices Type to drive multiple connectors that communicatively couple the two devices. The type of the physical interface may be one of multiple types of physical interfaces supported by at least one of the two devices.

[0011] In one aspect of the present disclosure, the data transmission method includes controlling a plurality of switches to couple the output of the selected encoder to the plurality of drivers.

[0012] In one aspect of the present disclosure, the plurality of connectors includes at least some bidirectional connectors. The encoder can provide encoded data in a differentially encoded signal.

[0013] In one aspect of the present disclosure, configuring the plurality of drivers to receive the encoded data includes putting one or more outputs of another and/or different encoder into a high impedance mode. The other and/or different encoder may include an N-phase encoder.

[0014] In one aspect of the present disclosure, the encoder encodes using a combination of the phase state of the first pair of connectors, the polarity of the second pair of connectors, and the selection of at least one undriven connector. The code is provided in the symbol sequence

Code data. The first pair of connectors may include the same wires as the second pair of connectors. One or more outputs of the differential encoder can be put into high impedance mode. The encoded data may be related to a camera or a display controlled by one of the two devices.

[0015] In an aspect of the present disclosure, a device includes a plurality of connectors that communicatively couple a first IC device with a second IC device, and are used to generate a physical connection for communication between the two devices. A device for encoding data conforming to the type of the interface, and a device for configuring a plurality of drives to receive the encoded data from one of the at least two encoders and according to the method used for communication between the two devices The type of physical interface drives a device that communicatively couples the multiple connectors of the two devices. The apparatus for generating encoded data may include at least two encoders configured to encode data in different ways. The plurality of connectors may include wires, traces, or other conductive connectors.

[0016] In an aspect of the present disclosure, a device includes a plurality of connectors that communicatively couple a first device and a second device in a wireless mobile terminal, and a processing system configured to determine the use of the first device The operation mode of the communication with the second device is to select the encoder for driving the plurality of connectors, and to configure the plurality of drivers to receive the encoded data from the encoder. The plurality of drivers may drive the plurality of connectors.

[0017] In one aspect of the present disclosure, a processor-readable storage medium having one or more instructions that when executed by at least one processing circuit causes the at least one processing circuit to determine that it will be used for wireless mobility The type of the physical interface for communication between the two devices in the terminal, selecting an encoder to generate encoded data that matches the type of the physical interface for communication between the two devices; and configuring a plurality of drivers to follow The encoder receives the encoded data and drives a plurality of connectors that communicatively couple the two devices according to the type of the physical interface used for communication between the two devices. The type of the physical interface may be one of multiple types of physical interfaces supported by at least one of the two devices.

[0018] Brief Description of the Drawings

[0019] FIG. 1 depicts an apparatus using a data link between IC devices, the data link selectively operating according to one of a plurality of available standards.

[0020] FIG. 2 illustrates the system architecture of an apparatus using a data link between various IC devices, the data link selectively working according to one of a plurality of available standards.

[0021] Figure 3 illustrates an example of a data link using differential signaling.

[0022] FIG. 4 illustrates an N-phase polarity data encoder.

[0023] Figure 5 illustrates the signaling in the N-phase polarity encoding interface.

[0024] FIG. 6 illustrates an N-phase polarity decoder.

[0025] FIG. 7 illustrates the system architecture of a device that can selectively use N-phase polarity encoding or differential signaling.

[0026] FIG. 8 is a flowchart of a method for selective N-phase polarity encoding.

[0027] FIG. 9 is a diagram illustrating an example of a hardware implementation of an apparatus using N-phase polarity data encoding.

[0028] Detailed description

[0029] Various aspects will now be described with reference to the drawings. In the following description, numerous specific details are set forth for explanatory purposes to provide a thorough understanding of one or more aspects. However, it is obvious that this (type) aspect can be practiced without these specific details.

[0030] As used in this application, the terms "component", "module", "system" and similar terms are intended to include computer-related entities such as but not limited to hardware, firmware, a combination of hardware and software, software, Or the software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable, a thread of execution, a program, and/or running on a processor.

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Or computer. As an illustration, both the application running on the computing device and the computing device can be components. One or more components may reside in processes and/or threads of execution, and the components may be localized on one computer and/or distributed between two or more computers. In addition, these components can be executed from various computer readable media having various data structures stored thereon. These components can communicate through local and/or remote processes, such as communicating based on a signal with one or more data packets, such as from another component in the local system or distributed system through the signal. Data of a component that interacts and/or interacts with other systems across networks such as the Internet.

[0031] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, the phrase "X adopts A or B" is intended to mean any natural inclusive arrangement. That is, the phrase "A or B for X meters satisfies any of the following examples: A for X meters; B for X meters; or both A and B for X meters. In addition, as used in this application and the appended claims The articles "a" and "some" should generally be interpreted as meaning "one or more" unless stated otherwise or it is clear from the context that they refer to the singular form.

[0032] Certain embodiments of the present invention are applicable to communication links deployed between electronic components, which may include sub-components of devices, such as phones, mobile computing devices, home appliances, automotive electronics, avionics systems Wait. Figure 1 depicts a device that uses a data link between various IC devices, the data link selectively working according to one of a number of available standards. In one example, the apparatus 100 may include a wireless communication device that communicates with a radio access network (RAN), a core access network, the Internet, and/or another network through an RF transceiver. The device 100 may include a communication transceiver 106 operatively coupled to the processing circuit 102. The processing circuit 102 may include one or more IC devices, such as an application specific IC (ASIC) 108_oThe ASIC 108 may include one or more processing devices, logic circuits, and so on. The processing circuit 102 may include and/or be coupled to a processor-readable storage 112 that may maintain instructions and data executable by the processing circuit 102. The processing circuit 102 may be controlled by one or more of an operating system and an application programming interface (API) 110 layer, which supports and allows the execution of software residing in a storage medium (such as the memory device 112 of a wireless device) Module. The memory device 112 may include read-only or random access memory (RAM and ROM), EEPROM, flash memory card, or any memory device that can be used in processing systems and computing platforms. The processing circuit 102 may include or access a local database 114 that may maintain operating parameters and other information used to configure and operate the device 100. The local database 114 may be implemented using one or more of a database module, flash memory, magnetic media, EEPROM, optical media, magnetic tape, floppy disk, or hard disk, etc. The processing circuit may also be operatively coupled to external devices, such as the antenna 122, the display 124, operator controls (such as the buttons 128 and the keypad 126, and other components).

[0033] FIG. 2 is a block diagram 200 illustrating certain aspects of an apparatus, such as a wireless mobile device, a mobile phone, a mobile computing system, a wireless phone, a notebook computer, a tablet computing device, a media player, a gaming device, etc. The apparatus 200 may include a plurality of IC devices 202 and 230 that exchange data and control information through a communication link 220. The communication link 220 may be used to connect IC devices 202 and 222 located close to each other or physically located in different parts of the apparatus 200. In one example, the communication link 220 may be provided on a chip carrier, a substrate, or a circuit board that carries the IC devices 202 and 230. In another example, the first IC device 202 may be located in the keyboard portion of the foldable phone, and the second IC device 230 may be located in the display portion of the foldable phone. In another example, a portion of the communication link 220 may include a cable or optical connection.

[0034] The communication link 220 may include a plurality of channels 222, 224, and 226. One or more channels 226 may be bidirectional, and may operate in half-duplex and/or full-duplex modes. One or more channels 222 and 224 may be unidirectional. The communication link 220 may be asymmetric, thereby providing a higher bandwidth in one direction. In one example described herein, the first communication channel 222 may be referred to as the forward link 222, and the second communication channel 224 may be referred to as the reverse link 224. The first IC device 202 can be designated as a host system or transmitter, and the second IC device 230 can be designated as a client system or interface.

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Receiver, even the IC devices 202 and 230 are configured to transmit and receive on the communication link 222. In one example, the forward link 222 may operate at a higher data rate when communicating data from the first IC device 202 to the second IC device 230, while the reverse link 224 may operate at a higher data rate when transferring data from the second IC device. When the device 230 communicates to the first IC device 202, it works at a lower data rate.

[0035] The IC devices 202 and 230 may each include a processor or other processing and/or computing circuits or devices 206, 236. In one example, the first IC device 202 can perform the core functions of the apparatus 200, including maintaining wireless communication via the wireless transceiver 204 and the antenna 214, and the second IC device 230 can support the user interface for managing or operating the display controller 232 , And the camera controller 234 can be used to control the operation of the camera or video input device. Other features supported by one or more of IC devices 202 and 230 may include keyboards, voice recognition components, and other input or output devices. The display controller 232 may include circuits and software drivers that support displays (such as liquid crystal display (LCD) panels, touch screen displays, indicators, etc.). The storage media 208 and 238 may include transient and/or non-transitory storage devices, which are adapted to It is configured to maintain instructions and data used by the corresponding processors 206 and 236 and/or other components of the IC devices 202 and 230. The communication between each processor 206, 236 and its corresponding storage media 208 and 238 and other modules and circuits may be facilitated by one or more buses 212 and 242, respectively.

[0036] The reverse link 224 may operate in the same manner as the forward link 222, and the forward link 222 and the reverse link 224 may be capable of transmitting at comparable speeds or at different speeds, where the speed may be Expressed as data transfer rate and/or clock rate. Depending on the application, the forward and reverse data rates can be substantially the same or differ by several orders of magnitude. In some applications, a single bidirectional link 226 may support communication between the first IC device 202 and the second IC device 230. When, for example, the forward and reverse links 222 and 224 share the same physical connection and operate in a half-duplex manner, the forward link 222 and/or the reverse link 224 may be configured to operate in a bidirectional mode. In one example, the communication link 220 may be operated to communicate control, commands, and other information between the first IC device 202 and the second IC device 230 according to industry or other standards.

[0037] Industry standards can vary from application to application. In one example, the MIPI standard defines a physical layer interface that includes a synchronous interface specification (D-PHY) between an application processor IC device 202 and an IC device 230 that supports a camera or display in a mobile device. The D-PHY specification controls the operating characteristics of products that comply with the MIPI specification of mobile devices. The DPHY interface can support data transmission using a flexible, low-cost, high-speed serial interface interconnected between the components 202 and 230 in the mobile device. These interfaces may include complementary metal oxide semiconductor (CMOS) parallel buses that provide relatively low bit rates and slow edges to avoid electromagnetic interference (EMI) problems.

[0038] FIG. 3 is a schematic diagram illustrating the implementation of certain aspects of the communication link 220 depicted in FIG. 2 using differential signaling. Differential signaling involves electrically transmitting information with two complementary signals sent on wire pairs 310a, 310b, or 310c, which wire pairs may be referred to as differential pairs. By eliminating the common mode interference effect that affects the two lines in the differential pair, the use of the differential pair can significantly reduce EMI. On the forward link 222, the wire pair 310a can be driven by the main differential amplifier 304. The differential amplifier 304 receives the input data stream 302 and generates a positive and negative version of the input 302, which is then provided to the wire pair 310a. The differential receiver 306 on the client side generates an output data stream 308 by performing a comparison of the signals carried on the wire pair 310a.

[0039] On the reverse link 224, one or more wire pairs 310c can be driven by a client-side differential amplifier 326. The differential amplifier 326 receives the input data stream 328 and generates a positive and negative version of the input 328, which is then provided to the wire pair 310c. The differential receiver 324 on the host generates an output data stream 322 by performing a comparison of the signals carried on the wire pair 310c.

[0040] In the bidirectional link 226, the host and client can use the same wire pair configured in half-duplex mode

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310b to transmit and receive data. Alternatively or in addition, the bidirectional bus may use a combination of forward link and reverse link drivers 304, 326 to drive multiple wire pairs 310a, 310c to operate in full duplex mode. In the half-duplex bidirectional implementation depicted, transmitters 314 and 314' can avoid driving wire pair 310b at the same time, and output enable (0E) controls 320a, 320c can be used (respectively) to force transmitters 314 and 314' Enter the high impedance state. Generally, by using the OE control 320b to force the differential receiver 316' into a high impedance state, the differential receiver 316' can avoid driving the input/output 312 when the differential transmitter 314 is active. Generally, by using the OE control 320d to force the differential receiver 316 into a high impedance state, the differential receiver 316 can avoid driving the input/output 318 when the differential transmitter 314' is active. In some cases, when the interface is inactive, the outputs of the differential transmitters 314 and 314' and the differential receivers 316 and 316' may be in a high impedance state. Accordingly, the OE controls 320a, 320c, 320b, and 320c of the differential transmitters 314, 314' and the differential receivers 316 and 316' can be operated independently of each other.

[0041] Each differential amplifier 304, 314, 314', and 326 may include a pair of amplifiers, one amplifier receiving the inverse of the input of the other amplifier at the input. The differential amplifiers 304, 314, 314', and 326 can receive a single input, and can include an internal inverter to generate an inverted input for use by a pair of amplifiers. The differential amplifiers 304, 314, 314' and 326 can also be constructed with two separately controlled amplifiers so that their respective outputs can be placed in a high impedance mode independently of each other.

[0042] According to certain aspects disclosed herein, the system and apparatus may use a multi-phase data encoding and decoding interface method for communication between the IC devices 202 and 230. The multiphase encoder can drive multiple conductors (ie M conductors). The M conductors generally include three or more conductors, and each conductor may refer to a line. Of course, the M conductors may include conductive traces on a circuit board or a conductive layer of a semiconductor IC device. The M conductors can be divided into multiple transmission groups, and each group encodes a part of the data block to be transmitted. The N-phase encoding scheme is defined as where the data bits are encoded as phase changes and polarity changes on the M conductors. In one example, an N-phase encoding scheme for a 3-wire system may include three phase states and two polarities, thereby providing 6 states and 5 possible transformations from each state. Deterministic voltage and/or current changes can be detected and decoded to extract data from M conductors. Decoding does not rely on independent conductors or conductor pairs, and timing information can be derived directly from the phase and/or polarity transformations of the M conductors. N-phase polarity data transmission can be applied to any signaling interface, such as, for example, electrical, optical, and radio frequency (RF) interfaces.

[0043] FIG. 4 is a schematic diagram illustrating the use of N-phase polarity encoding to implement certain aspects of the communication link 220 depicted in FIG. 2. The communication link 220 may include a wired bus having multiple signal wires, which may be configured to carry N-phase encoded data in a high-speed digital interface, such as a mobile display digital interface (MDDI). One or more of channels 222, 224, and 226 may use N-phase polarity encoding. The physical layer drivers 210 and 240 may be adapted to encode and decode the N-phase polarity encoded data transmitted on the link 220. The use of N-phase polarity encoding provides high-speed data transmission and can consume half or less of the power of other interfaces because fewer drivers are active in the N-phase polarity encoding data link 220. The N-phase polarity encoding device 210 and/or 240 can encode multiple bits for each transformation on the communication link 220. In one example, a combination of 3-phase and polar encoding can be used to support a wide video graphics array (WVGA), 80 frames per second LCD driver IC without the need for a frame buffer, which delivers pixel data at a rate of 810Mbps For the display to refresh.

[0044] In the example depicted at 400, the M-wire, N-phase polar coded transmitter is configured with M=3 and N=3. For the purpose of simplifying the description of certain aspects of the present disclosure, the example of the 3-wire, 3-phase encoding is selected separately. The principles and techniques disclosed for 3-wire and 3-phase encoders can be applied to other configurations of M-wire and N-phase encoders.

[0045] When using N-phase polarity encoding, connectors (such as the signal wires 410a, 410b, and 410c on the N-wire bus) may not be driven, driven to be positive, or driven to be negative. Signal wires 410a, 410b or 410c that are not driven can be in high impedance

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Resistance state. The signal wire 410a, 410b, or 410c that is not driven can be driven or pulled to a voltage level that is substantially midway between the positive and negative voltage levels provided on the driven signal wire. The signal wire 410a, 410b, or 410c that is not driven may not have current flowing through it. In the example 400, each of the signal wires 410a, 410b, and 410c may be one of the three states (labeled +1, -1, or 0) using the driver 408. In one example, the driver 408 may include a unit-level current mode driver. In another example, the driver 408 may drive opposite polarity voltages on the two signals 410a and 410b, while the third signal 410c is at high impedance and/or is pulled to ground. For each transmitted symbol interval, at least one signal is in the non-driven (0) state, and the number of positively driven (+1 state) signals is equal to the number of negatively driven (-1 state) signals, so that the flow direction The current sum of the receiver is always zero. For each symbol, the state of at least one signal wire 410a, 410b, or 410c is changed relative to the symbol transmitted in the previous transmission interval.

[0046] The mapper 402 can receive 16-bit data 410, and the mapper 402 can map the input data 410 into 7 symbols 412 for sequential transmission through the signal wires 410a, 410b, and 410c. The M-line, N-phase encoder 406 receives the 7 symbols 412 generated by the mapper one symbol 414 at a time, and calculates the state of each signal wire 410a, 410b, and 410c for each symbol interval. The 7 symbols 412 can be serialized using, for example, a parallel-to-serial converter 404. The encoder 406 selects the state of the signal wires 410a, 410b, and 410c based on the input symbol 414 and the previous state of the signal wires 410a, 410b, and 410c.

[0047] The use of M-line and N-phase encoding allows multiple bits to be encoded into multiple symbols, where the bits of each symbol are not integers. In a simple 4-wire system example, there are 4 available 2-wire combinations (the 2 wires can be driven at the same time) and 2 possible polarity combinations on the driven wire pair, resulting in 6 possible states. Since each transition occurs from the current state, 5 of the 6 states are available at each transition. At each change, the state of at least one wire is required to change. There are 5 states, each symbol can encode log2 (5) Zhu 2.32 bits. Correspondingly, the mapper can accept 16-bit words and convert them into 7 symbols, because 7 symbols carrying 2.32 bits per symbol can encode 16.24 bits. In other words, the combination of seven symbols encoding five states has 5? (ie 78125) permutations. Correspondingly, these 7 symbols can be used to encode 216 (that is, 65536) permutations of 16 bits.

[0048] FIG. 5 illustrates an example of signaling 500 using a three-phase modulation data coding scheme based on a cyclic state diagram 550. According to the data encoding scheme, the 3-phase signal can be rotated in two directions and can be transmitted on the three conductors 410a, 410b, and 410c. The three signals carried by the conductors 410a, 410b, and 410c include 3-phase signals and are independently driven, wherein each signal has a phase difference of 120 degrees with respect to the other two signals. At any point in time, each of the 3 wires is in a different state from the other 2 wires (represented by V+, V- and open circuit). The encoding scheme also encodes information in the form of the polarities of the two of the conductors 410a, 410b, and 410c that are actively driven to positive and negative levels. The polarity for the depicted state sequence is indicated at 508.

[0049] At any time in the 3-wire implementation, exactly two of the conductors 410a, 410b, and 410c carry signals, and the data encoding state can be defined in the form of a voltage difference or current flow between the conductors. As shown in the state diagram 550, three phase states (corresponding to states A, B, and C, respectively) are defined with, for example, signal flow from states A to B, B to C, and C to A in one direction. Subsequently, the transition between these three states is defined according to the state diagram 550 to ensure a cyclic state transition. In one embodiment, the clockwise rotation (A to B) to (B to C), (B to C) to (C to A), and (C to A) to (A to B) in the state transition can be It is used to transmit logic 1, and the counterclockwise rotation (B to C) to (A to B), (A to B) to (C to A) and (C to A) to (B to C) in the state transition can be It is used to transmit logic 0. Also note that at any time, only one of the states (A to B), (B to C), and (C to A) can be true. Correspondingly, it can be "rotated" by the control signal clockwise or counterclockwise. The bits are encoded at each transformation. In one example, the direction of rotation can be based on which of the 3 wires has not been transformed after the transformation.

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Drive to determine.

[0050] The information can also be encoded in the form of the polarity of the driven signal wires 410a, 410b, and 410c or the current direction between the two signal wires 410a, 410b, 410c. Signals 502, 504, and 506 illustrate the voltage levels applied to conductors 410a, 410b, 410c, respectively, at each phase state. At any time, the first conductor is coupled to a positive voltage (for example +V), the second conductor is coupled to a negative voltage (for example, one V), and the remaining third conductor is open. In this way, a polarity encoding state can be determined by the current flow between the first and second conductors or the voltage polarity of the first and second conductors. In some embodiments, two bits of data can be encoded at each phase change. The decoder can determine the rotation to obtain the first bit, and the second bit can be determined based on the polarity. The decoder that has determined the direction of rotation can determine the current phase state and the polarity of the voltage applied between the two active connectors 502, 504, and/or 506, or flow through the two active conductors 502, 504, and/or 506 The direction of the current.

[0051] As disclosed herein, one bit of data can be encoded in the form of rotation, or in the form of phase changes in a 3-wire, 3-phase encoding system, and the additional bits can be based on the polarity of the two driven wires. Form to encode. Some embodiments encode more than two bits in each transition of a 3-wire, 3-phase encoding system by allowing a transition from the current state to any of the possible states. Assuming that there are 3 rotation phases and each phase has two polarities, 6 states are defined so that 5 states are available from any current state. Correspondingly, there can be 2.32 bits per symbol (transformation) log2 (5), and the mapper can accept 16-bit words and convert them into 7 symbols.

[0052] N-phase data transmission may use more than three wires provided in a communication medium such as a bus. The use of additional signal wires that can be driven simultaneously provides more combinations of states and polarities, and allows more bits of data to be encoded at each transition between states. This can significantly improve the throughput of the system, and compared to the use of multiple differential pairs to transmit data bits to reduce power consumption, while providing increased bandwidth.

[0053] In one example, the encoder can use 6 wires to transmit symbols, where for each state, 2 pairs of wires are driven. The 6 wires can be labeled A to F so that in one state, wires A and F are driven positive, wires B and E are driven negative, and C and D are not driven (or do not carry current). For 6 wires, there can be:

,. 61

[0054] i\6.,4) * 77---7mOneτ; - 15 (6-4)! * 4!

[0055] Possible combinations of wires that are actively driven, where for each phase state, there are: _z 、 4!

[0056] C(4,2) = © _ 2)!· ?! = 6

[0057] A combination of different polarities.

[0058] 15 different combinations of actively driven wires may include:

[0059]

<td>ABCD</td><td>A Β C Ε</td><td>Α Β CF</td><td>ABDE</td><td>Α Β DF</td>

<td>A Β EF</td><td>AC DE</td><td>ACDF</td><td>Α Ε F</td><td>ADEF</td>

<td>Β C Ό Ε</td><td>Β CDF</td><td>Β C Ε F</td><td>Β D Ε F</td><td>CD Ε F</td>

[0060] Among the 4 driven wires, it may be a combination of two wires being driven positive (while the other two must be driven negative). Combinations of polarity can include:

[0061] ++—+—++-+—+-+-++---++

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[0062] Accordingly, the total number of different states can be calculated as 15×6=90. In order to ensure the conversion between symbols, there are 89 states available from any current state, and the number of bits that can be encoded in each symbol can be calculated as: log2 (89) = 6.47 bits per symbol . In this example, given 5 x 6.47 = 32.35 bits, the mapper can encode a 32-bit word into 5 symbols.

[0063] The general equation for the number of combinations of wires that can be driven by a bus of any size is a function of the number of wires in the bus and the number of wires that are driven at the same time:

[0064]

[0065]

[0066]

Swires ^driven)* * The equation for the number of combinations of polarities of the driven wires is: wide(x_? N Jiaqinlang dagger driven f 2 driven

[0067]

[0068]

[0069] The number of bits per symbol is: (c (% layer slightly) · q heart theory and gas)-* Figure 6 illustrates an example 600 of a receiver in a 3-phase PHY. The comparator 602 and the decoder 604 are configured to provide a digital representation of the status of each of the three transmission lines 612a, 612b, and 612c and the changes in the status of the three transmission lines compared to the status transmitted in the previous symbol period. The serial-to-parallel converter 606 combines 7 consecutive states to generate a set of 7 symbols for processing by the demapper 608 to obtain 16-bit data that can be buffered in the FIFO 610.

[0070] According to certain aspects disclosed herein, multiple three-state amplifiers can be controlled to generate a differential encoder, an N-phase polar encoder, or another encoder that encodes information in the form of wires or connectors A defined set of output states, this set of output states can infer one of the three states described.

[0071] Referring again to FIG. 4, the communication link 220 may include a high-speed digital interface that may be configured to support both a differential encoding scheme and N-phase polarity encoding. The physical layer drivers 210 and 240 may include N-phase polarity encoders and decoders (which can encode multiple bits according to the transformation on the interface) and line drivers that drive the connectors 410a, 410b, and 410c. The line driver may be configured to have an amplifier that generates an active output that may have a positive or negative voltage or a high-impedance output through which the connectors 410a, 410b, and 410c are in an undefined state or defined by external electrical components status. Accordingly, the output driver 408 may receive a pair of signals 416 including data and output control (high impedance mode control). In this regard, the tri-state amplifier used for N-phase polarity encoding and differential encoding can generate the same or similar three output states. When used for differential encoding, the three-state amplifier pair in the differential line driver 306, 316, 316' or 324 can receive the same input signal and the same output control signal, while the N-phase polarity encoding line driver 408 receives different input and output control signal. Correspondingly, the N-phase polarity encoding line driver 408 can be controlled by logic and/or switches to work as differential line drivers 306, 316, 316', and 324.

[0072] Certain embodiments provide a configurable interface that can selectively activate a desired number of wires to convey data, and/or reconfigure the M-wire, N-phase polarity encoding interface to be used as a differential interface. FIG. 7 illustrates an example in which the mobile platform 700 uses pin multiplexing to reconfigure the interface. In this example, the display processor 702 generates display data for the display device 124 (see FIG. 1). The display processor 702 may be integrated with the processing circuit 206, for example. The MIPI standard DSI or the N-phase polarity MDDI interface described herein can be used to transmit data to the device 230 through the communication link 220, and the device 230

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Includes display controller 232. FIG. 7 shows an example configuration in which the switching element 726 selects between the output of three differential drivers 714 and the output of two 3-phase, 3-wire encoders to drive 6 output pins 728. Other component combinations and configurations can be defined. In addition, the switch element 724 may include a switch matrix that allows the output pin 728 to be mapped to any output of any differential driver 714 or any output of any M-line, N-phase encoder.

[0073] When the MIPI DSI interface is configured, the display pixel data from the display processor 702 is provided to the MIPI DSI link controller 704, and the MIPI DSI link controller 704 formats the display pixel data to pass through the high-speed serial interface 728 The packet sent to the display (usually via the device 230 and/or the display controller 232). Both pixel data and control information can be transmitted through this link 728. A reverse link for reading status from the display 124 or receiving other information may be provided.

[0074] The data packet generated by the MIPI DSI link controller 704 in the digital core logic circuit system 720 can be provided to the MIPI DPHY pre-driver 706, which can be implemented in the input/output part (welding Disk ring) 724. The data packet may be provided to a set of output drivers 718 through the differential driver 714 and/or the electronic switch multiplexer 726. The differential driver 714 can be enabled, while the N-phase driver 716 is disabled. In one example, when the N-phase driver 716 is forced or otherwise placed in a high impedance output mode, the N-phase driver 716 may be disabled. In another example, the switch multiplexer 726 can select between the differential driver 714 and the N-phase driver 716 to provide the input of the line driver 718.

[0075] When N-phase polarity encoding is required, the switch 726 (switch multiplexer 726) can be operated to select the output of the N-phase driver 716 as the input of the output driver 718. Additionally or alternatively, the N-phase driver 716 may be enabled while the differential driver 714 is disabled. In this configuration, the data packet generated by the MIPI DSI link controller 704 can be encoded using the N-phase polarity encoder 710 and provided to the N-phase polarity predriver 712.

[0076] The encoder used to format the data can determine whether one or more of the line drivers 718 is in a high impedance mode. In one example, when the interface is driven in the differential encoding mode, the output control (high impedance control) of the line driver 718 can be controlled by the MIPI DPHY pre-driver 706. In another example, when the interface is driven in the N-phase polarity encoding mode, the output control of the line driver 718 can be controlled by the N-phase polarity pre-driver 712.

[0077] According to certain aspects described herein, data packets similar to MIPI DSI packets are sent over an N-phase polar link. Some packets may need to be reformatted to properly utilize the symbol grouping on the N-phase polar link. For example, MIPI DSI can be byte-oriented, and N-phase polar links can transmit 16-bit words at a time, and can add one byte to odd-length packets. Link synchronization for N-phase polarity may also be slightly different.

[0078] The M-line N-phase link controller 708 can provide input data words to data as input to the mapper 402 (see FIG. 4), which maps the input words into a series of symbols to be sent over the bus . The mapper 402 may be implemented in the encoding element 710. One purpose of the mapper 402 is to calculate the value of a set of symbols based on input data words. This may be particularly useful if the number of bits per symbol is not an integer. In the simple example described in conjunction with FIG. 4, a 3-wire system is adopted, in which, assuming that one wire is not driven, there are 3 possible combinations of 2 wires to be driven at the same time. There are also 2 possible polarity combinations for each wire pair that can be driven, resulting in 6 possible states. Since a conversion is required between any two symbols, 5 of the 6 states are available. For 5 states, there are log22.32 bits per symbol. The mapper accepts 16-bit words and converts them into 7 symbols.

[0079] The data packet generated by the N-phase polarity adaptation link controller 708 may be provided to the N-phase polarity encoder 710 to encode each set of link data (for example, 16-bit or 32-bit words) into The symbols are grouped and output to the N-phase polarity pre-driver 712 one symbol at a time. In one example, the N-phase polarity adaptation link controller 708 can be implemented in the digital core logic

CN 104412552 Β

In 720, the N-phase polarity encoder 710 can be implemented in the pad ring 724. The pre-driver 712 can amplify the received input signal to a level sufficient to drive the buffer 716 and/or the output driver 718.

[0080] The switch multiplexer 726 can choose to provide either the MIPI DPHY pre-driver 706 output or the N-phase polarity pre-driver 712 output to the output driver 718. The switch multiplexer 726 may transmit a signal having a voltage or current level much lower than the output of the output driver 718. Accordingly, the output signal from the MIPI DPHY pre-driver 706 or the N-phase polarity pre-driver 712 can be easily turned on on an IC device (such as the device 302). In some cases, a switch multiplexer 726 or related switching device may be used to switch a control signal that determines whether one or more output drivers should be in a high impedance state.

[0081] When the system is powered on, the mode selection 730 state of the switch multiplexer 726 can be set to the default or pre-configured selection. Generally, this state only needs to be configured once, because the display 124 can be permanently or semi-permanently attached to the processing circuit 102 (see FIG. 1). Therefore, the switch multiplexer can be configured during manufacturing, and the setting does not need to be changed during normal operation of the system. The switch multiplexer 726 may be addressed by the processor 206 or 236 through one or more configuration registers (which registers may be non-volatile). The code used to program the switch multiplexer may be stored in the storage 112. Using the switch multiplexer 726 to switch low-level signals allows the same application processor to be used for more than one interface without the need to duplicate I/O pads or pins. The same I/O pad or pin 728 can therefore be used for more than one interface, where the programming of the switch multiplexer only needs to be performed once for each system.

[0082] FIG. 8 is a flowchart illustrating an encoding system according to certain aspects of the present invention. The method may be executed by one or more IC devices 202 and 230. In step 802, the one or more IC devices 202 may determine the type of physical interface to be used for communication between the two devices in the wireless mobile terminal. The type of the physical interface may be one of multiple types of physical interfaces supported by at least one of the two devices. One or more of these two devices may include, for example, an N-phase encoder and a differential encoder.

[0083] In step 804, the one or more IC devices 202 may select an encoder to generate encoded data consistent with the type of physical interface used for communication between the two devices. This data can be communicated through a bus with multiple connectors that communicatively couple the two devices. The plurality of connectors may include at least some bidirectional connectors. The connector may include an electrical or optical connector.

[0084] According to certain aspects described herein, an encoder may provide encoded data in the form of a differentially encoded signal. Configuring the plurality of drivers to receive the encoded data may include putting one or more outputs of another encoder into a high impedance mode. The other encoder may include an N-phase encoder.

[0085] According to certain aspects described herein, the selected encoder provides options for using the phase state of the first pair of connectors, the polarity of the second pair of connectors, and the selection of at least one undriven connector. Coded data in the form of a sequence of symbols that are combined to be coded. The first pair of connectors may include the same wires as the second pair of connectors or at least one different wire. Configuring the plurality of drivers to receive the encoded data may include putting one or more outputs of the differential encoder into a high impedance mode.

[0086] In step 806, one or more IC devices 202 may be configured with multiple drivers to receive the encoded data from the encoder and drive the communicatively coupled according to the type of physical interface used for communication between the two devices. Multiple connectors for these two devices. The multiple drives can be configured by controlling multiple switches to couple the output of the encoder to the multiple drives.

[0087] In one aspect of the present disclosure, the encoded data may be related to a camera or a display controlled by one of the two IC devices.

CN 104412552 Β

[0088] FIG. 9 is a diagram 900 illustrating a simplified example of a hardware implementation of a device employing a processing circuit 902. The processing circuit 902 can be implemented by a bus architecture generally represented by the bus 920. Depending on the specific application of the processing circuit 902 and overall design constraints, the bus 920 may include any number of interconnecting buses and bridges. The bus 920 will include one or more processors and/or hardware modules (consisting of a processor 916, modules or circuits 904, 906 and 908, a number of different encoders 910, a line driver that can be configured to drive connectors or wires 914, and a computer The various circuits represented by the readable storage medium 918) are linked together. The bus 920 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0089] The processor 916 is responsible for general processing, including executing software stored on the computer-readable storage medium 916. This software, when executed by the processor 916, causes the processing circuit 902 to perform the various functions described above for any particular device. The computer-readable storage medium 918 may also be used to store data that is manipulated by the processor 916 when executing software. The processing circuit 902 further includes at least one of the modules 904, 906, and 908. Each module may be a software module running in the processor 916, a software module resident/stored in the computer-readable storage medium 918, one or more hardware modules coupled to the processor 916, or some combination thereof.

[0090] In one configuration, the device 900 for wireless communication includes means 904 for determining an operation mode for communication between two IC devices, and for selecting one of the encoders 910 to provide A device 906 for transmitting encoded data on a plurality of connectors 914, and a device 908 for configuring a plurality of drivers 912 to receive the encoded data from the encoder 910 and drive the connectors and/or wires 914. The aforementioned means may be one or more of the aforementioned modules of the device 900 and/or the processing circuit 902 of the device 902 configured to perform the functions described by the aforementioned means. For example, the aforementioned means may be implemented using a certain combination of the processor 206 or 236, the physical layer driver 210 or 240, and the storage media 208 and 238.

[0091] It should be understood that the specific order or level of each step in the disclosed process is an illustration of exemplary methods. It should be understood that based on design preferences, the specific order or hierarchy of the steps in these processes can be rearranged. The accompanying method claims present the elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0092] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be easily understood by those skilled in the art, and the general principles defined in this article can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown in the text, but should be granted the full scope consistent with the linguistic claims. The quotation of the singular form of the element is not intended unless specifically stated. It means "there is one and only one", but "one or more". Unless specifically stated otherwise, the term "some" refers to one or more. The elements of various aspects described throughout the present disclosure are all structural and functional equivalents currently or in the future known to those of ordinary skill in the art, which are expressly incorporated herein by reference, and are intended to be covered by the claims. In addition, any content disclosed in this article is not intended to contribute to the public, regardless of whether such disclosure is explicitly stated in the claims. No claim element should be construed as a device plus function, unless the element is explicitly stated using the phrase "device for ...".