Three phase and polarity encoded serial interface

(54) Title: THREE-PHASE SERIAL INTERFACE E (57) Summary:

CODED BY POLARITY (30) Unionist Priority: 3/2/2007 us 11 / 712,941 (73) Owner (s): Qualcomm Incorporated (72) Inventor (s): George A. Wiley (74) Attorney (s): Montaury Pimenta , Machado & Lioce (86) International Order: pct 11Ξ2008055566 of 29/02/2008 (87) International Publication: wo 2oos / io9478de 12/09/2008

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THREE-PHASE AND POLARITY-CODED SERIAL INTERFACE

FUNDAMENTALS

Field

The present invention generally relates to high-speed serial communication. More particularly, the invention relates to three-phase modulation data encoding schemes for high-speed serial communication.

Foundations

In the field of high-speed serial communication, the demand for ever-increasing data rates continues to grow.

Many conventional high-speed serial interface systems use non-return data encoding to zero (NRZ) with separate data and clock signals. This separation of data and clock signals, however, typically results in bias between the two signals, limiting the maximum possible rate of interface link data.

Typically, the bias elimination circuitry is used at the receiving end of the serial interface to eliminate bias between the data and clock signals. Consequently, both the real state requirements and the serial interface link initialization time are increased, with the latter becoming disadvantageous when the interface is being used intermittently in a low task cycle to minimize system power consumption. .

Other conventional serial interface systems are more immune to bias through the use of strobe data and signals, but still suffer from bias problems when operating at high speeds.

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In addition, certain integrated receiver devices are typically built with a slower logic as they have larger characteristic sizes in order to achieve high voltages. This is the case, for example, for the integrated LCD Controller Actuator circuits that are used to drive LCD panels. As such, it would be difficult to implement a high-speed serial interface for such devices using conventional systems.

What is needed, therefore, is a high-speed serial interface that solves the problems described above of conventional serial interface systems. In addition, a high-speed serial interface with increased capacity and reduced power consumption compared to conventional systems is required.

BRIEF SUMMARY OF THE INVENTION

A serial interface provided here.

In one aspect, the high-speed, high-speed serial interface uses a three-phase modulation data encoding scheme to encode data and clock information together. Accordingly, the need to have a joint bias elimination circuit at the receiving end of the interface is eliminated, resulting in reduced link initialization time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems with separate conductors for data and clock information. In another mode, the serial interface allows data to be transmitted to

3/27 any speed without the receiving end having prior knowledge of the transmission data rate.

In another aspect, the high-speed serial interface uses a polarity-encoded three-phase modulation data encoding scheme to encode data and clock information together. This, in addition to the advantages described above, further increases the link capacity of the serial interface allowing more than one bit to be transmitted in any single baud interval.

In an additional aspect, the polarity-encoded three-phase modulation data encoding scheme is used to implement high-speed serial interfaces for certain receiver drivers with slower logic circuits. By encoding at least two bits per transition on the interface, the encoding scheme allows the data transition rate to be equal to half the normal serial data rate.

A high-speed interface employing a three-phase modulation data encoding scheme provided here draws half the current from other high-speed interfaces using the same drivers. This is because only one trigger output is active at a time instead of having two outputs simultaneously active as is commonly the case on other serial interfaces (for example, data and clock or data and strobe). This reduction in power consumption is coupled with the ability of a high-speed interface employing the three-phase modulation data encoding scheme to send data at a rate at least twice that of other serial interfaces.

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Additional modalities, characteristics and advantages of the present invention, in addition to the structure and operation of the various modalities of the present invention are described in detail below with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The attached drawings, which are incorporated here and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to allow a person skilled in the relevant technique to create or make use of the invention.

Figure 1 illustrates illustrative transitions in a level 3 differential data coding scheme;

Figure 2 shows a circular state diagram;

Figure 3 is an example that illustrates a three-phase modulation data encoding scheme;

Figure 4 illustrates a serial interface transmitter for implementing a three-phase modulation data encoding scheme;

Figure 5 illustrates current flow situations that correspond to the coding states according to a three phase modulation data coding scheme;

Figure 6 illustrates an illustrative data recovery circuit for a three-phase modulation data encoding scheme;

Figure 7 illustrates the impact of timing deviations on the three-phase modulation data coding scheme of Figure 3;

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Figure 8 is an illustrative status table of a polarity-encoded three-phase modulation data encoding scheme;

Figure 9 is an example that illustrates a polarity-encoded three-phase modulation data encoding scheme according to the state diagram of Figure 8;

Figure 10 illustrates an illustrative implementation of signal conductors on a printed wiring panel to activate three-phase modulation data encoding schemes;

Figure 11 illustrates an illustrative implementation of the signal conductors on a cable to activate the three-phase modulation data encoding schemes;

Figure 12 illustrates an illustrative state diagram of a polarity encoded three phase modulation data encoding scheme;

Figure 13 illustrates an illustrative data recovery circuit for a polarity encoded three phase modulation data encoding scheme;

Figure 14 illustrates an additional circuitry of the data recovery circuit illustrative of Figure 13;

Figure 15 illustrates an illustrative data decoder for decoding the output of the data recovery circuit of figures 13 and 14.

The present invention will be described with reference to the accompanying drawings. The design in which the element appears first is typically indicated by the leftmost digits in the corresponding reference number.

DETAILED DESCRIPTION

This specification describes one or more modalities that incorporate the characteristics of this

6/27 invention. The described modalities merely exemplify the invention. The invention modalities The invention is limited to the ones defined by the illustrative specification, references in the one modality whether or not they can be scope of the described ones. attached claims.

The described modalities, a modality, etc. indicate that the described modalities may include a particular feature, structure, but each modality may not necessarily include the particular feature or structure. Furthermore, such phrases do not necessarily refer to the same modality. In addition, when a particular feature or structure is described in relation to a modality, it is considered to be included in the knowledge of those skilled in the art if it affects that feature or structure in relation to other modalities if explicitly described.

The modalities of the invention implemented in hardware, firmware, software, or any combination thereof. The modalities of the invention can also be implemented as instructions stored in a machine-readable medium, which can be read and executed by one or more processors. A machine-readable medium can include any mechanism for storing or transmitting information in a machine-readable form (for example, a computing device). For example, a machine-readable medium may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; fiash memory devices; electrical, optical, acoustic or other forms of propagated signals (for example, carrier waves, infrared signals, digital signals, etc.) and others. Additionally, firmware,

7/27 software, routines, instructions can be described here as responsible for carrying out certain actions. However, it must be appreciated that such descriptions are for convenience purposes only and that such actions, in fact, result from computing devices, processors, controllers, or other devices running firmware, software, routines, instructions, etc. .

Data Encoding_with Information

Built-in Timing

As discussed above, in order to eliminate bias between the data and clock signals or the need to have a bias elimination circuit set on a serial interface, it is desirable to encode the data and clock information together ( or timing information embedded in the data signal). A common technique for doing this is to use a differential data encoding scheme, where the data and clock information is encoded together in the state transitions of a single signal.

Most differential data encoding schemes are differential level schemes, where state transitions are defined in terms of changes in the clock level (magnitude).

of the data signal

Figure 1 illustrates illustrative transitions in a 3-level differential data coding scheme. According to the scheme in figure 1, a signal level (voltage) transition from: -V to 0 is a logical 0, from -V to + V is a logical 1, from 0 to -V is a logical 0, from 0 to + V is a logical 1, from + V to 0 is a logical 1, and from + V to -V is a logical 0.

Illustrative transitions 102 and 104 illustrate transitions of two signal levels where the signal level

8/27 changes from -V to + V. Transition 102 includes a first transition from -V to 0 followed by a second transition from 0 to + V, to transmit a data sequence 01. Transition 104 includes a single transition from -V to + V to transmit a logical 1.

However, as illustrated in Figure 1, because the signal slew rate is slow compared to the response time of the data recovery circuit set at the receiving end, both transitions 102 and 104 appear identical and are interpreted as 01 by the set of recovery circuits. Similar transition decoding problems occur in transitions from + V to -V in the case illustrated in Figure 1, or when the slew rate is faster than the response time of the data recovery circuit.

This ambiguity in decoding state transitions is due to the fact that there are high transitions that must pass through the intermediate states in order to reach a desired state. A differential data encoding scheme with circular state transitions is therefore necessary to resolve ambiguous state transitions in differential data encoding schemes.

Differential Data Coding with Circular State Transitions

Figure 2 illustrates a circular state diagram 200, which can be used to define state transitions in a differential data coding scheme. According to state diagram 200, data is encoded based on the transitions between three states a, b and c. Note that the transition between any two states (a to b, b to a, b to c, c to b, a to c and c to a) occurs in a single step without crossing states

9/27 intermediaries. As such, differential data encoding schemes based on state diagram 200 are free from state transition decoding problems, as discussed above.

Figure 3 illustrates a three-phase modulation data encoding scheme 300 based on circular state diagram 200 in figure 2. According to data encoding scheme 300, a three-phase signal that rotates in two directions is transmitted using three conductors A, B and C. The three signals (carried by conductors A, B and C) that create the three-phase signal are independent, with each signal being 120 degrees out of phase with respect to the other two.

At any given moment, exactly two of conductors A, B and C carry a signal, with data encoding states being defined in terms of signal flow between the conductors. In one embodiment, three states (corresponding, respectively, to states a, b, and c in figure 2) are defined with the signal flow from A to B, B to C and C to A. The transitions between the three states are then defined according to state diagram 200 to ensure circular state transitions. In one embodiment, the clockwise transitions (A to B) to (B to C), (B to C) to (C to Ά) and (C to A) to (A to B) are used to transmit a 1 logical, while counterclockwise transitions (B to C) to (A to B), (A to B) to (C to A) and (C to A) to (B to C) are used to transmit a logical 0.

Referring again to Figure 3, an example of data encoding using the three-phase modulation scheme is illustrated. Signals 302, 304 and 306 illustrate voltage signals applied to conductors A, B and C, respectively. At any time, a first driver is

10/27 coupled to a positive voltage (+ V, for example), a second conductor is coupled to a negative voltage (-V, for example), while the remaining third conductor is an open circuit. As such, the encoding state is determined by the current flow between the first and second conductors. It is also noted that only one of the states (A to B), (B to C) and (C to A) can be true at any time as illustrated by signals 308 (A&gt; B), 310 (B&gt; C) and 312 (C to A), with clockwise state transitions used to transmit a logical 1 and counterclockwise state transitions used to transmit a logical 0. In one embodiment, signals 308, 310 and 312 are generated using comparators that compare voltages across conductors A, B and C.

Figure 4 illustrates a serial interface transmitter circuit 400 for implementing the three-phase modulation data encoding scheme 300 of figure 3. Circuit 400 is implemented using the current driver circuit assembly. Other circuit implementations also exist as can be appreciated by a person skilled in the art based on the teachings presented here.

circuit 400 includes a plurality of current sources 402 a to f that can be coupled using switches 404a-f to the first ends of conductors A, B and C. The second ends of conductors A, B and C are coupled together using the terminating impedances 406a-c. In one embodiment, each of the conductors A, B and C has a natural impedance of Zor value with terminating impedances 406a-c, each having an impedance value of 3Z₀.

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At any given time, exactly two of the switches 404a-f are closed to cause a current to flow between exactly two of the conductors A, B and C. As such, there is a single path at any time in the circuit. In addition, according to coding scheme 300, the current can only flow from conductor A to conductor B, from conductor B to conductor C, or from conductor C to conductor A. These three current flow situations correspond to the only three valid coding states of the data coding scheme 300 and are illustrated in figure 5 with respect to the transmitting circuit 400.

Data Recovery Circuit

At the receiving end of the serial interface, a data recovery circuit is used to decode the data transmitted by the transmitting circuit. In one embodiment, the voltages across the 406a-b terminating resistors in the transmitter circuit 400 are monitored to detect state transitions. For example, signals similar to signals A&gt; B 308, B&gt; C 310 and OA 312 of figure 3 are generated, where at any time exactly one of these signals is high, indicating the current encoding state.

Figure 6 illustrates an illustrative data recovery circuit 600 that can be used to decode the transmitted data according to a three-phase modulation data encoding scheme. Another implementation of data recovery circuit can also be used as would be understood by those skilled in the art based on the lessons presented here.

The data recovery circuit 600 includes first, second and third layers 610, 624 and 638 of D flip flops and a multiplexer circuit 646.

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The data recovery circuit 600 receives input signals A to B 602, B to C 604 and C to A 606. At any time, exactly one of the signals 602, 604 and 606 is high, indicating the current encoding status being transmitted . Signals 602, 604 and 606 are recorded on the first layer D flip flops 612, 614 and 616 respectively.

The first layer 612, 614 and 616 D flip flops capture the most recent state transition as indicated by signals 602, 604 and 606. Note that each of the D 612, 614 and 616 flip flops has its D data entry coupled to a logic 1 and is configured every time its respective clock input 602, 604 or 606 experiences a high edge transition. In addition, note that every time one of the D flip flops 612, 614, 616 is configured, it asynchronously resets the other two first layer D flip flops. In one embodiment, this is done by coupling the Q output of each first loved D flip flop through a raised edge pulse circuit to the reconfigured inputs of the other two first layer D flip flops. For example, in the modality of figure 6,

622 respectively for

<td>, a</td><td>Q output</td><td>From</td>

<td colspan="2">OR gates</td><td> 620</td>

<td> at</td><td>Appetizer</td><td>From</td>

<td>for</td><td colspan="2">make sure</td>

616 are only momentarily reconfigured when a non-respective state occurs, the Q outputs of the D flip flops 612, 614 and 616 are coupled to OR 618, 620 and 622 through a circuit set, which ensures that OR 618, 620, and 622 are provided only with a narrow positive pulse and not a continuous signal of one. For example, the Q output of D flip flops 612 is coupled to OR 620 and 622 gates via an AND gate,

13/27 that receives as inputs said output Q and an inverted and delayed version of it.

The second layer D flip flops 626, 628 and 630 are configured as toggle flip flops with their Q_bar outputs connected to their D inputs. Accordingly, the second layer flip flops 626, 628 and 630 toggle at the rising edges of their respective clock input signal 602, 604 and 606. Note that the rising edges at signals 602, 604 and 606 correspond to state transitions in the data coding scheme. As such, since exactly one state transition can occur at any time, only one of the second layer D flip flops 626, 628 and 630 toggles at any time. The Q_bar outputs of flip flops 626, 628, 630 enter a three-input XOR port 632 to generate a Rx_Clk 636 receiver clock. Note that receiver clock 636 will toggle whenever any of the Q_bar outputs of flip flops 626 , 628 and 630 toggles, thus generating a half-rate watch.

The third layer D flip flops 640, 642 and 644 have clock inputs triggered respectively by signals A to B 602, B to C 604 and C to A 606. Its D inputs are cross-coupled with Q outputs of the first layer, so that the Q output of the first layer flip flop 616 is coupled to input D of the flip flop 640, the Q output of the first layer flip flop 612 is coupled to input D of flip flop 642, and output Q of first layer flip flop 614 is coupled to input D of flip flop 644.

As such, the third layer flip flops 640, 642 and 644 capture state occurrences from C to A, A to B and B to C, respectively, and send a logical 1 for transitions (C to A) to (A for B), (A for B) for (B for C) and (B for C) for (C for A),

14/27 respectively. These transitions are clockwise transitions as shown above with respect to figure 3. For counterclockwise transitions, flip flops 640, 642 and 644 all send the logical 0. Note that since exactly a state transition can occur at any time, only one of the Q outputs of the flip flops 640, 642, 644 can be a logic 1 at any time.

The Q outputs of the flip flops 640, 642, 644 enter a multiplexer circuit 646, with the Q outputs of the first flip flop layer 610 providing the selected inputs from the multiplexer. In one embodiment, the multiplexer 646 includes a layer of AND 648, 650 and 652 gates followed by an OR gate with three inputs 654. The AND 648, 650 and 652 gates provide the inputs of the OR 654 gate, which provides output signal 656 of the data recovery circuit 600. Note that the output signal 656 is a logical 1 whenever any of the AND gates 648, 650 and 652 sends a logical 1, which only occurs in time state transitions, as described above. Accordingly, the output signal 656 is a logical 1 for clockwise state transitions and a logical 0 for counterclockwise state transitions, thus having the ability to retrieve information encoded according to the three-phase modulation scheme.

Impact of Timing Deviation on Modulation

Three-phase

Figure 7 is an example 700 that illustrates the impact of timing deviations on the three-phase modulation data and coding scheme. As illustrated in figure 7, the timing deviation between signals A 702, B 704 and C 706 of the data signal and three-phase clock causes the phase to overlap the three-phase signal. Typically, this timing deviation may be due to differences in

15/27 signal between conductors A, B and C. As a result, ambiguous conditions can appear on signals A&gt; B 708, B&gt; C 710 and OA 712, which represents the inputs of the data recovery circuit. Fortunately, however, these ambiguous conditions can be resolved by adding a voltage or current deviation, as illustrated in signals 714, 716 and 718.

Polarity-Coded Three-Phase Modulation

As described above, the three-phase modulation data encoding scheme uses hourly state transitions to transmit logic and counterclockwise state transitions to transmit logical zeros. As such, exactly one bit of data is transmitted during each state transition, either hourly or counter-clockwise.

However, the capacity of the three-phase modulation data encoding scheme can be further increased by exploring the polarity of the coding states, in addition to the ability to target state transitions. Referring again to figure 5, for example, the current flow polarity can be used to generate additional encoding states such as A for B positive, A for B negative, B for C positive, B for C negative, C for A positive, C to A negative. Having twice the number of encoding states, the number of state transitions, and subsequently, the number of data bits that can be encoded during each state transition can be increased. This coding scheme is referred to as polarity-encoded three-phase modulation.

Figure 8 illustrates an illustrative status table 800 of a polarity-encoded three-phase modulation data encoding scheme. As understood by those skilled in the art based on

16/27 teachings presented here, other state diagrams are also possible with varied, but equivalent, mappings of state transitions to transmitted bits.

According to the state table 800, two data bits are transmitted during each state transition, resulting in a doubling of the capacity of the data coding scheme in figure 3. Note also that the state transitions in the state table 800 will still be circular as shown in state diagram 200 in figure 2.

In other modalities, state transitions in the

800 additional transitions can be split, illustrative status table additionally to generate, thus allowing a greater increase in the capacity of the coding scheme. For example, the state transition (A to B positive, or negative to B to C negative) can be divided into two transitions (A to B positive and B to C positive) and (A to B negative and B to C positive) . For example, from state A to positive B , the next state can be any of the following five states:

A for B negative, B for C positive, B for C negative, C for A positive or C for A negative. This allows log2 &lt;5) or approximately 2.3216 bits of information to be encoded in a single state transition. Using this technique, it is possible to encode 16 bits of information in 7 consecutive state transitions.

Figure 12 illustrates an illustrative state diagram 1200 based on the polarity-encoded three-phase modulation data encoding scheme, which illustrates all possible state transitions between different encoding states.

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Figure 9 is an example 900 that illustrates a three-phase polarity-encoded data encoding scheme according to the state diagram 800 of figure 8.

A three-phase signal that rotates in two directions is transmitted using three conductors A, B and C. The three signals 902, 904 and 906 (carried by conductors A, B and C) that create the three-phase signal are independent, with each signal being 120 degrees out of phase with respect to the other two.

At any given moment, exactly two of the conductors A, B and C carry a signal, with the data encoding states being defined in terms of the signal flow between the conductors and the polarity of said signal flow. Data coding is carried out according to the state transitions as defined in the state diagram 800. In one embodiment, the transitions in the hourly state (A to B to B to C, B to C to C to A and C to A to A to B) are used to transmit the data strings starting with a logical 1 (10 and 11) and counterclockwise state transitions (A to B to C to A, B to C to A to B and C to A to B to C) are used to transmit the data strings starting with a logical zero ( 00 and 01).

Figure 13 illustrates an illustrative data recovery circuit 1300 that can be used to decode transmitted data according to a polarity-encoded three-phase modulation data encoding scheme. Another implementation of data recovery circuit can also be used as would be understood by those skilled in the art based on the teachings presented here. The operation of the 1300 recovery circuit is described below.

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The recovery circuit 1300 receives input signals 1302, 1304, 1306, 1308, 1310 and 1312 from the previous analog circuits. At any time, only one of the signals 1302, 1304, 1306, 1308, 1310 and 1312 can have a value equal to one, depending on which of the coding states occurred. In the implementation, overlaps or spaces between the signs can occur. Input signals 1302, 1304, 1306, 1308, 1310 and 1312 are coupled to the clock inputs of D flip flops 11-16 respectively. Each of the D-16 flip flops 11-16 has its D data input coupled to a logical one, which makes its output Q equal to one each time its respective clock input undergoes a rising edge transition. . For example, D flip flop 11 will have an output Q equal to one every time the input signal 1302 undergoes a rising edge transition, or equivalent, whenever state A to positive B occurs. As such, D flip flops 11-16 capture which of the six states has just occurred, as indicated by their respective Q outputs 1322, 1324, 1326, 1328, 1330, 1332. Since only one state can occur at any time, only one of the outputs 1322, 1324, 1326, 1328, 1330, 1332 can continue to have a value equal to one at any time. As will be further described below, there will be a short overlap whenever a new state occurs with Q outputs corresponding to the current state and the new state having a value equal to one for the duration of the delay to reconfigure the flip flops.

When either state is captured by one of the D flip flops 11-16, the other flip flop will be reconfigured. In circuit 1300, this is achieved using the OR 1-6 ports, which generate reconfiguration signals for the respective D flip flops 11-16. OR 1-6 gates each receive pulses as inputs

19/27 caused by the rising edges of the Q flip flop outputs 11-16 except for the Q output of their respective D flip flop and a reconfiguration signal 1314. Accordingly, the output of the OR 1 gate will be equal to one every time that any state beyond A to B positive occurs or if the reconfiguration signal 1314 is determined. On the other hand, when the A to B positive state occurs and the reconfiguration signal 1341 is not determined, the OR 1 gate will send a value equal to zero.

In one embodiment, to ensure that D flip flops 11-16 are only reconfigured momentarily when a non-respective state occurs, the Q outputs of D flip flops 11-16 are coupled to OR 1-6 ports via a circuit set, which ensures that OR 1-6 gates are only provided with a pulse and not a continuous signal of a value equal to one. For example, the Q 1322 output of the D flip flop 11 is coupled to the OR 2-6 gates via an AND 71 gate. The AND 71 gate receives input Q 1322 and a delayed inverted version of output Q 1322. Note that just before the D flip flop 11 captures an occurrence of positive state A to B, the output of the AND 71 gate is equal to zero since output Q 1322 is equal to zero (D flip flop 11 will have been reconfigured previously). On the other hand, the delayed inverted version of Q has a value equal to one. When positive input A to B occurs, output Q 1322 changes to one. The delayed inverted version of Q maintains a value equal to one for the duration of the delay (generated by a delay element as illustrated) before changing to zero. Accordingly, for the duration of the delay, the AND 71 gate will send a value equal to one, creating a pulse that reconfigures flip flops 12-16.

D flip flops 21-26 are used to generate a dual data rate clock signal Rx-Clk 1316, which

20/27 transits every time a new entry is presented. D flip flops 21-26 receive input signals 1302, 1304, 1306, 1308, 1310 and

1312. D flip flops 21-26 also receive the reconfiguration signal 1314. As illustrated in figure 13, each of the D flip flops 21-26 has its Q_bar output fed back to its D data input. As such, for each D flip flop 21-26, whenever its respective input clock signal undergoes a rising edge transition, its Q_bar output will toggle from one to zero or from zero to one. The Q_bar outputs of the D flip-flops 21-26 enter together through the XOR 35 and 36 ports, as shown in figure 13. The outputs of the XOR 35 and 36 ports, in turn, enter together through the XOR 37 port. XOR 37 will send a value equal to one whenever an odd number of outputs Q__bar from D flip-flops 21-26 has a value equal to one. Since only one of the Q_bar outputs of D flip-flops 21-26 will toggle at any time while the others will maintain the same value, the XOR 37 output will toggle for each change at inputs 1302, 1304, 1306, 1308, 1310 and 1312. This generates a Rx_Clk 1316 dual data rate clock signal. In one embodiment, a delay element 62 is used to ensure that the Rx_Clk signal is in sync with the other signals that are sent by the 1300 data recovery circuit. .

The OR 31 gate generates the signal Rx_Data_Polarity 1318, which indicates whether the state that has just occurred has positive or negative polarity. The OR gate 31 receives inputs Q 1322, 1324 and 1326 from D flip-flops 11-13, respectively. As such, the OR 31 gate sends a value equal to one each time a positive polarity input (A to B positive, B to C positive or C to A positive) occurs. On the other hand, the Rx_Data_Polarity 1318 signal will

21/27 a value equal to zero when a negative polarity state occurs.

OR ports 32, 33 and 34 are used to capture respectively a state C for A (positive or negative polarity), an state A for B (positive or negative polarity), and a state B for C (positive or negative polarity) occurs regardless of polarity. For example, the OR gate 32 receives inputs Q 1326 and 1332 from D flip-flops 13 and 16, respectively. As such, the OR 32 gate sends a value equal to one whenever C for A positive or C for A negative occurs.

The outputs of the OR 32-34 ports are coupled to the D data inputs of the D flip-flops 41-46, as shown in figure 13. The output of the OR 32 port is coupled to the D inputs of the D flip-flops 41 and 44. Similarly, the output of the OR 33 port is coupled to the D inputs of the D flip-flops 42 and 45, and the output of the OR gate 34 is coupled to the D inputs of the D flip-flops 43 and 46. At the same time, the clock inputs of D flip-flops 41-46 are respectively coupled to inputs 1302, 1304, 1306, 1308, 1310, and 1312. Accordingly, for example, D flip-flop 41 will have a Q cm output value equal to one whenever the previous state is C for A (regardless of polarity) and the current state is A for B positive. With reference to figure 12, this corresponds to the clockwise transitions to the positive A to B state from any of the positive C to A or negative C states. Similarly, D flipflop 44 will have an output Q equal to one whenever the previous state is C for A (regardless of polarity) and the current state is A for B negative. With reference to figure 12, this corresponds to the clockwise transitions from state A to negative B for

22/27 states C for A positive or C for A negative. Accordingly, D flip-flops 41-46 each capture one of the six clockwise transitions in state diagram 1200 in figure 12.

The Q outputs of the D flip-flops 41-46 enter together with the respective Q outputs of the D flip-flops 11-16 on the respective AND 51-56 gates, as shown in figure 13. For example, the Q output of the D flip-flops flop 41 enters together with the Q 1322 output of the D flip flop 11 on the AND 51 gate. The AND 51-56 gates are used to ensure that only one of the six time transitions is reflected at any time. In other words, only one of the outputs of AND 51-56 gates can have a value equal to one at any time. The outputs of AND 51-56 gates enter an OR 61 gate together to generate Rx_Data_Phase 1320. Accordingly, Rx_Data_Phase 1320 has a value equal to one every time a time phase transition occurs and a value equal to zero otherwise. Note that Rx_Data_Phase 1320 can have a value of zero if a counterclockwise transition or a polarity transition only (same phase transition; for example, A to B positive to A to B negative) occurs. For example, if the current state is A to B positive, recovery circuit 1300 will send the same values ​​to Rx_Data_Polarity 1318 and Rx_Data_Phase 1320 if the next state is C for A negative or A for B negative. Therefore, the additional circuitry is necessary to distinguish between these types of transitions.

Figure 14 illustrates an additional circuit assembly 1400 for capturing polarity transitions only. Inputs for circuitry 1400 include input signals 1302, 1304, 1306, 1308, 1310 and 1312 and outputs Q 1322, 1324, 1326, 1328, 1330 and 1332 from

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D flip flops 11—16. Circuit set 1400 includes D flip-flops 71-76 which are used to capture polarity transitions only. For example, D flip-flops 71 receive input signal 1302 as clock input and output signal Q 1328 as D data inputs and are used to capture negative A to B to A to B positive transitions. Note that when a negative A to B occurs, output Q 1328 will have a value equal to one. Subsequently, when A to B positive occurs, output Q 1328 will continue to have a value equal to one for the duration of the delay between the time when output Q 1322 changes the value to one and the time when flip flops 12-16 are reset . During this delay duration, both input signal 1302 and output Q 1328 will have a value of one, causing output Q of D flip-flop 71 to change to a value of one. This also makes the output of the AND 81 gate a value equal to one. The operation of D flip-flops 72-76 and the respective AND 82-86 gates is similar.

The outputs of AND 81-86 gates enter together in an OR 87 gate, which generates the output signal Rx_Data_same_phase 1402. The output signal Rx_Data_same_phase 1402, in this way, has a value equal to one every time that any of the six possible transitions of polarity state just occur. As such, Rx_Data_same_pahse 1402 can be used to determine whether a transition is polarity only or counterclockwise, whenever Rx_Data_phase 1320 of circuit set 1300 has a value of zero.

Note that circuit set 1400 operates in conjunction with data recovery circuit 1300 in figure 13. In other words, output Rx_Data_same_phase 1402 from circuit set 1400 is provided together

24/27 with outputs Rx_Clk 1316, Rx_Data_polarity 1318, and Rx_Data_phase 1320 of circuit 1300 for a subsequent decoding stage for decoding, as will be further illustrated below.

Figure 15 is an illustrative embodiment 1500 of a decoder 1502 that can be used to decode the outputs generated by the data recovery circuit shown in figures 13 and 14. Decoder 1502 receives seven sets of input 1504, 1506, 1508, 1510 , 1512, 1514 and 1516. In illustrative mode 1500, each input set is a 3-bit input with one bit for each of the outputs Rx_Data_phase, Rx_Data_polarity, and Rx_Data_same_phase of the data recovery circuit illustrated in figures 13 and 14. Decoder 1502 decodes seven sets of 3-bit input received to generate 16-bit data output 1518. Other variations of decoder 1502 are also possible as can be understood by those skilled in the art. For example, the decoder 1502 can receive more or less than seven sets of input and / or generate a data output of different length 1518.

Illustrative Serial Interface Implementations

Figures 10 and 11 illustrate illustrative serial interface implementations employing the three-phase modulation data encoding schemes of the present invention. Figure 10 illustrates an illustrative implementation 1000 on a printed wiring panel. As illustrated, three conductors A, B and C are interspersed with earth in an upper layer with a dielectric core separating them from earth in a lower layer. In one mode, the impedance of any conductor to ground has a value equal to Z0. Figure 11 illustrates an illustrative implementation 1100 using a triple twisted cable.

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Three-Phase Modulation for Digital Mobile Display Interface (MDDI)

MDDI is an inexpensive and low power consumption transfer mechanism that allows the transfer of very high speed serial data through a short-range communication link between a host and a client. In certain embodiments, an MDDI interface can benefit from the use of the three-phase modulation data encoding schemes of the present invention.

In one aspect, an MDDI host can comprise one of several types of devices that can benefit from using the data encoding schemes of the present invention. For example, the host may be a portable computer in the form of a portable computing device, laptop or similar. It can also be a Personal Data Assistant (PDA), a paging device, or one of many phones or wireless modems. Alternatively, the host may be a portable entertainment or presentation device such as a portable DVD or CD player, or a gaming device. In addition, the host can reside as a host device or control element in a variety of other commercial products planned or widely used for which a high-speed communication link with a client is desired. For example, a host can be used to transfer data at high rates from a video recording device to a storage-based client for improved response, or to a larger, high-resolution display for presentations. In general, those skilled in the art will appreciate the wide variety of modern electronic devices and devices that can be

26/27 benefit from the use of this interface, in addition to the ability to fit older devices with a higher data rate information transport using limited numbers of conductors available in newly added or existing connectors or cables. At the same time, an MDDI client can comprise a variety of devices useful for presenting information to an end user, or presenting a user's information to a host. For example, a micromonitor built into glasses, a projection device built into a hat or helmet, a small screen or even a holographic element built into a vehicle, such as a window or windshield, or multiple speakers, headphones or systems sound for high quality sound or music presentation. Others for presentation include projectors or projection used to present or for film or television images. Other examples include the use of touch keyboards or sensitive devices, voice recognition recording devices, security scanners and so on that can be used to transfer a significant amount of information from a device or system user with little real input. in addition to the user’s touch or sound. In addition, docking stations for computers and car kits or desktop kits and retainers for cordless phones can act as interface devices for end users or other devices and equipment, and employ customers (output or input devices such as a mouse) or hosts to assist with data transfer, especially where high-speed networks are involved. However, those skilled in the art will readily recognize that the present invention is not limited to such meeting information devices,

27/27 devices, with many other devices on the market, and proposed for use, which must provide end users with high quality images and sound, in terms of storage or transport or in terms of presentation during playback. The present invention is useful in increasing data throughput between various elements or devices to accommodate the high data rates required to carry out the desired user experience.

Conclusion

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. It will be apparent to those skilled in the relevant technique that various changes in form and details can be made here without departing from the spirit and scope of the invention. Accordingly, the scope and scope of the present invention should not be limited by any of the illustrative modalities described above, but should be defined only in accordance with the following claims and their equivalences.

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