Digitally controlled a.c. to d.c. power conditioner that draws sinusoidal input current

DIGITALLY CONTROLLED A.C. TO D.C. POWER CONDITIOHeR THA~ DRAWS SINUSOIDAL INPUT CURRENT BACRGRoUND OF THE INveNTIoN Recently there ha~ been an expanded interest in po~er condit~oning eq~ipment that draws ~inusoidal input current from the A.C. line. This need 1~ di6cussed in the articles by E. Kamm entitled ~New Military EMI Specif~cations Affecting the Input Architecture of A.C. to D.C.

Converters~, Proceedings of Powercon 8, 1981, and by M.J.

Kocher and R.L.

Steigerwald entitled ~An A.C, to D.C.

Converter with High Quality Input Wave~orms~, IEEE PESC Conference Rec , 1982. The present invention provides a digital implementation of a voltage feedback loop and a multiplying digital-to-analog converter in a current feedback loop to provide a power conditioner, which draws sinusoidal output current and provides a regulated direct current output voltage and is operable over a wide range of A.C. line frequencies.

BRIEF DESCRIPTION OF T~E DRAWINGS 20The present invention is described by reference to the drawings in which:

Fig. 1 shows a block diagram of the digitally controlled power conditioner of the present invention.

, Fig. 2 shows the control voltage waveforms of the current program loop during one half cycle of the A.C.

line.

Fig. 3 - Shows a block diagram of a digital P~ controller which determines the gain to be used by the curcent progcam loop during the next half cycle of the A.C.

line from a digital error signal and the discrete integral of the digital error sign~l.

~S~l~ Flg. 4 - Show6 the ~wltch1ng f~equency and lnduc~or t1pple current versus (Vln/VOUt) plots for various converter conditions, where ~ ig. 4a l~ for con6tant current hy~teresls control, Pig. 4b is for constant switching frequency control, Fig. 4c ~s for variable current hystere~is control, and Fig. 4d i~ for constant off-time con~rol.

TECHNICAL DESCRIPTION OF THE INVENTIO~ _ Noise generated by high speed switching can upset the operation of a current program loop in A.C. to D.C. power converters. Variable hysteresis control is employed in the present invention so that the highest noise immunity is provided when the switching energy ~and therefore, the noise generation) is the greatest. Variable hysteresis control is employed in the present invention to control the inductor ripple current Irip in proportion to the instantaneous rectified input voltage Vin, where:

I . = K V. ~l) rlp hy ln The power converter utilizes a step up converter which has a switching frequency that is much higher than the A.C.

line frequency. Steady-state operation may, therefore, be assumed in the step-up converter for any averaqe ~ instantaneous input voltag-e.- Using Equation l and the approximations:

~ 25 LlIrip LlICip ; t = - t ~f = __ (2,3) Vin VOut Vin --3- Dn e%pre8sion for the switch1ng f~equency f8~ ~Y be found ln term8 of the current hy~teresis coefficient ~hy~ the ~tep-up converter inductance Ll, and the ~nput and output voltages Vout Vin f ~ 4 ~w hy l out The maximum switching frequency, which occur~ when the input voltage goes to zero, is bounded and is given by fsw,max ~ hy l) In practice, the maximurn switching frequency will not be obtained since a real step-up converter is unable to maintain an output voltage as the input voltage and duty ratio approach zero.

The circuit of Fig. l can be used ~o implement the variable hysteresis curcent program loop of the present invention. The A.C. input line voltage is connected across the lines lO, 12 to a full w~ve rectifying circuit consisting of the rectifiers 14, 16, 18 and 20. The rectified output which is labeled Vi~ appears at the junction node 22 of a high-permeability core of soft iron, or other suitable material that has magnetic hysteresis characteristics and filter inductor Ll which is coupled ~-between the node 22 and the output terminal 24 and a : - 25 capacitor C2, which has a relatively small value compared to the filter capacitor Cl. C2 is used to by pass the A.C.

line so the ripple current in the inductance Ll flows : through C2, and not back through the A.C. power system.

The output voltage VOUt is developed across the output terminals 24, 26 , the inductance ~l' the diode Dl, the capacitor Cl and the ~ransistor Ql form a step up or boost converter. The diodes D2 and D~, the capacitor C3 5~ and the resl~tors Rg ~nd Rl2 form a snubber clrcui~ ~or reducing ~wltchln9 tr~n~lents on the power tcan6istor Ql~ A diode D4 is in series with the re~tor ~12. Rl~ ls coupled to the ~unction point of the inductor L2 and ehe anode of the diode D2 and the drain D of the fleld-effect power tran~istor Ql' The ~ource S of the field-effect trans~stor Ql i6 grounded. ~he gate G of the field-effect receives the output of the amplifier A6. The amplifier A6 supplies a logic ~l~ and a logic "0" to the transistor Q~ so that it acts as a switch under control of the flip~flop Fl to provide step-up conversion.

The node 22 i5 also coupled to a voltage dividing network consis~ing o the resistors Rl and R2,. R2 i~ coupled to a filtering capacitor C4. The junct~on point of R2 and C4 is coupled to the no~-inverting input terminal of operational amplifier Al which is connected so that its inverting input terminal is directly connected to its output so that the amplifier Al acts as a voltage ollower. The output of the amplifier Al is coupled through the resistor R3 to a multiplying digital-to-analog converter (MDAC~. The MDAC is supplied a gain signal cn from the PI controller which has an input coupled to the output terminal 24. The ~esistor R3 is coupled to the MDAC controller and receives the voltage VLINE from the amplifier Al. Under the control o the gain signal from the PI controller, the gain-controlled analog output signal of the MDAC is supplied to the inverting input terminal of the amplifier A3. The amplifier A3 also has a feedback resistor R4 coupled between its output and its inverting input terminal. The output of the ampli~ier A3 ;s coupled to the voltage-dividing network consisting of the resistors R5 and R6 to the inverting input terminal, one side of a dual comparator A~B.

The other side of the inverting comparator A~A is coupled to receive the output from the amplifier A3 on its non-inverting input terminal.

~ he lower end of th~ cap~cltor C2 1s coupled to a junct~on of the r~lstor R7 and the re81st~r ~ the other end of which i8 grounded. The ~lgnal obtained at the junction node 28 of these two resist~rs i8 coupled thcough the resi~tor R7 to the inverting input term nal of an amplifier A5. ~he amplifier ~5 ha~ a feedback resistor fro~ its output to it6 inverting lnput terminal.

The output of the amplifier AS is connected to the inverting input terminal of the comparator A~A and al~o to the noninverting input terminal of comparator A4B. The outputs ofthe comparators A4A and A4B are coupled to the clear and the set terminal~ of the flip-flop ~l respectively.

In operation, the 8 bit multiplying digital-to-allalog convertor (MDAC) multiplies a reference voltage V~INE (that 15 is proportional to the instantaneous input voltage) by the quantized current gain value cn supplied from the proportional-integral (PI) controller in the voltage regulation loop to provide an upper (or ~turn-off~) control voltage VCOntl. The resistive voltage division provided by RS and R6 supplies a lower (or ~turn-on~ control voltage VCOnt2. The current flowing through the inductor Ll is measured using a small, (on the ocder of 0.l Ohm) resistor R The amplifier A5 provides a voltage VIL, which is proportional to the instantaneous inductor current through Ll to the inverting input terminal of the tucn-on ~ comparator A4B and:to the non-inverting input terminal of : ~he turn-off comparator A4A.

An S-R flip-flo;p Fl is toggled by the comparators through an amplifier A6 to turn the field-effect transistor switch Ql' which acts as the output stage of the step-up convecter, ON and OFF. The time relationships between VIL, VCOntl, cont2 half cycle of the input A.C. line is shown in Fig. 2. The : differences between the voltage VIL and VCOntl controls the state of the flip-flop Fl, which controls the field-effect transistoc Ql.

~z~ Tr~nsfer functions describing the ga~n of the current program loop ~nd the current hy~tereals coefficient in terms of the qu~ntized current gain value cn and the input voltage Vin are useful for further snalysis. The instantaneous vol~ages drivinq comparator~ A~ and A4A are ~elated to the input vol~age and inductor current through Ycontl ( ~ R2R,~ cn ~ (6) Vin( ) (Rl+R2)R3 2m Ycont2(t) R6 . = . (7) Vcontl( ) S 6 VIL(t) RllR8 8) ILl(t) R7 where m is the number of bits used to represent the quantized current gain value cn and (t) indicates an instantaneous value. During steady-state operation, the average value of the upper and lower control voltages will be equal to the voltage representing the inductor current Vcontl ~cont2 ~ = VIL ~9) :-~ 20 2 The gain of the current program loop may-be expressed as a function of the quantized current gain value I~(t) R2R4R7(0-5Rs+R6) cn ( 1 0 Vin( ) ( l R2~R3(~s~R6)~8Rll 2m ~z~ --7-~ he d1fference between the upper ~nd lower control voltageB, ~hen multiplied by the voltage-to-current gain of Equation 8, determines the inductor rlpple current rip 2 ~ 5 7 Cn Khy R 2~ ~ll) in( ) ~l+R2)~3~Rs~6)Rll 8 The selection of the value of the capacitor C2 is a critical aspect of the design of the unity power factor power conditioner. The cap~citor conducts the ripple current directly to the 6hunt resistor, bypassing the A.C.

line. If the capacitor is large and lf there is no delay between the instant that the inductor current re2ches a threshold and the instant that the power transistoc Ql actually switches states, the cureent program loop will be unconditionally stable. However, if the value of the capacitor C2 is too large, unacceptable harmonic distortion will be produced in the A.C. line current.

A digital proportional-integral (PI) control may be implemented as shown in Fig. 3, and used for output voltage regulation and current gain control in accordance with the present invention. A digital error circuit consisting of an uncompensated analog amplifier A7 and an analog-todigital (A/D) converter, samples and digitizes the error in the output voltage at the sensing of each zero-crossing of the A.C. line with a conventional zero-crossing circuit to produce a digital error signal en. Sampling at the zerocrossing is advantageous since the average output voltage (to a close approximation) is measured, regardless of the magnitude of the ripple component. Furthermore, sampling at the zero-crossings insures that no information ~ill be obtained at the ripple frequency. This prevents the voltage regulation loop from distorting the A.C. line current waveform in an attempt to reduce the output voltage ripple.

,. . .

:L2~$1~ -B~ The d~gital output ~ign~l from the diglta1 PI controller ~djusts, in di6ccete steps, the galn of the current progr~m loop, and iB therefore termed the guanti2ed current gain value. The quantized current gain v~lue ls restricted to the 2 integec values ~hich may be represented by An m-bit digital word. As ~n ex~mple, if an 8 bit binary representation is used the digital PI controller, the decimal representation of the quantized current gain value cn may range from 0 to 255. Since ~ hardware realization ~s used, the calculation updating the quantized current gain value is completed during the zerocrossings of the A.C. line.

The digital error signal en desccibes the diff.erence between the actual output voltage of the power conditioner at the nth zero-crossing of the A.C. line and a reference voltage Vre.

As an example, if an 8 bit two's complement representation is used in the digital PI controller, the decimal representation of en may range from -128 to +127.

The quanti~ed current gain value cn is calculated from the weighted summation cf two digital signals, The irst digital signal is propoctional to the digita~l error input en. The second digital signal Yn is obtained from the discrete integration of the digital error input en.

Discrete integration is accomplished using an adder and a register to maintain a continuous summation of the digital error input.

y = eO + el + + en (12) A discrete time difference equation may be written Yn ~ Y~ en ~13) `~ ~L2~ where Yn 1 is the stored digital value in the latch which was obtained from the sample prior to the one which yielded the Yn signal.

Weighting coefficients Kp and Ki are provided to adjust the contribution of the proportional and integral signals to the current gain value calculation, respectlvely, Cn - KiYn + Kpen (14) Overflow detection and correction may be implemented in a conventional manner at the outputs of both adders to prevent erroneous operation.

In general, Kp and Ki can take on any value. In the preferred system however, Kp is restrictea to unity and Ki may take on the values: 2, 1, 1/2, 1/4. This is because digital multiplication or division by powers oE two is simply implemented, and because the gain of the digital error amplifier may be used to adjust the overall loop gain.

A PID controller which may be utilized to implement the PI control of the present invention is shown in United 5tates Patent application, Serial No. 773,684, now Patent No. 4,630,187, Power Converter with Duty Ratio Quantization, filed September 9, 19850 In order to maintain a unity power factor, the closedloop frequency response of the output voltage regulation loop must cross through unity gain at a frequency which is less than the frequency of the ripple in the ou~put voltage.

~ If this condition is not met, the output voltage regulation ; loop will distort the input current waveform in an effort to reduce the output ripple voltage.

The digitally controlled power converter of the present invention may alternately ~30 accept a quantized current gain value from an external source, allowing open-loop operation.

`: ~ -1 0 A high per~ormance A.C. to D.C. power condlt1oner ig dlsclosed which u~e~ digltal proportlonal-integr~l con~rol for output voltage regulation and varlabl~ hy~teresis control for current programming. ~ d~gitally controlled analog converter ~i.e., ~ multiplying d~glt~l-to-~nalog conttoller - MDAC) i~ used as the interface between the voltage regulation loop and the current program loop.

The sampling instant of the digital PI controller ~6 determined by the zero-crossing6 of the A.C. llne.

This scales the frequency characteristic6 o~ the closed-loop system with changes in the A.C. line frequency. Power conditioners for different A.C. line frequencies may be implemented with the power conditioner of the present invention since only the output capacitor must be changed to take advantage of the improved dynamic characteristics offered by a higher line frequency. On-the-other-hand, if a ~ingle power conditioner is required to operate over a wide range of A.C. line frequencies, modifications are required to insure that proper operation is retained. This may be accomplished by including circuitry to automatically alter the proportional and integral weighting coefficients as different line frequencies are encountered.

Another approach is to mask some of the zero-crossings when operating at higher line frequencies to maintain a nearly constant sampling rate. Providing an internal clock to determine the sampling instances if zero-crossings are not detected would allow the power conditioner to operate from D.C. as well as A.C. power sources. Care must be taken, however, since the loop gain varies with both magnitude and shape of the input voltage waveform.

The digital control technique of the present invention is also well suited for three-phase applications since precise current balancing is easily obtained. A single PI controller and three step-up convertecs (with isolated D.C.

to u.C. output stages~ are required for a three-phase system. The diqlt~l quantlzed current galn control ~lgn~l may be dellvered to each step-up converter, without any 108~ of accuracy, using, for example, d~gltal optical couplers.

Various control functions may be implemented via the PI controller to develop switching control wavefor~s for the current program loop.

For e~ample, the~e control laws may include: constant 6witching frequency control, constant current hysteresis control, con~tant off-time control, ~nd variable current hysteresis control. Switching frequency and inductor ripple current are plotted against the normalized input voltage for each of the control functions in Fig. 4 and derivations are given below using the symbols defined in Fig. l. (It is assumed that the step-up ~ l5 converter is ideal and operating in steady-state in these : derivations.) Constant Frequency Control. Since the switching frequency is constant, the sum of the on-time and the offtime of the switch must also be constant ton + toff l/fSW = constant (15) Assuming that the inpu~ and output voltages are constant over the dur.ation of the switching cycle and using ; . di : V - L ~ 6 dt the on-time and off-time may be expressed as LlIrip t = ~17 on Vin :

1 2 L 1 I r ~ p tof (as) VOut Vin By ~ubstituting Equations 17 and 18 into Equation 15, an expression for the ripple current i6 obtained.

Vin(V0ut Vln) I ~ ~ (19) sWLlVoUt It is noted that the ripple current goes to zero when the input voltage is e~ual to zero and also when the input voltage is equal to the output volta~e. The maximum ripple current may be found by setting the derivative of Equation 19, with respect to the input voltage~ equal to zero.

dIrip _ = o when Irip ~rip,max (20) dVin Vout VOut I = - when V. = (2~) rip,max ln ~fswLl 2 Constant ~ysteresis Control.

By definition, the ripple current will be constant.

Using Equations 17 and 18, Equation 15 may be solved for the switching frequency LlI r ip LlIr ip ton ~ toff = ~ (221 --fsw Vin VOut in Vin(Vo,~t ~ Vin) sw (23) IripLlVout ~Z9~ -13~ he switching frequency goes to ~ero a~ the lnput voltage goes to zero and ~hen the input volt~ge 1~ equ~l to the output voltage. The maximum switchlng frequency ~y be found by setting the derivative o~ Equation 23, with respect to the input voltage, equal to zero.

VOut VOut w,max when Vin (24) 4LlIrip 2 Constant Off-Time Control. Since the off-time is constant, the on--time may be expressed as ton Tsw off ~2S) where TSw = lJfsw During steady-state operation, the static voltage ; transfer function for the step-up converter is VOut = ~ (26) in 1 - D ; where D is the duty ratio of the power switching transistor. Since the duty ratio is defined as the on-time divided by the switching period ~sw~ Equation 26 may be rewritten as 27 out Tsw~ By combining E~uations 25 and 27, the switching frequency may be solved for Vin f (28) 6w V t toff ~he r~pple curcent 18 found dlrectly fro~ Equatlon 18 off rip (VOut V~n) (29) Ll Varlable Hysteresis Control.

Expressions for the switching freguency and ripple current as a functlon of the input and output voltages are given in Equations 1 and 4.

Rowever, it is interestlng to note -that Equations 1 and 2 may be combined to 6how t = Kh Ll = constant (30) Therefore, variable hysteresis control may al50 be described as constant on-time control.

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