Synchronization system for use in direct sequence spread spectrum signal receiver

44.368/376 Can~d~ SYN~RONIZATION SYSTEM FOR USE IN DIRECT SEQUENKE SPREAD SPECTRUM SIGNAL ~ECEIVER Technical Field Ihe invention relates generally to code division multiplex mg using direct sequence spread spectrum signal processir~, and more particularly, towand signal processing to increase the number of trans~itters multiplexed for a gi~en code le~gth.

Backgroun~ Art In a spread spectrum system, a transmitted signal is spread over a frequency band that is much wider than the minimum bandwidth required to transmit particular information. Whereas in other foLms of mcdulation, such as amplitude modul~tion or frequency modulation, the transmission bandwidth i5 comparable to the bar.dwidth of the information itself, a spread spectrum system t~ spreads an information bandwidth of, for example, only a few kilohertz over a band that is many megahertz wide, by modulating the information with a wideband encoding signal.

Thus, an important characteristic distinguishing spread spectrum syst~ms from other types of broadband transmission systems is that in spread spectrum signal processing, a signal other than the information being sent spreads the transmitted signal.

Spreading of the transmitted signal in typical spread spectrum systems is provided by (l) direct sequence modulation, (2) frequency hopping or (3) pulsed-FM or ~chirp" modulation.

In direct sequence modulation, a carrier is modulated by a digital code sequence whose bit rate is much higher than the information sign~l bandwidth.

Frequen y hokping involves shifting the carrier frequency in discrete increments in a ~attern dictated by a code sequence, and in chirp modulation, the carrier is swept over a wide band during a given pulse interval.

Other, less frequently used, carrier spreading techniques include time hopping, wherein transmission time, usually of a low duty cycle and short duration, is governed by a code sequence and time-frequency hopping wherein a code sequence determines both the transmitted frequency and the time of transmission.

Applications of spread spectrum systems are various, depending upon characteristics of the codes being employed for band spreading and other factors.

In direct sequence spread spectrum systems, for example, wherein the code is a pseudo-random sequence, the composite signal acquires the characteristics of noise, making the transmission undiscernable to an eavesdropper who is not capable of decoding the transmission. ~dditional applications include navigation and ranging with a resolution depending upon the particular code rates and sequence lengths used.

Referer.ce is made to the textbook of R.C.

Dixon, SPread Spectrum Systems, John Wiley and Sons, ~ew ~ork, 1976. especially Chapter 9 for application details.

~3~7,~Q~ .

Direct sequence modulation involves modulation of a carrier by a ccde sequence o~ any one of several different for~ats, such as ~M or FM, although biphase phase-shift keyi~g is the st common.

In biphase phase-shift keying (PSK), a balanced mixer whose inputs are a code sequence and an RF sarrier, controls the carrier to be tran3mitted with a first phase shift of X when tne code sequence is a "1" and with a second phase shift of (18Q + X)~ when the code sequence is a "O".

Biphase phase-shift keyed modulation is advantageous over other forms because the carrier is suppressed in the transmission making the transmission more difficult to receive by conventional equipment and preserving more power to be applied to information, as opposed to the carrier, in the transmission.

Ch æ acteristics of biphase phase-shift keying are given in Chapter 4 of the Dixon text, supra.

The type of code used for spreading the bandwidth of the transnission is preferably a linear oode, particularly if message security is not required, and is a maximal code for best cross correlation characteristics.

Maximal codes are, by definition, the longest codes that could be generated by a given shift register or other delay element of a given length.

In binary shift register sequence generators, the maximum length (ML) sequence that is cap2ble of being generated by a shlft register having n stages is 2n _ 1 bits. A shift register sequence generator is formed fr a shift register with certain of the shift register stages fed back to other s~ages~ The output bit stream has a length depending ueon the number of stages of the register and feedback employed, before the sequence repeats. A shift register having five stages, for example, is capable of generating a 31 bit binary sequence (i.e. 25 - l), as its maxim 1 length (ML) sequence.

Shift register ~L sequence senerators having a large num~er of stages generate ML sequences that repeat so infrequently that the sequences appear to be random, acquiring the attributes of noise, and are difficult detect.

Direct sequen oe systems are thus scmetimes called ~pseudo-noise" systems.

. ~ Properties of maximal sequences are summarized in Section 3~1 of Dixon and feedback connections for max~mal code generators from 3 to lO0 stages are listed in Table 3.6 of the Dixon text.

For a 1023 bit code, corresponding to a shift register having lO stages S with maximal length feedback, there are 512 "l~s and 511 ~onS the difference is l.

Whereas the relative positions of "lns and "O"s vary among ML code sequenc~s, the number of "lns and the number of "O"s in each maximal length sequence are constant for identical ML length sequences.

Because the difference between the number of "lns and the numter of "O"s in any maxLmal len~th sequence is unity, autocorrelation of a maximal linear code, which is a bit by bit comparisGn of the sequence with a phase shifted replica of itself, nas a value of -1, except at the 0 + l bit phase shift area, in lS which correlation varies linearly from -l to ~2n _ 1). A 1023 bit maximal code (2n - 1) therefore has a peak-to-average a~tocorrelation value of 1024, a range of 30.1 db.

It is this characteristic which makes direct sequence spread spectrum transmission useful in code division multiplexing.

Receivers set to different shifts of a co~mon ML code are synchronized only to transmitters having that shift of the comnon code.

Thus, more than one signal can be unambiguously transmitted at the same frequency and at the same tL~e.

In an autocorrelation type multiplexed system, there is a common clock or timing source to which several transmitters and at least one receiver are synchronized.

The transmitters generate a common maximal length sequen oe with the code of each transmitter phase shifted by at least one bit relative to the other codes.

The receiver generates a local replica of the common transmitted maximal length sequence having a code sequence shift that corresponds to the shift of the particular transmitter to which the receiver is tuned.

The locally generated sequence is autocorrelated with the incoming signal by a correlation detector adjusted so as to recognize the level as~ociated with only ~ l-bit synchronization to despread and ex~ract information from only the signal generated by the predetermined transmitter.

~ 2 ~ r3 Because the autocorrelation characteristic of a maximal length code sequence has an offset corresponding to he inverse of the code length, or V/ (2n 1) where V is the magnitude of voltage corresponding to "ln and n is the number of shift register stages, overlap occurs in neighboring channels.

Thus, there is imperfect rejection of unwanted incoming signals.

Unanbiguous signal discrimination thus requires a guard band between channels reducing the nunber of potential transmitters ~or a given code length. A long maximal length sequence compensates for the guard band to increase the number of potential transmitters, but this slows synchronization and creates power imbalance of the multiplexing transmitters.

In one type of code division multiplexer a plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signal transmitted by a 2redetermined transmitter fram signals transmitted by the others by cross-correlating the inconing signal with a trinary sequence that is developed at the receiver.

The receiver develops the trinary sequence by generating a first pseudo-random code that is a replica of the common bipolar pseudo-random ccde transmitted by the transmitters and having a code sequence shift corresponding tc that of the predetermined transmitter to which the receiver is tuned, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift.

Correlation consists of multiplication of an incoming signal with the local reference signal that corresponds to the difference bet~een the fir,t and second bipola. pseudo-random code sequences. Integration of the product averages out random noise to enhance the signal-to-noise ratio. When the information transnitted is binary, t~o different waveforms are generated: one for a ~zero" and another for a "one" at the receiver. When tne ~x~ -- 5 - transmitted signal is biphase, the transmitted waveforms for a "one" and a "zero" differ from each other by a 180 phase shift.

When the predetermined transmitter and the receiver are synchronized with each other, the multiplier output is at a maximum at a positive polarity for a "one" and a negative polarity for a 'zeron.

The multiplier output is integrated fot the duration of l-bit period.

Ir the initial integrator output is "zero" then the polarity of the integrator output at the end of a bit period c~rresponds to the transmitted binary information.

The degree of correlation between the predetermined transmitter and the receiver is determined by comparing the outputs of several correlation detectors having reference signals that are displaced in time with each other.

Each detector develops two output signals, an in-phase signal that is at a maximum and a quadrature-phase signal that is at a minimum when the receiver and peedetermined transmitter are aligned.

The receiver is fine tuned to the predetermined transmitter by adjusting the receiver timing until the quadrature-phase signal is minimized.

During Eine tuning of the receiver, a decision is made on - each incoming sequence bit whether to advance or retard receiver timing by an equal fraction of a code chip.

The receiver timing is advanced by the code chip fraction if the in-phase and auadrature-phase correlation signals are of opposite polarity.

If the in-phase and quadrature-phase correlation signals are of the same polarity, the receiver timing is retarded.

During perfect correlation between the receiver and predetermined transmitter, however, the fine tuning mechanism of the receiver tends to drive the receiver tLming from the optimum reception point, causing the receiver to continually search for correct synchronization, since thsre is no deadband.

Further, because there is a delay innerent in the feedback loop of the receiver, the correction decision is made using information ~ore than one data bit old, causing the receiver to tend to overshoot as it attempts to lock in the optimum synchronization point.

As another problem, a direct sequence spread spectrum receiver does not readily distinguish between a signal and noise, particularly since the incoming signal is a data modulated carrier that is spread by a pseudo-noise sequence.

The receiver will thus tend to attempt to lock onto noise in the absence of a signal.

Disclosuee of Invention It is accordingly one object of the invention to improve synchronizatlon in a direct sequence spread spectrum receiver.

A further object is to improve receiver synchronization in a direct sequence spread spectrum receiver of a type using multiple correlation detectors displaced from each other by an equal fraction of a code chip, to identify optimal synchronization delays.

Another object is to distinguish between an incoming signal and noise in a direct sequence spread spectrum receiver.

m ese and other objects are satisfied by the method and system of the present invention which improve the synchronization between a transmitter and a receiver used in a direct sequence spread spectrum code division multiplex system, and in particular where a plurality of transmitters and at least one receiver are synchronized to a common timing signal source.

Each transmitter transmits a data signal spread by a bipolar pseudo-random code which is a different assigned shift of a common bipolar code sequence.

The receiver comprises a plurality of correlation detectors, each generating two local bipolar pseudo-random codes that are replicas of the transmitted common bipolar pseudo-random code.

One of the locally generated codes has the same code sequence shift as the code sequence shift assigned to the predetermined transmitter. m e other locally generated code has a code sequence shift tnat is not assigned to any of the transmitters. m e two locally generated codes are processed to obtain a trinary code sequence that is cross-correlated with the incoming signals to discriminate and extract information frcn the signal transmitted by the predetermined transmitter.

The cross-correlation develops an in-phase signal that is at a maximum and a quadrature-phase signal that is at a minimum ~hen the receiver and predetermined tran3mitter are aligned.

Synchronization is provided by adjusting receiver timing to minimize the quadrature-phase cross-correlation signal.

In accordance with one aspect of the invention, the ratio of the in-phase and quadrature-phase signals is measured and processed to control size of the receiver timing shifts to obtain a perfect s~nchronization without stepping through intermediate receiver timing shifts.

The receiver is presumed perfectly synchronized if the ratio is greater than a predetermined number, thereby establishing a deadband and reducing synchronization overshoot.

In accordance with anotber aspect of the invention, tne ratio of the in-phase and quadrature-phase correlation signal magnitudes at one of the correlation detectors is measured to identify a signal in the presence of noise.

If the absolute value o the ratio is much greater than one, a signal will be presumed present;

otherwise, the receiver will be presumed to be receiving noise.

m e receiver is controlled to attempt to synchronize to an incoming signal only if the measured ratio is greater than a predetermined value.

Still other objects and advantages of the present invention will become readily apparent to those skilled in this art fron the following detailed description, wherein there is shown and described only the preferred embodiment of the invention, simply by way of illustration of the best modes contemplated of carrying out the invention.

As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modification in various, obvious respects, all without departing from the invention.

Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

~ 7 ~C)~2 _ 9 _ Brief oescrietion of the Drawings Fisure 1 is a simplified block diagram showing a OSSS code division multiplex receiver;

Figure 2 is a representation of a bipolar pseudo-random pulse sequence;

Figure 3 is a diagr~m showing an autocorrelation pattern for a bipolar pseudo-{andom pulse se~uence of the type shown in Figure 2;

Figure 4 is a superposition of several autocorrelation patterns corresponding to neighboring transmitters in a code division multiplex system;

Figure 5 is a diagram corresponding to Figure 4, with signals of neigh~oring transmitters separated by guard bands;

Figures 6~a)-6(d) are wave for~s showing trinary code lS generation;

Figure 7 is a simDlified block diagram showing a receiver op~rated in accordance with the principles of the invention;

Figure 8 is a diagram showing an idealized cross-correlation pattern between a locally developed trinary code sequence and an incoming binary code sequence in accordance with the invention Figures 9(a)-9(c) æ e diagrams showing correlation patterns developed by multiple channel correlation detectors in accordance with various em~odiments of the invention;

Figure 10 illustrates an actual correlation pattern obtained 2S in the receiver of the present invention when operated in the presence of various degrading factors;

Figure 11 illustrates an analog embodiment of multiple correlation detectors for determining the degree of correlation in accordance with the invention;

Figure 12 is a circuit simplification of the analog embodiment of Figure 11 using binary reference signals;

Figure 13 is a further circuit simplification of the analog circuit of Figure 11, using digital logic to reduce the number of analog multiplexers;

s - L0 Figures 14(a) and 14(b) illustrate two methods of implementing the circuit of Figure 13;

Figure 15 is a digital implementation of one channel of the circuit shown in Figure 11;

Figure 16 is an N-channel generalization of the circuit implementation in Figure 15;

Figure 17 sh~ws another digital ~mplementation of a single channel correlator of a type shown in Figure 11;

Figure 18 i9 an N-channel generalization of ~he circuit shown in Figure 17;

Figure 19 illustrates an in-phase and quadrature-phase correlation pattern, together with the locations of sub-receiver channels for correlation detection;

Figure 20(a) and 20(b~ are flow charts shcwing two alternative methods for performing fine tuning of the receiver;

Figure 21 illustrates a microprocessor based circuit for performing fine tuning of the receiver and signal presence detection;

Figures 22(a) and 22(b) are flow charts respectively showing methods for correcting receiver timing and for performing signal presence detection;

Figure 23 is a flow chart showing one technique for performing coarse tuning of the receiver;

Figure 24(a) - 24(e) are timing diagrans showing the relationship of timing pulses between a transmitter and a receiver;

Figure 25 illustrates a circuit for loc~ing a transmitter and receiver to the same timing pulses; and Figure 26 illustrates a microprocessor based circuit for performing da~a recovery in the receiver.

3est Mode for Practicinq the Invention General In spreaa spectr~m communications, spreading of signal bandwidth beyond the bar.dwi~th normally required for data being - 1.1.

transmitted is acccmplished by first phase shift keyed (PSK) modulating a carrier waveform by data to be transmitted, and then modulating the resultant signal by a reference pseudo-random code of length L running at a re~etltion rate which is nonmally at least twice the data rate.

Forms of modulation other than PSR can be aFplied to modulate the carrier as well as to spread the composite signal, although PSR is preferred for reasons set forth earlier.

To demodulate the signal transmission, the received signal is heterodyned or multiplied by the same reference code as the one used to spread the composite transmission, and assuming that the transmitted and locally generated receiver codes are synchronous, the carrier inversions caused by the code PS~ modulation at the transmitter are removed and tne original base-band modulated carrier is restored in tne receiver.

Figure 1 illustrates the fundamental elements o~ a basic spread spectrum receiver incorporating one aspect of the invention~ Receiver 100 receives a direct sequence spread spectrum (DSSS) signal transmitted by a particular transmitter among a plurality of such transmitters, and processes the received sign 1 to discrLminate the signal transmitted by the particular transmitter from among the signals transmitted by all the transmitters. 3earing in mind that the received signal is essentially mcdulated twice, that is, the carrier is modulated with data and then the composite is modulated by a pseudo-random code se~uence to spread the composite over a bandwidth that is comparable to the bandwidth of the pseudo-random sequence, receiver 100 provides two stages of demodulation of the received signal to extract the trans~ission data.

The received DSSS signal is first heterodyned or multi~lied by the code of the particular transmitter whose signal is being discriminated from a~ong the others.

Thus, assuming that the codes generated at the transmitter and receiver are synchronous, the sarrier inversions saused oy the code ~SK modulation at the transmitter are removed o5 - 12 at multiplier 102, and the original base-band modulated carrier i5 restored. ~he narrow-band restored carrier is applied to a band pass filter (not shown) designed to pass only the base-oand modulated carrier. 3ase-band data are then extracted by heterodyning or multiplying the restored carrier by a locally generated carrier at multiplier 104.

The output of multiplier lQ4 is applied to a conventional correlation filter 106, such a_ an integrate and dump circuit, followed by a sample and hold circuit which develops signals corresponding to the transmitted data.

m e receiYer 100 is controlled by a standard microprocessor 108, synchroni2ed to a system clock llO, to which the transmitter~ are also synchronized.

Because noise and undesired transmissions are treated in the same process of multiplication m multiplier 102 by the locally ge~erated reerence code that conpresses the received direct sequence signal into tne original carrier bandwidth, any incoming signal not synchronous with the locally generated reference code is spread m to a bandwidth equal to the sum of the bandwidth of the incoming signal and the band~idth of the reference code.

Since this unsynchronized input signal is mapped into a bandwidth that is at least as wide as the reference code, a band pass filter can reject a significant amount of the power of an undesired signal.

This is the significance of a DSSS system: synchronous input signals at the reference code ~odulated bandwidth are transformed to the base-band modulated bandwidth, whereas non~ynchronous input signals remain spread over the code-modulated bandwidth.

Synchronization processing makes use of a property inherent in the particular code that is employed at the transmi~ter.

The autocorrelation of a maximal length (ML) sequence, that is, multiplication of the sequence by a time shifted replica of itself, is at a peak when synchronization i5 achieved and has an absolute value that drops to -P /L, where P is the magnitude of the code sequence and L is the c~de length, as synchronization becomes lost (i.e., ~he time difference ~etween the code and its ~ ~3,~ - 13 replica approaches a code chip or greater).

The sign of the autocorrelation pattern is dependent upon the data bit being used to modulate the t ansmitter.

It is thus possible to recover the transmitted data at the receiver by monitoring the sign of the autocorrelation out2ut when the receiver and transmitter are properly synchronized.

Referring to Figure 2, a pseudo random code sequence of a type to which receiver 100 is tuned is bipolar, that i~, it is assumed to switch polarities of a constant voltage power supply.

In the invention, bipolar, rather than unipolar, sequences are used to improve pcwer transmission efficiency, since the carrier is suppressed in bipolar transmission. 8ipolar transmission also avoids high con oe ntrations of energy in any frequency band to help avoid interference between transmissions by different transmitters in the system.

Each bipolzr sequence has a magnitude P and a chip duration Tc.

The length of the ~L sequence depends upon the nu~ber of different transmitters whose signals are to be code-division multiplexed within the system.

Each transmitter is assigned the same transmission code having a different specified chip of the common ML sequence.

The maximum number of transmitters that are capable of being multiplexed within this system thus corresponds to the length of the ML sequence.

The number of transmitters that may be multiplexed without interference within a code-division multiplex system of this type is equal, theoretically, to the bit length of the sequence.

For an ML code having a length of 63 bits, for example, the transmission channel is theoretically capable of multiplexin~ 63 different transmitters.

This assu~es that synchronization is deemed to be achieved between the receiver and a preselected transmitter when the autocorrelation between the code received from the transmitter and the locally generated code, ~oth synchronized to a cs~mon timing source, is at a peak.

In practice, however, the number of transmitters that can be code division multiplexed in the system is much lower than the - 14 theoretical maximum, because there is overlap between neighboring correlation curves due to the -P /L term in the autocorrelation of the ~L sequence. miS can be better appreciated with reference to Figure 3 which shows a correlation curve for a single transmission and Figure 4 which shows a number of correlation curves for neighboring transmissions, tha~ is, for transmissions that are time offset from each other by a single code chip.

In Figure 3, the correlation curve has a magnitude _p2/~ when the transmitted and locally genesated code sequences are time ~0 offset from each other by greater than a code chip Tc, where P is the ab~olute magnitude of the sequence and L is the ~e~uence length in bits.

When the transmitted and locally generated codes are near synchronization, that is, are within a time offset of one code chip of each other, the correlation increases in magnitude to a peak of p2 at perfect synchronization.

Thus, synchroniz~tion between the receiver and a single transmitter can be detected by mcnitorinq the correlation output and deeming synchronization to exist when the correlation signal is above a 2redetermined positive value.

Referring now, however, .o Figure 4, assume that there are three transmitted code sequences k, k-l and k~l, time shifted from each other by a single code chip.

Each correlation has a ositive peak value of P and a negative peak value of -P /L, as in Figure 3.

The correlation curves of neighboring code sequences overlap, within the regions shown by cross-hatching in Figure 4.

In those regions, neighboring code sequences have common correlations, making it impossible to distinguish between transmissions.

As a practical matter, to avoid interference between transmissions, it is necessary to insert a guard band between sequences, as shown in Figure 5.

This is provided by assigning transmissions to sequence shifts corresponding only to alternate code chip delays, rather than to every code chip delay ~s in Figure 4.

The result is that, at best, only one-half the number of transmissions, compared to the theoreticaL maximum - 15 number, can be multiplexed.

In practice, even fewer than cne-half the theoretical maxlmum transmitters are capable of being multiplexed in a code division multiplex system using bipolar sequen oe s because a guard band that is greater than that provided using only alternate code shift delays is required to avoid synchronization ambiguities.

In accordance with one aspect of the invention, the number of transmitters that are capable of being ;nulti~lexed is increased to one less th~n the theoretical limit oy cross-correlating the input 19 signal with a trinary code developed by obtaining the difference between the code sequence assigned to the particular transmitter to which the receiver is tuned and a code se~uence that is unassigned.

In other words, two bipolar code sequences are developed at the receiver.

Cne of the codes is the replica of the com~on code sequence transmitted by all the transmitters and has a sequence shift that corresponds to the sequence shift of a predetermined cne of the tran~nitters.

The second c æ e is a replica of ~he common bipolar sequence and has a code sequence shift that is not assigned to any of the transmitters.

One of the locally generated codes is subtracted from the other, and the resultant, which is a trinary code sequence, is correl~ted with the incoming signals.

The sequence shift of the trinary code sequence is brought to within one code chip of the sequence generated by the preselected transmitter, using a static synchronization technique to be described below.

Perfect synchronizatisn between the receiver and preselected transmitter is obtained using dynamic synchronization, also to be described ln detail belcw, obtained generally by successively shifting the timing o~ the receiver by a fraction of a code chip and monitoring the output of the correlator. W~en tne correlation output is at a peak, the receiver and preselected .ransmit~er are considered to ~e synchronized to each other.

Assuming now tha~ the receiver and transmitter are also synchronized to corresponding clock Dulses (i.e., the transnitter is not synchronized to one clock pulse and t~e receiver synchronized to another), the polarity of the c~rrelation output is nitored to extract the transmitted da~a.

'7'~:~5 - 16 DeveloFment of the trinary pulse sequence to be cross-correlated with the transmitted sequences is ~etter understood with referen oe to Figures 6(a)-6(d).

In Figure 6(a), a transmitted bipolar sequence s(t) having an absolute magnitude P and chip period Tc is shown. m is sequence is a simplification of an actual seqyence which, in practice, would be substantially longer, e.g., 63 bits. ~ithin the receiver is develo~ed a first reference pulse sequence r(t~ shown in Figure 6(b). m e sequence r(t) is identical to the sequence s(t) transmitted by the predetermined transmitter shcwn in Figure 6(a), because tne transmltter and receiver sequences have the same delay and are presumed synchronized to each otner.

The receiver generates a second reference eulse sequence e(t), shown in Figure 6(c), which is the same s~quence as the one transmitted by the preselected transmitter as well as by all the ~ther transmitters but has a sequence delay that is not assigned to any of the transmitters.

The difference [r(t) - e(t)l between the ~wo locally generated reference pulse sequences is obtained, to provide the trinary pulse sequence shcwn in Figure 6(d).

The trinary sequence has a value [+2, 0, -2], depending upon the relative binary values of ~he two reference pulse sequences r(t) and e(t).

It is to be understood that the sequence length in the ex~,~le shown in Figure 6 is 7 bits, although in practicet much longer sequences would be applied to accommodate a relatively large num~er of transmitters to be code division multiplexed.

~eferring to Figure 7, development of the trinary reference sequen oe to be cross-correlated with incoming bipolar pulse sequ~nces for signal demultiplexing is provided in a receiver 200. m e receiver 200 receives the transmitted pulse sequences s(t) and applles the incoming sequences to the inputs of a first correlation multiplier 202 and a second correlation multiplier 204.

The first correlation multiplier 202 multiplies the incoming sequences s(t) by the locally generated reference pulse sequence - 17 r(t) having a sequence shift corresponding to the sequence shift of the preselected transmitter.

The multiplier 204 multiplies the incoming sequ~nces s(t) by the pulse sequence e(t) having an unassigned pulse sequence shift.

The resultant multiplication products are applied to a difference circuit 206, and the difference is integrated and sampled in a standard correlation filter 208 to develop an output signal Yout.

~t is pointed out that in Figure 7, the input sequences s(t) are first multiplied ~espectively by the two reference puLse sequences r~t) and e(t), and then the product difference is obtained in difference circuit 206.

This is equivalent to obtaining the difference between the two reference pulse sequences r(t) and e(t) and then multiplying the difference by the incoming sequences s(t).

The resultant cross-correlation is shown in Figure 8.

Note that each correlation curve has a value 0 when the preselected transmission and locally generated reference sequence r(t)-e(t) are displaced from each other by more than one code chip.

This contrasts with the cross-correlation curve of Figure 3, wnerein there is a negative residual correlation having a magnitude P /L.

The magnitude of the correlation curve increases linearly to a 2eak v~lue of P(L+l)/L when the preselected transmitted and locally generated reference pulse sequences are synchronized.

The advantage of this correlation strategy is appreciated by camparing Figure 9a showing the correlations of a number of neighboring transmission~s in accordance with the invention and Figure 4.

In particular, Fig. 9a shows codes with a separa~ion of 2 code chips.

However, it will be appreciated that the Figure 9a transmissions can be displaced from each other by a single code shift and that there is no overlap between the correlations of adjacent transmissions, whereas in Figure 4, overlap occurs in the cross-hatched portions.

The invention thus enables the number of transmissions capable of ~eing multiplexed to ~e equal ~o one less than the length of the pulse sequence in bits, a result that is - 18 not possible using prior art syste.~s.

Even if a guard band is plac~d bet~een transmissions in tne strategy shown in Figure 3a, the numGer of transmissions that can be reliably multiplexed ls substantially greater than the number that can be reliably multiplexed using the correlation strategy shown in Figure 4.

AssumR that the code-division multiplexed PSK signal Y(t) incoming at the receiver is expressed as follows:

Y(t) = ~ PjdiXj(t)Cos(~ct ~ 0) + N(t) ~1) where for J inccming transmissions:

0 5 t 5 T, wnere T is a code chip period;

P. is the power within each incoming bipolar pulse sequence;

d~ is the polarity or sign of each corresponding inc~ming sequence;

lS Xj(t) is the transmitted data;

Wc is tne frequency of tne carrier in radians, O is the carrier phase; and N(t) is noise.

The ou~put V~(T) of ~he conventional receiver, using a single referense code sequence, is defined by the following:

1 N VA(T) = Prdr + ~ ~ Pjdj + NA (2) j~r where:

Pr is the pawer of the desired incoming sequence;

dr is the data sign of the desired sequence;

L is the pulse se~uence length in bits;

P. is the power of each of the undesired sequences;

d is the corresponding data sign of the undesired sequence; and NA is noise.

The output VB(T) of the receiver operating in accordance with the prLnciples of the invention is defined as follows:

~JB(T~ - Prdr (1 + l/L) + ~ (3) ~_r~ - 19 Because the correlation method of the invention involves a subtraction of a code sequence having an unassigned code sequence shift, all undesired transmission cGmponents (identified by the subscript "rn) in the output VB(T) are perfectly rejected, whereas in the prior art receiver, the output VA(T) involves contributions of the undesired transmissions (having the su~script c well as the desired transmlssions tsubscript "r").

Multiplexer trinary sign 1 correlation induces an additional three decibels of degradation in data signal-to-noise demodulation with res~ect to white noise appearing at the receiver input, compared to conventional correlation using only the particular transmission binary pulse seguence.

Thus, NA = ~ = (4) Nb = 2(1+1/~) NA The multiplexing strategy discussed above results in perfect unwanted access rejection capability using ~L codes of any length in a code-division multiplex system.

In the past, only ML codes of sufficiently long length ~ere potentially usable with the number of allowable multiplexers being much less than the code length.

Even there, power imbalances of the multiplexing transmitters occurred.

Additionally, the ideal cross correlation ~attern in Fig. 9a lends itself to mul~iplexing schemes using more than the theoretical limit of code, each time-offset by less than a code chip, and ?~suming a more complex receiver configuration.

For example, it has been discovered that the number of transmitters whicn could be multiplexed can be increased to 2 x (L-2) channels by adding a ccde between each of the code sequences shown in Fig.

4, ~ith only a slight trade off in overall receiver signal-to noise perfor~ance.

As shown in Fig. 9b an additional code can be inserted between each of the codes shown in Fig. 4.

The codes are detected at a plurality of taps ~rovided at the receiver.

The out?uts of the Yarious receiver taps shown in Fig.

9b are as ~ollows:

s - 20 T~BLE I 1. extra code 2. 1/2 extra code 3. null 4. 1/2 code 1 5. code 1 ~ 1/2 code 1' 6. 1/2 code 1 + code 1' + 1/2 code 2 7. 1/2 code 1' + code 2 + 1/2 code 2' The sequence of equations may then ~e solved for each channel:

channel 1 = 2 x tap 4 channel 1' = 2 x (tap 5 - channel 1) channel 2 = 2 x (tap 7 - channel 1' - tap 4) channel 2' = 2 x (tap 7 - channel 2 - tap 5) n 1~ ~l cnannel L' = 2 x tap(2L + 3) In practice, the above arrangement would be somewhat difficl~lt to implement due to both noise and synchronization problems.

An alternative implementation would require that a null of the carriers occurred at the point where the correlation envelope is equal to 1/2 the maximum.

In such an arrangement, the equations for the outputs of the ~aps beccme: TABLE II 1. extra code 2. null 3. null 4. null 5. code 1 6. code 1' 7. code 2 This arrangement allows for full da~a recovery without interference.

However, it may s~ill be samewhat susceptible to noise.

- 21 - ~2~ S In order to overcame the above problems, there is shown in Fig. 9c an arr~ngement in which two or more code sequences are grouped together and separated by guard-bands.

The exact separation of the groups or the patterns comprising the groups is independent of this arrangement.

This approach also allows the grouping of transmitters with similar characteristics and simplifies synchronization problems.

Any additional modulation by data bearing signals and that necessary for improved communication between transmitters and receivers can be incorporated in the above described strategies.

m e only condition require~ is that any additional mcdulation must not destroy ~he necessary timing of the shifted ~ulse sequences thereby maintaining receiver multiplexing sensitivity.

lS Svnchronization - General The receiver and preselected transmitter must be time synchronized to each other before data can be extracted.

Assuming tha~ the receiver and transmitter are synchronized ~o a common timing source (if the ccmmercial power line is the transmission medium, common timing can be obtained from the 60 Hertz power source)~ synchronization is a matter of adapting receiver timing to different propagation delays of the transmitted signal as well as to the timing signal and to delays inherent in the transmitter and receiver.

Scme of these delays are fixed, and can be compensated using a "static~ delay, to synchronize the receiver and predetermined transmitter to within one code chip of each other, wherein a chip is defined as the bit period of the pseudo-random code generator.

In general, static delay can be compensated during initial calibration of the receiver, since most static delays are fixed.

A difficulty occurs, hcwever, when the transmlssion medium is a transmission line with the transmitter and receiver synchronized to a common timing source, and wherein communication between the t~ units is bidirectional.

Static delay mus~ thus be examined - 22 from two reference points, one where the transmitter is at the timing source and the other where the receiver is at the timing source.

With the transmitter located at the timing source and the receiver located elsewhere, the t~ming signal and transmitted signal will propagate at approximately the same speed from the transmitter to the receiver.

Other timin~ variations between the transmitter and recelver are due to delays induced within the transmitter and receiver circuitry, and can be preset to synchronize the transmitter and receiver to within one code chip of each other.

All receivers remote from the tim mg source can thus have identic l static delays~ If the receiver is located at the timing source and the transmitter is located elsewhere, however, each receiver may require a static delay that is unique for each remote transmitter to account for different signal propagation distances.

Thus, to er.able a receiver to receive signals from a multiplicity of transmitters, the static delay of tne receiver must be variable.

In practice, the static delay between each transmitter and the receiver is measured upon installation of the transmitter; that static delay value for all future communications with a particular transmitter is preset within the receiver.

Whenever a transmission is received from that transmitter, to obtain united synchronization of the transmitter, receiver timing is automatically adjusted to accommodate tne delay associated with the particular transmitter.

In one e~bodiment of the invention, there are a plurality of transmitter/receiver units disposed in a so-called "master/slave" arrangement~ In this arrangement, one transmitter/receiver unit, called the master station, acts as the source of tlming signals for the other stations (slave units).

The amount of dela~ associated with the timing si~nals between the master station and e æ h of the slave stations includes such things as the filter delay for the timing signal source at the master station, the ~ ~ ~ 7~;3 - 23 received filter delay at the master station, the signal propagation delay between the master and a particular slave, the coupling delay at the master station and t`ne transmit filter delay at the master station.

Knowledge of these various delays will give an estimate of the amount of static delay associated between the master station and a particular slave station. ~owever, some variation in each delay will occur with changes in the transmission line associated with temperature changes, transmlssion frequency, etc.

While dynamic delay adjusbments can take care of mos~ o~ these changes in the static delay characteristics between the master and slave units, the multiplexing capabilities of the system may be somewhat reduced because the receiver at a particular master or slave unit must be capable of tracking delay variations over a range of several code chips.

This requires a guard band that is wide enough to allow the signals of two adjacent receivers to vary in time over their associated bands without interference.

However, it has been discovered that the amount of required guard band may be r~duced by periodically measuring, at the master station, the static delays associated with signal transmission between the ~aster station and each of the slave stations and then periodicaily adjusting the transmitter signal timing at the slave in order to bring the static delay back into a desired r.~nge.

This allows more slave stations to transmit at one time since the guard band required for delay variations can be greatly reduced thus allowing more usable code delays for multiplexing.

Variations frcn synchronization established by the static delay are compensated by a dynamic delay mechanism within each receiver.

The dynamic delay consists of two stages: fine tuning and coarse tuning. ~hereas static delay timing causes the receiver and predetermined transmitter to be synchronized to each other to within one code chip, fine tuning uses correlation detection to make fine adjustments in receiver timing as a - 24 ~ Q~ function of received transmission, rather than as a function of an expected transmission (static delay).

After fine tuning has established that receiver timing is at a local correlation peak, it becomes necessary to determine if the local peak to which the receiver is timed is the "correct" lccal peak for best correlation.

This is necessary because, depending upon the correlation properties of the code selected, as well as other factors, there are likely to be multiple correlation peaks, with the primary local peaks having the greatest peak magnitude.

These multiple peaks arise from carrier correlation within the ~lTC code correlation peak.

Finally, it must be determined which of the system timing pulses present in each data bit is the proper one for synchronization.

Without such a deter~ination, a condition can exist wherein the transmitter is locked to one lS timing pulse while thè receiver is locked to another timing pulse. m is is because these are two timing pulses in a data period and incorrect timing causes a quadrature condition between transmitter and receiver data periods.

Thus, the net energy for such quadrature data periods is zero.

Even with the receiver and transmitter properly synchronized to each other, data cannot be extracted from the received sequence because it is not possible to detect and decode the data transmission unless the receiver and transmitter are locked to the same timing pulses.

Fine tuning and coarse tuning as well as synchronization to the proper timing pulse within each data bit shall now be described in more detail.

Figure 10 illustrates the correlation pattern obtained by cross-correlating an incoming, bi-polar pulse sequence together with its carrier and the locally generated trinary reference sequence. m e correlation pattern has a major peak at receiver timing Vl and has minor correlation peaks at receiver timings V2, V3, V6 and V7, referred to hereinafter as "channels".

The correlation peak at primary channel Vl depends upon the correlation properties of the code selected as a function of code chip time delay difference between the incoming code sequence and - 25 the reference code sequence.

The correlation is at a peak ~hen synchronization between the receiver and transmitter is achieved, with the absolute value of the correlation dropping to zero as the synchronization difference approaches a code chip or greater.

It should be noted that, due to imperfect correlation properties of the code and due to the influence on correlation by the sinusoidal carrier, the correlation shown in Figure 10 is approximately sinusoidal as c3npared to the piece-wise linear, ideal correla~ion profile sho~n in Fiqure 9a which does not include a carrier. ~his 0 i5 the reason that coarse tuning is required; fine tuning adjusts receiver tim m g until a correlation peak is determined; coarse tuning then determlnes whether the correlation peak is the major correlation peak associated with channel Vl or iq a minor correlation peak associated with channels V2, V3, V6 or V7, or others.

In accordance with one aspect of the invention, synchronization of the receiver is achieved by providing a plurality of separate sub-receivers or correlation detectors ~hat are tuned to each receiver channel.

Assuming that each of the channels Vl, V2, V3, V6 and V7 are spaced apar~ from each other in time by one third of a code chip, fine tuning adjusts the receiver timing such that the channels are all located at local peaks.

Furthermore, assuming that channel Vl is ~ithin a code chip of being synchronized, the channel Vl is within one sixth of a code chip of a local peak.

The outputs of the correlation de~ectors are applied to a microprocessor 314, described below, to develop a receiver timing signal for synchronization to the transmitter and to extract transmission data.

Various em~odiments of the multiple correlation detectors are illustrated in Figures 11-18.

Correlation 0etection One embodiment of the multiple channel correlation detector shown in Figure 11 is generalized for N correlation channels.

The multiple channel correlation circuit identified generally by 300 ~ ~ ~'7 - 26 comprises for each channel 2 correlator 302 each comprising a first multiplier 304, a qecond multiplier 306 and a difference circuit 308.

The first mult}plier 304 has one input that receives the incoming æ quences s(t) and a second input that receives the first lccally generated reference sequence r(t) having a sequence shift that corresponds to the sequence shift of a predetermined transmitter.

The multiplier 306 has one input that receives incoming sequences s(t) and a second m put that receives the second ceference se~uence e(t) having an unassigned s~uence shift.

The outputs of the two multipliers 304 and 306 representin~, respectively, the products of ~he incoming sequences and the two locally generated reference sequences are applied to the inputs of differen oe circuit 308.

The difference output is applied to an integrate and dump type filter 310, matched to the period of a bit at the chip rate, to develop a signal VN for each channel as follows:

VN = S S(t)[r(tN) - e(t~)]dt (5) o wherein VN and s(t) are analog signals while r(tN) and ettN) are binary signals.

The output of the integrate and dump circuit 310 is applied to a sample and hold circuit 312 which monitors and stores the magnitude and polarity of the integrator output VN.

This value if applied to a conventional microprocessor 314 that in 2S response to outputs from all N of the detectors 302 extracts the binary data from the predetermined transmission and develops a timing error signal to retain ~he receiver locked in svn^hronism with the predetermined transmitter, as discussed in more detail below.

~he analog multiple channel correlation detector shown in Figure 11 requires a subs~antial number of calibration adjustments associated with the multipliers 304, 3Q6, the difference circuits 308, the integrate and dump circuits 310 and the sample and hold circuits 312.

In practice, an 8-channel detector of this type requires approxlmately 80 calibration adjustments.

~2~ - 27 If only the polarity of the reference s~quences r(t) and e(t) is used, considerable simplification of the system results, with only a sllght degradation in performance.

Because the two referen oe sequen oe s are binary (bi-polar) signals, multiplication can be achieved in an N channel correlator usins 2N two-input analog multiplexPrs and one inverter, shown in Figure 12.

In this implementation, the binary referenc~ signal determines whether the input signal s(t) o~ an inverted input si~nal s(t) is selected to be applied to subtraction circuit 308.

Bearing in mind that the desired output of each of the N difference circuits 308 is s(tN)[r(tN) - e(~N)], each channel in the correlation detector 400 shown in Figure 12 ccmprises a first two-input multiplexer 402 and a second two-input muLtipLexer 404 controlled, respectively, by the instantaneous polarities of the first and second bi-polar reference ~equences r(tN) and e(tN).

One input of each of the two multiplexers 402, 404 is connected to a first line 406 that receives the incoming sequences s(t) and a second input connected to a line 408.

The line 408 receives the incoming sequences s(t) inverted in polarity by an inverter 410.

The multiplexers 402 and 404 are driven by the reference sequences r(tN) and e~tN) through drivers 412 and 414.

Assuming that the polarities of r(tN) and e(tN) are identical, both of the multiplexers 402 and 404 are connected to the line 406.

Ihe input sequence s(t) is thus appLied to both the positive and negative input terminals of the difference circuit 308 whereby a zero signal is applied to integrate and dump circuit 310 (Fig. 11).

If r(~) is positive and e(t~) is negative, multiplexer 402 is connected to line 406 and multiplexer 404 is connected to line 408.

The sequence s(t) is thus applied to the positive input of difference circuit 308 and the inverted sequence s(t) is applied to the negative input terminal of circuit 308; the sequence 2s(t) is thus applied to integrate and dump circuit 310.

If, on the other hand, the relative polarities of the two reference sequences are reversed, the sequence s(t) is applied to - 28 ~ the negative input of difference circuit 308 and the inverted input sequence s(t) is applied to the positive ineut of difference circuit 308. The signal -2s(t) is thus applied to integrate and dump circuit 310, thereby satisfying the equa~ion S VN(t) ~ s(tN) [r(tN) e(tN) ] The circuit of Figure 12 is advantageous over the circuit of Figure 11 because analog multiplier calibration adjustments are not required in Figure 12, although the inverter 410 requires two (balance and of~set) calibration adjustments.

The number of adjustments required for an eight-channel detector is thus reduced fr~m approximately 80 to 34.

Referring to Figure 13, a further simplification of the circuit shown in Figure 11 can be achieved by recognizing that the input to each integrate and dump circuit 310 is the difference between two signals, each of which is the input sequence s(t) multiplied by a +l or a -l, with the output being zero when the two reference sequences are equal to each other.

In accordance with Figure 13, the 2N multipliers and the N subtractors are repLaced, in circuit 500, by N three-input analog multiplexers 502.

One input of each of the multiplexers 502 is connected to a line 504 which receives the input sequence s(t). A second input of multiplexer 502 is connected to a line 506 which receives an inversion s(t) of the input sequence, inverted by 508.

The third input of multiplexer ;02 is connected to a line 510 that in turn is connected to ground.

The first reference sequence r~tn) is connected direc~ly to the control input of multiplexer 502 through ~n inverter/driver 512.

Also connected to the control input of multiplexer 502 is an exclusive-CR circuit 514 having inputs connected re~pectively to the two reference sequences r(tn) and e(tn).

When the two refe~ence sequences are equal to eacn other, ~he output of the exclusive-OR circuit 514 drives the multiplexer to line 510, causing the output of multlplexer 502 to generate a zero signal to integrate/dump circuit 310 (Fig. lL). I~ the first - 29 - '~Z~ 5 eferen oe r(tn) equals 1, the output v(t) of multlplexer 502 equals s(t).

If r(t) equals 0, on the other hand, the multiplexer output v(t) equals -s(t).

The output of the difference circuit thus generates the signal s(tn) k (tn) - e(tn)~ and the integrate and dump output for each channel is S s(t)[r(tn) - e(tn)~dt, as required. (6) o Two circuits for implementing the three-input analog multiplexer 502 of Fisure 13 are shown respectively in Figures 14a and 14b.

In Figure 14a, each of the ~o two-input multiplexers 600, 602 have the follcwing characteristics:

x - x0, when A = 0;

x = xl, when A = 1.

lS The first reference sequence r(t) is connected to control terminal A of multiplexer 600 and to one input of an exclusive-OR circuit 604.

The second reference sequence e(t) is connected to a second input of exclusive-OR circuit 604.

The output of the exclusive-OR 604 is connected to the control terminal A of multiplexer 602.

m e incoming sequences s(t) are connected to one input terminal xl of multiplexer 600, and, through an inverter 606, to the second input x0 of the same multiplexer.

The output x of multiplexer 600 is applied to one input xl of multiplexer 602;

the second input x0 of multiplexer 602 is connected to ground.

The output v(t) of the multiplexer shown in Figure 14a is defined by the following truth table, which corresponds to the required equation v(t) - s(t)[r(tn) - e(tn)].

I~BLE III r(t) e(t) r ~3 e v ~t) 0 0 0 0 0 1 1 -s (~) 1 0 1 s(t) 0 0 _ 30 _ ~2~ In the embodiment of the three-input multiplexer 606 shown in Figure 14b, the output x is connected selectively to any one o the four inputs xO, xl, x2, X3, depending upon the binary values of control inputs A, 8.

The input sequences s(t) are S connected directly to input x2 and through an inverter 6~8 to input xl~ Inputs xO and X3 are connected to ground. m e two reference sequences e(t) and r(t) are connected respectively to control inputs A and B of multiplexer 606.

m e operation of multiplexer 606 is described by the truth table set forth above with respect to Pigure 14a and also provides the desired output v(t).

The correlation detector embodiments of Figures 11-14 are based upon the analog technique of integrating a continuous signal.

The number of calibration adjustments required can be reduced further by replacing analog integration in the correlation detector by discrete signal summation.

Referring to Figure 1;, correlation detector 700, provided in each channel of the reseiver, digitizes the incoming sequences s(t) and algebraically sums the digitized signal in an accumulator over a period of time equal to a bit period.

The difference between the initial and final values in the accumulator represents the value of s(t) integrated over a bit period.

Accum~llation is controlled by the values of the reference sequences r(t) and e(t).

When the two reference sequences are equal, the accumulated value is unchanged.

When r(t) and e(t) are unequal, the accumulatlon is incremented or decremented by the value of s(t) depending upon the value of r(t).

Correlation detector 700 comprises an analog-to-digital converter 702 that receives ~he analog sequence s(t) and in response generates a corresponding digital signal at output terminal D. me output of analog-to-digital convertor 702 is applied to one input A of an adder/subtracter circuit 704 having an output applied to the input of an accumulator register 706.

~he output of the accumulator 706 is applied to output register 708 and also to the second input B of adder/subtracter 704.

~2~7~ - 31 Operation of the units 702-708 as wel1 as of a sequencer 710 are synchroniæed to a bit period ~.

Sequencer 710 in turn controls the conversion times of A~D converter 702 and the accumulation times of accumulator register 706 at outputs 71~ and 714, respectively.

The accumulator registes 706 is also controlled by the values of the two refrence sequences r(t) ~nd e(t) through exclusive-oR gate 716 and AND gate 718.

The adder/subtracter 704 develops an output signal which is the sum of the digitized input sequence s(t) and the contents of accumulator register 706 when reference sequence r(t) is 1 and generates the difference between the accumulator register ~ontents and the digitized value of input sequence s(t) when reference sequence r(t) is zero.

Selective addition and subtraction of the two signals applied at adder/subtracter inputs A, 3 are controlled by the signal applied at input F, developed by reference sequence r(t) through an inverter 720.

If r(t) equals e(t), the exclusive-OR gate 716 develops a logic 0 signal that is applied to one input of AND gate 718.

To the output input of AND gate 718 is a write-accumulation signal developed by sequencer 710.

Sequencer 710 alternately develops a "convert input~ signal applied to AfD converter 702 to provide an analog-to-digital conversion of input sequence s(t) and a ~write accumulator~ signal which adds or subtracts the instantaneous value of s(t) to the current accumulated value, to be aFplied to output register 708 and then to microprocessor 314 (~igure 11) which develops binary output and timing error signals.

m us, the content of the accumulator register 706 remains unchanged when r(t) equals e(t) under control of an exclusive-aR gate 716.

When r(t) equals a logic 1, the content of accumulator register 706 is incremented by the value of the incoming sequence s(t); when r~t) equals a logic 0, on the other hand, the content of the accumulator register is decremented by the value of the input sequence s(t). ~nis 'nas the effect of multiplying s(t) by +l or -1 and integrating.

- 3~ m e correlation detector 700 of :Figure 15 is generalized into an N-channel correlation detector 800 in Figure 16.

The reference sequences r(tn) and e(tn) are applied to an input latch 802 having r(tn) and e(tn) outputs tnat are applied respectively to a pair of N to 1 multiplexers 804, 806.

The outputs of the two multiplexers 804, 806 in turn are applied to the inputs of exclusive-OR gate 808 that controls accumulator memory 810 through AND gate 812.

Accumulator memory 810 in Figure 16 corresponds to accumulator r~gister 706 in Figure 15.

Memory 810, however, contains a plurality of memory regions corresponding to each channel and addressed by a channel sequencer 814 controlled by the output of sequencer 816.

Similarly, the output of accumulator memory 810 is applied to an output memory 818 that corresponds to output register 708 in Figure 15.

Memory 818, however, contains a plurality of memory regions corresponding to the correlation channels and addressed by the output of sequencer al6.

m e incoming sequence s(t) is sampled by a sample and hold circuit 820 and applied to analog-to-digital converter 822 wherein the .inccming an~og sequence s(t) is digitized and aFplied to adder/subtracter 824 in a manner described with respect to Figure 15.

In operation, sample and hol~ circuit 820 samples the inconing analog sequence s(t) and converts the samples ~o 2S corresponding digital values in synchronism with the bit period T developed by microprocessor 314 (Figure 11) and applied to sequen oe r 816. ~he content of the accumulator memory 810, within each memory region addressed by sequencer 816 is incremented or decremented by the current value of s(t), depending upon the value of the referen oe sequen oe r(t) at the corresponding channel.

The circuit 800 thus successively samples the input sequence, multiplies the sequence by +l or -1 and integrates for each channel N, under control of channel sequencer 814 and sequencer 815, as well as of the microprocessor 314. T.he accumulator memory _ 33 ~ '7~S 810 and output memory 818 thus monitor N accumulation channels, with time synchronism of signals during channel sequencing being preserved by the sample and hold circuit 820 and the input latch 802.

Referring now to Figure 17, another digital implementation of a single channel correlation detector 900 co~prises a conventional voltage-to-frequency converter 902 that receives the absolute value of input sequence s(t) through an absolute value circuit 904.

Absolute value circuit 904 is required because the volt ge-to-frequency converter 902 responds, as is conYentional, to a unipolar input signal.

Voltage-to-frequency converter 902 converts the instantaneous magnitude of the inccming sequence s(t) to a single corresponding frequency signal to be applied to an up/down counter 906 through one input of an AND gate 908.

lS The input sequence s(t) is also applied to an analog comparator 908 which keeps ~rack of the polarity of the input sequence s(t).

In other words, the output of the analog comparator 908 is representative of the sign of the input sequence s(t).

The reference sequences r(t) and e(t) are applied to the remaining input of gate 908 through exclusive-OR gate 910.

The up/down counter 906 is controlled by a second exclusive-CR gate 912 that receives the output of the analog comparator 908 and the first reference sequence r(t).

Thus, the up/down counter is controlled to increment when the signs of the input sequence s(t) and reference sequence r(t~ are the same;

otherwise the counter is caused to decrement.

The output of counter 906 is applied to a latch 914 synchronized to bit period T.

The clock CL~ of up/down counter 906 is disabled by exclusive CR gate 910 when the two reference sequences r(t) and e(t) are equal to each other.

Otherwise, the counter clock is enabled and the counter 906 tracks the incoming sequence s~t).

In other words, when r(t) is 1, the counter counts up for a positive polarity sequence bit s(t) and counts down for a negative polarity sequence bit s(t).

When the reference sequence r(t) is a logic - 34 zero, on the other hand, accumulation is subtracted and the count direction is ceversed.

The circuit 900 of Figure 17 is generalized to N channels of correlation detection by circuit lO00 in Figure 18.

In circuit 1000, voltage to-frequency converter 1002, absolute value circuit 1004 and analog ccnparator 1006 correspond to corresponding components in Figure 17 and are common to all channels.

Up/down counter 1008 as well as ~ND gate 1010 and exclusive-OR qates 1012 and 1014, however, are duplicated for each channel.

The output of each binary up/down counter 1008 is applied to a latch L016, commonly synchronized to a bit period T.

The outputs of the N latches are applied to mic~oprocessor 314 (such as shown in Fig.

ll) which processes the individual channel correlation siynals and in response develops binary data recovered from the predetermined transmitter and timing signals to shift receiver timing into synchronism with the predetermined transmitter.

~ynamic Synchronization As discussed above, static synchronization involves establishing predetermined delays in the receiver that correspond to different propagation times associated with different transmitters.

Static delays, preset in the receiver during initial set-up, synchronize the transmitter and receiver to within one code chip of each other. ~erfect correlation is then established by microprocessor 314 in response to the correlation signals developed by the correlation detectors described above.

~icroprocessor 314 more specifically processes the channel correlation signals to control receiver timing to synchronize to the predetermined transmitter in two stages; namely, fine and coarse tuning, followed cy synchronization correction, if recessary, to the proper pulses of the system clock.

Referring again to Figure 10, it is recalled that code correlation is a function of code chip time delay differences between a received code and a reference code and, depending upon - 35 the particular correlation peoperties of the code employed, has a peak when synchronization is achieved and has an absolute value that drcps to zero as the synchronization difference approaches a code chip or greater.

Data are recovered from the correlation pattern, based upon the reccgnition that the sign of the pattern depends upon the data bit used to modulate the transmitter.

Thus, when the receiver and a predetermined transmitter are properly synchronized to each other, transmitted data are recovered by monitoring the sign of the voltage Vl at the primary correlation channel.

Fine Tuning Referring to Figure 19, a correlation pattern corresponding to the correlation pattern shown in Figure 10 is identified by 1100.

This is an ~in-phase" correlation pattern, with coarse correction channels Vl, V2, V3, V6 and V7 tha~ are used to determine which of the correlation peaks corresponds to the primary channel, with maximum correlation at synchronization.

An additional pair of channels V4, V5 are fine, or vernier, correction channels, which maintain receiver synchronization by maximizing the correlation output of the pr~mary channel Vl.

In the foregoing discussion, it should be rec~gnized that all references to fraction of a code chip are related to the ratio between the carrier frequency and code seneration frequencies.

As one example, the carrier frequency is 5670 Hz, and the code generation frequency is at 3870 bits/second, so that references to fractions of a code chip are related by a ratio of 3/2, allowing three peaks per code chip.

The additional correlation curve 1200 in Figure 19 is a quadrature-phase correlation curve that is di-placed from the in-phase correlation curve by 90 degrees. ~he significance of the quadrature-phase correlation curve is that the value of the quadrature-phase curve is at zero when the value of the in-phase quadrature curve is at a maxLmum.

As shall be discussed below, signal processing, and particllarly correlation peak detection, is simplified using quadrature phase correlation.

~ 2 ~ 7 ~ - 36 Because there are three correlation peaks per code chip, assuming that the primary correlation channel Vl is within a code chip of being properly synchronized, the orimary channel Vl is wlthin one-sixth of a code chip of a "local" peak.

Fine tuning causes the receiver to adjust its timing, under control of microprocessor 314, such that the correlation channels Vl, V2, V3, V6 and V7, spaced apart from each other by one-third of a code chip, are all located at local peaks.

One method of adjusting receiver timing to locate the five correlation channels to local peaks is by serial hunting shown in the flow chart given in Figure 20(a).

This involves use of a preamble of a length 2(p s), where s is the numker of smoothings on each bit and p is equal ~o one-sixth (in this example) of a code chip period divLded by the receiver correlation resolution, or the number of correlations of minimum resolution required to adjust the receiver from a synchronization null to a peakO For each data bit in the preamble, the receiver primary correlation channel Vl timing is adjusted by a minLmum fraction 1/6(p) of a code chip (step 1320) and the magnitude of the correlation voltage Vl is stored (1330~.

This process is repeated until the receiver has changed its timing over a maximum o a full one-third of a code chip (1340).

Thereafter, ~he point at which the magnitude of the primary correlation Vl is at a maximum is selected as being the local peak ~1350), and the timing of tne 2S receiver is adjusted to position channel Vl at that point (1360).

An alte~native fine tuning method controlled by microprocessor 314 is tne use of fine tuning channels V4 and V5 shcwn in Figure 19. ~ne fine tuning channels V4 and V5, provided by an additional pair of correlation detectors (not shown), are offset in time from the pr~mary correlation channel Vl by an equal fraction of a code chip that is less than one-sixth of a code chip.

Optionally, a preamble may De included in the method, having a ~orst case length of p- s with a mlnimum receiver correction (resolution) being l/6(p) of a code chipo Referring to ~z~ ~ 37 ~ Figure 20(b), the correlation voltages V4 and VS are applied to microprocessor 314 (step 1950) along with the correlation voltage of the primary channel Vl.

By comparing the relative magnitudes of V4 and V5 (steps 1960, 1970), the microprocessor determines the direction toward which receiver timing is to be shifted ~steps 1980, l990) to pcsition the primary channel Vl at the major local correlation peak. A system of this type is shown schematically in Figure 21.

Programming of microprocessor 314 is omitted for brevity, but is considered routine to implement based upon the simplified flow chart of Figure 20(b) and the discussion herein.

Another alternative fine tuning method involves the use of a channel whose tLming is generated with a quadrature-phase carrier. ~2cognizing from Figure 19 that the nulls of the quadrature-phase correlation pattern 1200 occur at ,he peaks of in-phase correlation pattern llO0, an error voltage may be developed by microprocessor 314 based upon the sign of the product of the in-phase and quadrature-phase patterns.

The sign of the error voltage thus indicates a direction to which receiver timing must be shifted to cause the receiver correlation channels to synchronize to local correlation peaks.

It is also possible to apply the magnitudes of the in~phase and quadrature-phase correlation voltages 1100 and 1200 to determine not only the direction of shift of receiver timing to achieve synchronization but also the amount of shift required ~o obtain a local peak.

Thus, in accordance with another aspect of the invention and as summarized in the flow chart of Figure 22(a), the in-phase Vl and quadrature-phase Vlq correlation voltages are measured (step 2050).

The ratio of the in-phase Vl and quadrature-phase Vlq correlation voltages is calculated (2060), and if the ratio is positive (2080), the t~o correlations are presumed to have ~he same polarity and receiver timing delay is increased (2~95);

otherwise, ~he t~o correlations are presumed to have opposite polarities and receiver timing delay is decreased (2090).

To prevent receiver timing from being changed if the receiver is 38 perfectly synchronized to the predetermined transmitter, and to avoid ccmplications caused by delay in the receiver whereby a correction decision is made using information that is more than one data bit old, the absolute value of the ratio Vl/Vlq, which is S essentially a cotangent function, is monitored. A table stored in a memory associated with microprocessor 312 relates the ratio Vl/Vlq to the number of fine tuning corrections, e.g., 1/48th of a code chip for each correction, to reach optimal synchronization.

The table is se~ forth below.

~BLE IV Number of Corrections (Equal fractions o~ a Vl/Vla Code Chip) 0 00 lS 1 5.02 2 2.41 3 1.49 1 . 00 0.668 6 0.4149 7 0.1999 8 0 Thus, the number of corrections applied to receiver timing is determined directly from vl/vlq~ and there is a correction dead ~and when the ratio is greater than 5.02, eliminating receiver hunting about optimum synchronization.

Furthermore, the n~mber of data ~its ne~ded to move the receiver from a correction null to a correlation peak is reduced from 8 (in this example) to as l~w as 1, minimizing the length of any required preamble and providing accelerated serial hunting.

Finally, it is possible to inhibit tracking corrections on consecutive data bits without decreasing the tracking rate of the receiver, ~hereby eliminating overshoot.

- 39 Signal Presence Detection The provision of quadrature-phase Vlq as well as in-phase Vl correlation voltages furthermore makes it possible to determine a signal present withLn a background of noise.

As summarized in the program flow chart of Figure 22(b), when only noise is present at the receiver input, both the in phase Vl and quadrature-phase Vlq voltages will have approximately the same value R, such that the ratio Vl~Vlq will be close to unity With both signal and noise present, however, fine tuning maximizes Vl and minimizes Vlq to obtain a ratio much greater than unity. m e ratio Vl~Vlq is ~IUS used as an indication of signal present.

In practice, the ratio may be monitored over a number of data bits, with smoothin~ techniques or majority vot mg being a~plied to ensure acc~racy.

Circuitry for detecting presence of a signal in a background of noise is shown in Figure 21, with microprocessor 314 developing signals Vl and Vlq in response to the outputs of the correlation detectors discussed above. ~he signals Vl, Vlq are processed with the microprocessor 314 to develop the ratio Vl/Vlq and the absolute 0 value Vl~Vlq of the resultant is magnitude compared with a predetermined threshold magnitude to determine whether an incGming signal represents a data transmission or whether it is merely noise.

Following determination that the receiver is tuned to a local peak using fine tuning as described above, it becomes necessary to determine through coarse tuning, whether the current local peak is the ~correc_" local peak such that the receiver has best correlation.

Coarse Tuning In accordance with one embcdiment, coarse tuning of the receiver to a predetermined transmitter to ensure that the receiver is tuned to the maximum, and other than a secondary, correlation peak involves serial huntin~ wherein, having once fixed a point as a local peak, the receiver is adjusted in ~o~ - 40 multiples of one-third of a code chip to measure the magnitude of the receive sign31 at each ~djacent local peak~ Once the magnitudes of the peaks are determined, a decision as to the proper peak is made.

Because the magnitudes of adjacent peaks near the center of the correlation pattern are difficul~ to distinguish from one another due to channel filter distortion, a conventional "center-of-mass" approach may be used to identify the maxlmum local peak by basing the decision on the relative values of alL channels rather than on only a selection of the channel having the greatest correlation magnitude.

The microprocessor 314 is programmed in a coarse tuning, serial hunt mode to cause the receiver, following identification of a local peak, to shift in timing by multiples of one-third of a code chip, measure and store correlation magnitudes and make ccmparisons using the center of mass approach or other approach to identify the correct correlation peak.

Serial hunting requires a transmission preamble of length Wo 5 where W is the width of the peak search range (in thirds of a code chip) and s is the number of bits of smoothing in the voltage readings.

In Figure 23, a slmplified flow chart of programming of microprocessor 314 to provide coarse tuning by serial hunting include~ a test at step 1~00 to determine, using fine tuning as discussed above, whether the receiver is at a local peak. IE the receiver is not at a local peak, the receiver is fine tuned until the ceceiver is determined to be at a local peak.

The receiver, once at a local peak, is incremented (step 1202) until its timing is at R + N, wherein K is the timing of the local peak obtained during fine tuning and N is a predetermined number of thirds o~ a c~de chip.

The correlation value of ~ + N is measured and stor~d (step 1204), and the receiver timing is decre~ented by one-third of a code chip (step 1206).

The correlation of the receiver and predetermined transmitter is now measured and stored (step 1208), and receiver timi~g is tested to determine whether it is at (R - N), that is, at the opposite side of the initially de~ected . .....

~ ~?7~S - 41 loc~l peak R ~step 1210).

If not, the receiver timing is again decremented and the correlation is measured and stored.

Otherwise, all the stored correlations are tested (step 1212) to identify a peak correlation.

In accordance with another ~mkodiment, to reduce the preamble length, multiple secondary receiver channels, offset from each other by multiples of one-third of a code chip on both sides of the primary chanr,el Vl develop primary and secondary correlation signals to be applied to microprocessor 314.

The microprocessor 314 is programmed, using center of mass analysis or other analysis, to identify the primary channel Vl which has the greatest maximum correlation and the secondary channels.

By using a multiple num~er of receiver channels or correlation detectors, rather than serial hunting circuitry or programming, the length of the preamble required for coarse corrections may be reduced to the number of bits of smoothing, s. miS assumes of course that for the desired width of search, a channel exists with common offsets of multiples of one-third of a code chip on both sides of the primary correlation channel Vl.

With multiple receivers it is not necessary to program the microprocessor to serially hunt.

The microprccessor 314 is instead programmed to simply compare the outputs of the correlation detectors, all tuned to a local ~eak, to identify the peak having the greatest magnitude.

Timing Signal Correction I the data bit rate of the transmission is less than one-half the pulse repetition rate of the timing source, the transmitter and receiver may become locked to different timing pulses even though they appear to be perfectly synchronized to each other.

For example, for a data bit rate of 30 bits ~er second, a timing pulse source of 60 Hz and a carrier frequency located between 60 Hz harmonics, the transmitter may ~ecome locked to a first 60 Hz timing pulse with the receiver locked to the next - 42 ~ S successive 60 ~z timing pulse.

An alternating data transmission will not be detected due to improper receiver data timing recovery with otherwise perfect synchronization between the receiver and transmitter.

To illustrate this condition more clearly, Figure 24(a) is a diagram representing the timing pulses to which the receiver and a predetermined transmitter are synchronized.

The transmitter carrier is shown in Figure 24(b~ and transmitted data representing alternate ones and zeros are shown in Figure 24(b).

Assuming that the receiver and transmitter are synchronized to the same timing pulses, the integrate and dump circuits 310 of the receiver will ~e synchronized to the transmitted data inversions so as to dump at the trailing edge of each datum, as shcwn in Figure 24~d), where ndots" designate integration dump points.

The sampled integrator output is thus a replica of 'he data embedded within the transmission.

If the transmitter and receiver are not synchronized to the same timing pulses, however, the integrate and dump circuits 310 will not be properly synchronized to the data being transmitted.

Ihis condition is shown is Figure 24(c), where the integration dump points occur between transmission data inver~ions, and the sampled output of the integrator 310 is at zero.

In other words, with the receiver and transmitter respectively synchronized to successive~ rather than the same, timing pulses, it is impossible to recover any of the transmission data.

It is therefore necessary to test the receiver and transmitter to ensure that the two units are synchronized to the sam~, rather than successive, timins pulses.

In accordance with one asFect of the invention, associated with the primary receiver channel Vl is a secondary receiver channel Vl' having a built-in additional delay of one-half a data bit.

One of the two channels Vl and Vl' will always therefore detect the transmitted signal. A determination is made by applying an alternating data preamble associated with the - 43 - ~ O 5 transmission to the primary and secondary receiver channels.

By comparing the magnitudes of the correlation outputs of the two receiver channels, the correct channel (having the larger correlation magnitude) is tne one synchronized to the same timing pulse as the transmitter is.

Data are monitored at the "correct" channel only.

~ simplified circuit for synchronizing receiver timing to cause the receiver and transmitter to be locked to the same timing pulses as shcwn in Figure 25. t~icroprocessor 314 develops a secondary channel Vl' offset from channel Vl by one-half of a da~a bit.

In response to an incQming sequence having an lternating preamble, the microprocessor co~pares the magnitudes of the data outputs from the channel Vl and its half bit delayed channel Vl', and identifies the one channel having the larger ~agnitude.

This channel is thus presumed to be the one which is locked to the same timing pulses as the transmitter is, and is reapplied to the micro~rocessor for data recovery.

In an alternative embod~ment of the invention, the need for the secondary receiver channel Vl' may be eliminated. m e transmitter and receiver can be synchronized when the timing reference frequency is less than or equal to the data sampling rate and the ratio of the data sampling rate to the timing reference frequency is an integer by combining more than one of the consecutive data samples together to yield one data point or bit.

By ccmbining these data samples, an optimum data sample point may be determined while receiving an alternating sign preamble by comparing the magnitudes of all possible summations and selecting the sample which give a maximum output.

If each sample is assigned to its own synchronization point, then synchronization may be accomplished by locking to the time that gives the maximum output.

For example, if the timing signal has a frequency of 60 Hertz and a data sanpling rate of 30 samples per second, for a data rate of 30 bits cer second each data sample is used to yield one data _ 44 - ~Z~ 5 point or bit.

For data rates of 15, 7.5 or 3.75 bits per second two, four and eight consecutive data s~.,yles are used to yield one data bit.

In addition to eliminating the need for a redundant data channel, the above technique eliminates the need for the data sampling rate to be the same as the data rate.

In fac~, sampling may occur at a rate higher than the data rate.

This aLlows the data samples to be combined digitall~, for example in a microprocessor, and allows the data rate to be independent of the actual hardware timing.

Data Recovery Data recovery in spread spectrum systems is ~ell known.

As background, reference is made to section 5.3 of the Dixon text mentioned earlier, and p2rticularly to the discussion of Costas loop demodulators beginning on page 155.

Because the spread spectrum system as provided herein includes muLtiple correlation channels, data recovery is Lmproved in accordance with one aspect of the invention by extracting data at each channel rather than at only a single correlation channel.

It is thereby possible to lower system message error rate and possibly to also reduce the length of or eliminate any required preambles for receiver synchronization.

With reference again to Figure 19, i~ is noted that the correlation pattern 1000 is centered about the primary correlation channel Vl.

The sign of the primary correlation channel Vl is dependent upon the sign of the data being transmitted. A positive value of Vl thus corresponds to a logic 1 being transmitted whereas a negative value of the correlation Vl corresponds to a logic 0 being transmitted.

The correlations at V2, V3, V6 and V7 also have values that correspond to the sign of the data being transmitted.

Specifically, the relationship of the voltage outputs at channels Vl, V2, V3, V6 and V7, in the absence of noise and distortion, are described as follows:

~7~05 - 45 V2 = V3 - Rl Vl V6 = V7 = R2 Vl where (7) ~ 2/3 S R2 = 1/3 In accordance wi~h the invention, the data sign at the output of each correlation detector, following proper receiver synchronization, is monitored. Depending upon the characteristics of noise and distortion, data may be extracted using only tne outputs at channels Vl, V2 and V3, witn an effective signal-to-noise ratio gain of (l+lJL) ( ~ uj ~j)2 (8) (l+l~L)- ~ u; 2 + 2 (Rl+l/L) ul (u2+u3) + 2-(R211/L)~u2~u3 j=l where R = relative noise free amplitude of Vj witn respect to Vl, i = 2, 3 (Rj ~ Rl in the distortion free case), L = the length of the pseudo-random code and u; = weighting factor for Vj, j = 1, 2, 3.

The weighting factors are selected according to the particular distortion present.

Figure 26 is a sLmplified circuit diagram showing microprocessor 314 responsive to channels Vl, V2 and V3 and programmed to ccmbine all three correlation channel out~uts to extract transmission data, with weighting factors selected according to particular distortion known to be present on the transmission medium.

Table V illustrates the signal-to-noise enhancements under a few possible distortion and weighting factor scenarios.

7~5 - 46 ~BLE V S/N 5 W2IGHTI~G FACTCRS FCR Vj DISTCRTIGN FA~TORS FCR Vj DMPRCVEMENT Ul U2 u3 kl k2 k3 FACTOR _ _ . _ 1 -1 -1 1 -1 -1 1.44 _ 1 -1 -1 L -0.9 -0.9 1.254 _ _ _ _ _ :

1 -1 -1 1 -0.8 -0.8 l.Oa2 , , .

1 -1 -1 1 -0.7 -0.7 O.g22 _ _ _ .

1 -0.34 -0.34 1 -0.67 -0.67 0.971 1 -0.67 -0.67 1 -0.67 -~.67 0.918 _ _ ._ 1 -0.9 -0.6 1 _~.9 -0.6 1.055 _ _ _ _ 1 -0.8 -0.8 1 -0.~ -0.8 1.09 _ 1 -0~9 -0.9 1 -0.9 -0.9 1.252 . _ .

An additional advantage of providing a recovery on all channels of the receiver is that random and burst errors, which tend to affect all channels, can be identified and ignored.

This is s~milar to signal presence detection using in-phase and quadrature-phase correlation outputs, as discussed above, but employs all channels rather than orthogonal outputs associated with a single charnel.

Furthermore, as an additional advantage of obtaining data recovery at all correlation channels or at least sever~1 correlation channels, it is possible to monitor synchronization during meassage reception.

Although synchronization adjustments are not feasible during message reception, the message content may be recovered, without repeats, using the additional receiver channels.

In this disclosure, there is shown and described only the preferred embodimen~s of the invention, however, it is to be s - 47 understood that the invention is capable of use in various other combinations and environments and is caFable of changes or modifications within the scope of the inventive concept as expressed herein.