Radio frequency (rf) integrated circuit (ic) packages with integrated aperture-coupled patch antenna(s) in ring and/or offset cavities

-1 / 18 RADIO FREQUENCY (RF) INTEGRATED CIRCUIT PACKAGE (RF) WITH INTEGRATED COUPLED OPENING ANTENNA (S) IN RING AND / OR DISPLACED CAVITIES AND THEIR MANUFACTURING METHOD

FIELD OF THE INVENTION

The present invention in general relates to circuitry of

......... communication and more particularly. radio frequency (RF) integrated circuit (Cl) packages.

BACKGROUND OF THE INVENTION

In a wireless network, connectivity and communication between devices are achieved through antennas coupled to receivers or transmitters, in order to radiate the desired signals from or to other elements of the network. In radiocommunication systems, such as millimeter wave radios, in general, separate components are assembled with low levels of integration. These systems are often assembled using waveguides and microtrail-level or plate-level structures, which are too expensive and too large to interconnect semiconductors and the necessary transmitting or receiving antennas. With the recent progress in semiconductor technology and package engineering, the dimensions of these radio communication systems have become smaller. For applications such as wireless USB (universal serial bus), the operating distance is limited to approximately one meter and a single antenna of about 7 dBi at 60 GHz will provide the required antenna gain. For distances of 10 meters (such as wireless video) or greater (such as radar), in point-to-point applications, an increase of the order of 30 dBi of the antenna gain is required, depending on the application. However, high-gain antennas for wireless video applications have very narrow beam widths, making it very difficult for the consumer to point the antenna. Therefore, a steerable array radiation pattern is required, such as a phased array (control of several signals). Phased arrays are also widely used on military radars. However, the packaging of

-27 18 radio frequency with integrated antennas or phased array is extremely difficult and very expensive due to the expensive components and the intense work involved.

SUMMARY OF THE INVENTION

The foundations of the present invention provide techniques for implementing Cl RF packages with ____ coupled opening patch antennas integrated in, for example, ring and / or displacement of cavities.

In one example of an embodiment, in accordance with one aspect of the invention, a radio frequency chip integrated circuit package with N opening patch antennas, N at least 2, includes N generally 10 planar seams, and at least one ground plane generally planar spaced internally from the N planar seams and considerably parallel to them. The ground plane is formed by at least N opening slits coupled to it, and the slits are considerably opposite to the seams. Also included are N power lines spaced internally from the ground plane and 15 considerably parallel to it, at least one radio frequency chip spaced internally from the power lines and coupled to the power lines and the ground plane, and a first layer of substrate spaced internally of the power lines. The first substrate layer is formed by a chip receiving cavity, and the chip is located in the chip receiving cavity 20. An additional element includes a second layer of substrate interposed in the region between the ground plane and a plane defined by the splice. The splice is formed of a first layer of metal, the ground plane is formed of a second layer of metal, and the second layer of substrate defines an antenna cavity. The N planar splices are located in the antenna cavity.

Optionally, an island is formed in the second substrate layer, inside the cavity, thus defining the ring shape of the cavity, and the N planar seams are located in the shape of a ring. The island is considerably ^ óostãrà⁷ dochip receiving cavity; —- - - - -3 / 18In another optional approach, the antenna cavity is spaced out (offset) from the chip receiving cavity when viewed in plan, so that the charges during insertion of the chip into the chip receiving cavity are considerably supported outside the antenna cavity.

In another aspect, a method of fabricating a radiofrequency chip integrated circuit package with N opening-patch antennas - ~ - “- coupled, -beingN-nominimo-two_>-equeinciui.ospassosparao_fornecirnento_of the package of the type described (minus the chip), with the optional island as described and inserting at least one radio frequency chip in the cavity, and this island 10 supporting induced loads. by inserting the chip into the cavity.

In yet another aspect, a method of fabricating a radiofrequency chip integrated circuit package with N integrated coupled opening patch antennas, N at least two, and which includes the steps for supplying a package of the type described (minus the chip), with the optional cavity displacement configuration 15 as described, and inserting at least one radio frequency chip in the cavity, so that the charges existing during the insertion of the chip in the chip receiving cavity are considerably supported away from the antenna cavity.

One or more embodiments of the invention are suitable. 20 for automatic processes and reduce the number of components previously involved with the packaging of antennas.

These and other objects, features and advantages of the present invention will become apparent from the description of illustrative embodiments of the invention detailed below, which should be read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

- ,· ., ,_w, -rwT, A₃FiG_L-1- shows a_iiexample_Íin_:!concretization.de_; a package, in cross-section, according to an aspect of the invention;

-47 18A FIG. 2 shows an example of an embodiment of another package, in cross section, according to another aspect of the invention; ,

FIG. 3 shows an example of carrying out yet another package, in cross section, according to another aspect of the invention;

FIG 4 is the bottom view of an example of a package without a reflector or with a built-in reflector.

FIG. 5 is the bottom view of an example package with a visible reflector.

FIG. 6 is the bottom view of an example of an embodiment of a planar phased array.

FIG. 7 is the top view of a rectangular ring cavity package, according to an additional aspect of the invention (note that the terms top view and plan view are used interchangeably here);

FIG. 8 is a cross-section taken along line VIIIVIII of FIG. 7;

FIG. 9 is a larger version of the FIG. 7;

FIG. 10 is a cross-section taken along line XX of FIG. 9;

FIG. 11 is the top view of a circular ring cavity package, according to a further aspect of the invention;

FIG. 12 is a cross-section taken along line XIIXII of FIG. 11;

FIG. 13 is a smaller version of the FIG. 11;

FIG. 14 is a cross-section taken along line XIVXIV of FIG. 13;

4'

-5/18)

FIG. 15 is a top view of a displaced cavity package (side by side), according to a further aspect of the invention;

FIG. 16 is a cross-section taken along line XVIXVI of FIG. 15;

FIG. 17 is the top view of an example configuration of sixteen phased array antennas, according to an even more^r~ ^^ ~ ^ ãvançãdÕclã * irivêh'çãÕ; e—

FIG. 18 is the top view of an example configuration of sixteen phased array antennas, in accordance with an additional aspect of the invention.

DETAILED DESCRIPTION OF THE INVENTION

One or more embodiments of the invention provides an apparatus and method for low-cost packages with integrated antennas and dynamic phased array, operating in the millimeter wave range. An example of an inventive package 15 with integrated antennas is based on a multilayer printed circuit board (PCI). The package contains, for example, a rectangular or ring cavity for implementing high-performance antenna (s) or antenna arrays and another cavity containing millimeter radiofrequency (RF) waves of integrated circuit chips. One or more embodiments of the invention 20 also provide techniques to overcome the difficulties of making internal cavities and to avoid the need to employ wirebonding electrical interconnection technologies at millimeter wave frequencies. Embodiments of packaging technology are consistent with the printed circuit board (PCI) manufacturing process and can be used for packages with an integrated antenna or antenna array.

Thus, cases of the invention provide low-cost packaging with integrated or planar phased array antennas; in particular, the ^ ^ packaging ^ of ^ chip ^ with integrated rantenas or phâsèd ~ arrãy ^ pláriare ~ s' designed for millimeter-wave and higher frequencies.

-6 / 18Typical chip packages with integrated antennas have three main parts: (i) an RF chip, (ii) one or more antennas, and (iiij a packet carrier (and in some cases a cap or cover, or an encapsulator) to protect the package). One or more embodiments of the invention provides a package 5 which has a high performance antenna, interface for interconnecting an RF chip by the Flip-chip method and interface for interconnecting the package by the Flip-chip method with a printed circuit motherboard.

_ ___ FIG- - shows a cross-sectional view of an example of package 100, according to an aspect of the invention. Note that, for better clarity, the section line has been omitted from all figures. The package has seven total layers, including substrate and bonding layers. For millimeter wave applications, especially in the case of frequencies above 60Hz, it is necessary to consider a bonding film and / or layer thickness in the design process. With the explanations provided here, a person with knowledge of antenna and packaging will know how to consider thickness and how to employ high precision PCI fabrication techniques to make embodiments of the invention. Package 100 also has a few layers of metal. In particular, there is a substrate further away from the center. Right afterwards internally there is a metal layer used for the splice (s)

104 of the patch antenna (s). Inside the substrate 102 and the patch antenna 104 (the

FIG. 1 depicts a single antenna, but more can be provided, as discussed below) there is a layer of bonding film 106, another layer of substrate 108 and another layer of bonding film 109. Another layer of metal, on the inside of the bonding film 109, is used for the ground plane

110 of the patch antenna. Slots 113 in the ground plane are used for the openings of the coupled opening antennas. The ground plane 110 also separates the radiating elements (splices) 104 from the power line (s) and the RF chip (s), as discussed below.

Another substrate 112 is inside the ground plane 110. Another 30 _ layer of ^ metaLinterna_ao__substrato ^, L12_x,It is_Theused_andto- implement the antenna power line (s) 114, islands 116, 118, 120 for RF chip connections [preferably a type of flip-chip / C4 technology connection (“connection

4'

-7 / 18 of controlled collapse chip ”)] and interconnection (s) 122 (when appropriate) to one or more conductive paths, such as conductive path 124, in an additional layer of bonding film 126 within the metal layer forming the feed line 114 and another substrate 128 within the bonding film

126. Another layer of metal provides all the islands for signaling, control, power supply and ground connections to the printed circuit motherboard (the printed circuit motherboard has been omitted in the figure for greater __ _. ----- -clearzaj.-rAsJlhas ^ may -include the interconnected earth-130 ^ with the plan ^ ground ^:

110 through the earth path 140, as well as one or more signaling, energy and control islands exemplified by the island 132 connected to the interconnection 122 and the isolation area 142 by the path 124. The conductive paths can be, for example, forged through boreholes. ticket. Package islands can also be provided. Depending on the patch-antenna design, an optional 144 reflector can also be implemented in the same metal layer as the islands

130, 132, 134. In some situations, as discussed below, reflector 144 is built-in.

In order to implement the flip-chip approach, chip 162 should preferably have a plurality of solder points directly connected to the connection islands of chip 116, 118, 120.

To increase the bandwidth of the patch antenna, the splices can be suspended in the air or secured with foam material with a dielectric constant close to that of low frequency applications. Suspended or foam supported seams, however, are not realistic for millimeter wave frequency, especially for packaging applications. Thus, in one or more embodiments of the invention, an air cavity 150 can be implemented in the packages. To avoid problems with hot gases during the PCI manufacturing process, ventilation hole (s) 152 may be employed. These holes may be designed in such a way that they have little effect on the performance of the antenna. For example, hole 152 can be located near the middle of the cavity 150 or near the end of the cavity 150, and can be made relatively small, consistent with adequate ventilation. The ventilation holes may be above (in the furthest part) from the cavity

-8/18150, as shown in FIG. 1 or next to the cavity, as discussed below, depending on the manufacturing process used.

The earth piano 110 is also used to make earth connections through conductive paths (eg 140) and signal, power and control connections through conductive paths and isolation area (eg path 124 with isolation area 142, illustrating a path with isolation area that could be used for signal, energy or control functionality). The - ^ “^ '- ^“' “'áfeãsriè ^ isolamerito are beneficial from the manufacturing point of view, and result in greater reliability, as it is difficult to obtain reliability on partial paths (ie paths such as 124 that do not extend completely through the structure ) without using isolation areas.

An open chip receiving cavity or socket 160 is shown on the substrate 128 and on the connecting film 126. This socket is used to hold the RF chip 162. The chip is attached to the package by the flip-chip method.

It should be noted that all components of the onameter (antennas, power amplifiers, low noise amplifiers and the like) are in package 100. Paths 124, 140 are used for passing DC frequency signals or much smaller.

Package 100 can be attached to the motherboard (not shown) with advantage by means of encapsulation with balls (BGA).

FIG. 2 shows an embodiment 200 considerably similar to embodiment 100, except that reflector 144 is encapsulated by an additional bonding layer 170 internal to reflector 144 and an additional substrate 25 172 inner of bonding layer 170. Similar items received the same number of reference and will not be described again. Chip receiver socket 160 is also formed on substrate 172 and link layer 170 in this embodiment. ____

FIG. 3 shows an embodiment 300 considerably similar to embodiment 200, except for ventilation 352, located laterally,

-9 / 18 in layer 108, in order to ventilate cavity 150. Similar items received the same reference number and will not be described again.

FIG. 4 shows a bottom view 400 in which chip 162 is encapsulated with encapsulant 402. The chip can be partially or completely encapsulated 5, for the purpose, for example, of resisting moisture. The plurality of outer islands 404 may correspond, for example, to annexes, heat conduction, or land islands such as island 130, while the plurality_of, inner islands 406 may 'correspond, for example, to signal control or islands of force, as the island 132. In FIG. 4, there is no reflector or it is built-in. FIG. 5 10 shows a view 500 similar to view 400, with the exception of a package with a reflector 144, as in FIG. 1. Similar items were given the same reference number and will not be described again.

FIG. 6 shows an example of a 600 package with a 2x2 planar phased array layout. There can be more than two antennas on each line. This 2x2 basic control can be used to form larger matrices.

In addition to the first patch antenna 104 with the first supply line 114, the second, third and fourth patch antennas 602, 604, 606 with the corresponding supply lines 608, 610, 612 are also included. Each power line is connected to the chip 162 described above. Although, for purposes of illustrative convenience, the power lines are shown ending at the seams in FIG. 6, it will be desirable that they go beyond the corresponding seams when viewed in top or bottom views, and that they are spaced from the corresponding seam and the coupled opening when viewed in cross section, as shown in FIGS 1-3 25 (for example, a end of the supply line passes through the center of the splice (FIG. 17) or remains in the center (FIG. 18). The other end of the supply line passes through the end of the RF chip).

Thus, it is desirable that aspects of the invention include a package with a socket for an RF chip and a planar antenna. In one or 3θ = »more ° situations ^ ó ^ cliipdè RF is attached to the package by the flip-chip method. The internal cavities can be used to perfect the seam width splice

-ΙΌ / 18banda. Vent holes can be used to remove hot gases during the PCI manufacturing process. The package can be attached to the motherboard PCI by BGA. The package can implement a planar phased array.

In view of the discussion of FIGS. 1-6, it is desirable that, in general terms, a coupled opening antenna-patch package, according to one aspect of the invention, can include at least one planar splice, such as splice 104. Also included is at least one planar range .planar, ~ comoo110, internally spaced from planar splice 104 and considerably parallel to it. The ground plane is formed by at least one coupled opening slot, such as slot 113. Slit 113 is considerably opposite splice 104. At least one supply line, such as line 114, is spaced internally from the ground plane 110 and is considerably parallel to it. At least one radio frequency chip, such as chip 162, is spaced internally from the power line 114 and is coupled to the power line 114 and the ground plane 110. Also included is a first layer of substrate, such as that formed by the connecting film 126 and substrate 128, spaced internally from the feed line 114. The first layer of substrate is formed by a chip receiving cavity 160. Chip 162 is located in the chip receiving cavity 160.

With the description provided here, a PCI and antenna specialist can make embodiments of the invention. Non-restrictive examples of materials that can be used include thermoset / ceramic / fiberglass resins or similar laminates such as Rogers' R04000® series of materials (and other compatible materials) available from Rogers Corporation of Rogers,

Connecticut, USA, as well as copper for metal layers, possibly gold-plated on islands or other exposed areas. Similar techniques can be used for all of the pictured embodiments, including FIGS. 1-18.

It will be desirable and advantageous that embodiments of the invention, such as 100, 200, and 300, provide a complete package, not a simple one. _{tc = lIZ}__{=; t}^_ii^ .30c ^ »antenna-patch'separadãnôchipedeother in'packages.

-11 / 18Note that paths such as 124, 140 can be formed, for example, using foliage through the holes.

Embodiments of the invention may also include a second layer of substrate, such as that formed by substrate 108 and bonding films 106, 109, interposed in a region between the ground plane 110 and the plane defined by seam 104. Seam 104 can be advantageously formed in a first layer of metal, and the terra1.10 plane can be formed in a_:advantageous in a second metal layer.

In one or more embodiments, a third layer of substrate, such as that formed by substrate 112, is interposed in a region between the ground plane 110 and the feed line 114. The feed line 114 can be advantageously formed in a third layer of metal . In addition, one or more packages, according to embodiments of the invention, can include at least one path, such as path 190, formed in the third layer of substrate 112 and coupled to the ground plane 110. A plurality of chip connection islands, such as islands 116, 118, 120, can be formed in the third layer of metal. At least one of the chip connection islands, such as 118, can be coupled to at least one path 190 in the third substrate layer. The chip connection islands connect the chip to the power line 20 114 (island 120), path 190 (island 118) and path 124 (island 116).

One or more embodiments of the invention can include one or more signal islands, one or more control islands, and one or more power supply islands, all exemplified by island 132, as well as one or more land islands, such as 130. The signal, control, power supply and earth islands are advantageously formed in a fourth layer of metal. As noted, the provision of package 134 islands is optional.

Also included in one or more embodiments is at least one earth path, such as 140, coupling the earth plane 110 and the earth island! J30 ._ „This ^ earth path — MOaDassa ^ through the ^ first ^ and-third ^ layers of substrate (eg, substrate 112, bonding film 126, and substrate 128, in a region that does not intersect with feed line 114. One or most

-12 / 18concretisations include at least one of each strength, signal and control isolation area, such as isolation area 142, formed considerably coplanar with the ground plane 110. At least one signal path couples the signal isolation area and the signal island and passes through the first and third 5 layers of substrate. Similarly, at least one force path couples the force isolation area and the force island and passes through the first and third layers of substrate. In addition, at least one control path ___ engages the 'controlé'è ã ~' control island 'isolation area', and passes through the first and third substrate layers. As noted, island 132, path 10 and isolation area 142 are illustrative of island, path and isolation area elements that can be provided for power, signal and control functionality.

As also noted, in some situations a reflector, such as 144, is spaced internally from the third layer of substrate 15 and, in general, opposite the coupling opening slot 113. The reflector can be located on a more internal surface of the first layer of substrate (eg, on the hidden surface of substrate 128). The reflector can be exposed, as in FIG.

1, or embedded, as in FIGS. 2 and 3, in which case the package may include a fourth layer of substrate, such as that formed by the bonding film 170 and substrate 172, internally spaced from reflector 144. The reflector can thus be embedded between the first and fourth layers of substrate.

Advantageously, the second layer of substrate, such as that formed by films 106, 109 and substrate 108, is formed with an air cavity, such as cavity 150. Air cavity 150 is located between 25 seam 104 and the coupling opening slot 113 in the ground plane 110. Preferably, the air cavity is formed in communication with a passage, such as passage 152 or 352. In the latter case, as in FIG. 3, the passage is formed in the second substrate layer, in particular substrate 108. In the previous case, passage 152 is formed in an additional layer of substrate, 30 like that formed. pglq.suibst mouse -102,_FOR es paçad a · for outside the 104Γ Ά seam is formed in the additional layer of substrate and the passageway is formed in the additional layer of substrate 102.

-13 / 18- As noted with reference to FIG. 6, in one or more embodiments of the invention, two or more amendments are implemented to form a planar phased array. Thus, in general terms, amendment 104 discussed above can be referred to as a first amendment, and the power line discussed above is a first power line. The ground plane can be formed with one or more coupling opening slits, such as slot 113. The package may include one or more amendments, in general planar, such as _ the amendments. 6O2, -604. 606, spaced apart from the ground plane. The additional slits can be considerably opposed to the additional splices. The package may also include one or more additional power lines, such as lines 608, 610, 614, spaced into the ground plane and considerably parallel to it. At least one radio frequency chip 162 is coupled to the additional power line (s) and the first additional splice (s) are arranged to form a planar phased array. A single large ground plane 15 with multiple slits can be employed in phased array embodiments. A phased array can include any number of amendments greater than or equal to 2; however, powers of two are advantageous, eg, 2, 4, 8, 16, 32, and so on.

For matrix applications, the spacing between the antenna elements 20 is approximately one-half of the free space of the wavelength (for example, about 2.5 mm at 60 GHz). Thus, it becomes challenging to implement multiple antenna cavities, when the cavity wall is too thin. Embodiments of the invention that address this issue will be discussed with reference to FIGS. 7-18. One or more of these embodiments 25 advantageously provide ease of manufacture in the case of dies.

FIGS. 7 and 8 show, respectively, the top and cross views of an example of a package embodiment with integrated antennas. The elements similar to those described in the previous figures received the same reference character. As seen in FIG. 8, the package has the same “storage” as the existing package. However, there is a 750 ring rectangular cavity for all antennas, to allow greater bandwidth and high antenna efficiency. Exist

-14 / 18 still a central island 702 to support the coverage of package 102 so that it does not bend. Island 702 is also desirable so that the package does not deform during chip 162 attachment. With this configuration, more than one antenna ring (as seen in FIGS. 9 and 11) is possible and power lines 114 can be very small. The island 702 can include layers .106, 108, 109, and can be formed, for example, by a cavity 750 milled in these layers. FIGS. 9 and 10 are similar to FIGS. 7 and 8, but with a cavity_750.bigger.containing-plus-antennas—— ~ '

FIGS. 11 and 12 show, respectively, the top and cross-sectional views of another example of a package embodiment with integrated antennas. Here, a circular ring cavity 750 is employed. The circular ring cavity 750 can, in at least some situations, be easier to manufacture (since circular shapes tend to be easier to work) than the rectangular ring cavity shown in FIGS. 7-10. The island 702. it is also circular in this embodiment. FIGS. 13 and 14 are similar to FIGS. 11 and 12, but with a 750 smaller cavity containing fewer antennas. Simulations indicate that, in at least some situations, circular arrangements have slightly better irradiation patterns than rectangular ones.

For smaller panels, an offset or side-by-side configuration 20 is possible, as shown in FIGS. 15 and 16. Radio frequency chip 162 is typically much smaller than antenna arrays. Thus, this configuration will not increase the packet size much. However, the supply lines 114 will be larger than the configurations shown in FIGS. 7-14, and thus, the approach of FIGS. 15 and 16 will be more advantageous 25 for smaller matrix applications. The displacement of chip 162 in the cavity

160 antenna cavity 750 prevents undesirable deflection and stress when chip 162 is mounted in cavity 160, while layers 102, 106, 108, 109, 110, 112 above cavity 160 provide support, so there is no need for island in cavity 750. The radiation patterns of the antenna are also slightly better ^ in ^ casp ^ of ^ displacement-than-in patterns ^ for the case of the ring cavity, since the panel is completely filled. However, in at least some situations, the design of the lines

-15 / 18feeding the panel is more challenging in the case of displacement, especially for larger panels.

FIGS. 17-18 show the first (receiver) and second (transmitter) configurations of the sixteen antenna phase elements. In the

FIGS. 17 and 18, as well as in the other illustrative embodiments of the island, the cavity 750 is defined in layers 106, 108, 109, with the island 1702 and the outermost portion 1704. For configurationsnas_FIGS .._ 17-e.18, -size —V -: - wwclo “pãcõtê“ is only 28 mm x 28 mm, with a height of 46 mil (on the page) (note 46 mil = 0.046 inches = 1.17 mm). In FIG. 17, RF chip 162 requires coplanar waveguide (CPW) feed antennas, so there are sixteen microwaves for CPW 1902 transitions. Chip 162 is in chip cavity 160. Also note power lines 114, reflectors 144, and ground flat slits 113. The configuration of FIG. 17 employs an earth plane slit per seam, whereas that of FIG. 18 two earth plane slits

113 by amendment 114. Note also that FIGS. 17 and 18 are top views in which no dashed (hidden) lines are used, for illustrative convenience - chip 162 in cavity 160 is located below island 1702, exactly as in FIGS. 7-14.

Accordingly, one or more embodiments of the invention 20 provide a package with a socket 160 for an RF chip 162 and an internal cavity 750 for planar antenna arrays. The antenna cavity 750 can be, for example, a circular or rectangular ring, or a large cavity for side-by-side configurations (an example of which is shown in FIGS. 15 and 16). Embodiments of the package can implement a planar phased array 25, preferably without the need for RF feed paths, and in one or more embodiments, with a considerably equal and relatively short feed line length. If a larger relative phased array is needed, more antenna elements can be used to increase the cavity size, as shown in FIGS. 9-12.

30 —----- ii - ^^ In view of the description above FIGS. 7-18, it will be desirable, in general terms, that a radio frequency chip integrated circuit package

-16 / 18with N coupled patch antennas, N at least two, include N in general planar seams 104, as well as at least one planar ground plane 110 internally spaced from N planar seams and considerably parallel to them. The ground plane is formed by N opening coupling slits of 113 coupling, and the slits are considerably opposite the splices 104 (in some cases, as in FIG. 18, there may be more than N slits, for example, 2N slots, two slits for each splice). The N 114 power lines are internally spaced ~~^r~ plãno '~ earth 110 is considerably parallel to it. At least one radio frequency chip 162 is spaced internally from the power lines 114 and coupled to the power lines 114 and the ground plane 110. Note which path, islands, and isolation areas as described for FIGS. 1-6 can also be used in the embodiments of FIGS. 7-18. N amendments 104 can be arranged to form a planar phased array.

A first substrate layer, such as that formed by the connecting film 126 and substrate 128, is spaced internally from the feed lines 114, and is formed by a chip receiving cavity 160, with chip 162 located in the chip receiving cavity. A second layer of substrate, such as that formed by films 106, 109 and substrate 108, is interposed in a region between the ground plane 110 and the plane defined by amendments 104. The splices 104 are formed in a first layer of metal, the ground plane 110 is formed in a second layer of metal, and the second layer of substrate defines an antenna cavity 750, with N generally planar splices 104 located in the antenna cavity 750.

In some cases, an island 702, 1702 is formed in the second layer of substrate, within the cavity 750, thus defining a ring shape of the cavity, and the generally planar N seams 104 are located in the shape of a ring, with the island 702, 1702 considerably opposite chip receiving cavity 160. “Considerably opposed”, as used in this context, is intended to describe a configuration ^ in ^ which ^ loops-overtake it · ““ ^^ rriíriimo, the chip-receiving cavity when viewed in the plane, to help support insertion loads during insertion of chip 162 into cavity 160. The

-17 / 18 The can and the cavity can have a variety of shapes, and can have the same or different shapes in any particular situation. In some examples, but without being limited to these cases, both can be considerably rectangular (rectangular here encompassing, but not limited to 5 to, square) when viewed in plan, while in other cases, also without restriction to them, both are considerably circular when viewed in plan.

In some cases, a third layer of substrate, such as that formed by substrate 112, is interposed in a region between the ground plane 10 110 and the feed lines 114, and the feed lines 114 are formed in a third layer of metal. In one or more embodiments, N reflectors 144 are spaced internally from the third substrate layer and in general opposite the coupling opening slits 113. Reflectors 144 can be located, for example, on an internal surface of the first layer of substrate. In addition, in some cases, a fourth layer of substrate, such as that formed by the bonding film 170 and substrate 172, is spaced internally from reflectors 144, with reflectors 144 being embedded between the first and fourth layers of substrate.

In other cases, as shown in FIGS. 15 and 16, the antenna cavity 750 is spaced apart from the chip receiving cavity 160 when viewed in plan, so that the charges incurred during insertion of the chip 162 into the chip receiving cavity 160 are considerably supported away from the antenna cavity (for example, by compression in layers 102, 108, 106, 109, 110, 112 immediately above chip 162).

In some cases, a cover, such as layer 102, is attached over the antenna cavity 750, and is partially supported by the island 702.

In another aspect, a method of manufacturing a radio frequency chip integrated circuit package of the type described includes providing a ^ description.type-packagewithout QÍChip^and162 inserted T ^ with the island ~ 30 702 as described, as well as the insertion of at least one chip

-18 / 18 radio frequency 162 in cavity 160, with island 702 supporting loads induced by inserting the chip in the cavity.

In yet another aspect, a method of manufacturing a radio frequency chip integrated circuit package of the type described includes providing a package of the type described, without the chip 162 inserted, and with the antenna cavity spaced apart from the receiving cavity. chip when viewed in plan (as shown, for example, in FIGS..J5 and 16), benncomoa; ~ '“- hnsêrçãfrdeplenomenenoson a radio frequency chip 162 in cavity 160, so that the charges incident during the insertion of chip 162 in cavity 10 of chip 160 are considerably supported away from the antenna cavity (for example, by compression in layers 102, 108, 106, 109, 110, 112 immediately above chip 162).

It is desirable and to be understood that the examples of embodiments of the invention described above can be implemented in several different ways.

With the guidance on the invention provided here, anyone with common knowledge of the subject will be able to think of other implementations of the invention. Although illustrative embodiments of the present invention 20 have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those embodiments, and that various other changes and modifications can be made by someone skilled in the art without departing from the scope spirit of the invention.