Nova Patents
ATE375552T1

Pipelines of multithreaded processor cores for packet processing

Abstract

A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.

Term

Term ended

Projected expiry passed 16 January 2023, 3.7 years ago.

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20 members in 11 offices

This recordMember, by publication datePriority claim1 more office is in the list below

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Priority claims
DocumentOfficeKindDate
5772302United States of AmericaA

Members20

Family members, oldest first
DocumentOfficeKind
US2003145173A1United States of AmericaA1
CA2473551A1CanadaA1
WO03065207A2World Intellectual Property Organization (WIPO)A2
AU2003209290A1AustraliaA1
TW200307214ATaiwan Province of ChinaA
KR20040017251ARepublic of KoreaA
WO03065207A3World Intellectual Property Organization (WIPO)A3
EP1481323A2European Patent Office (EPO)A2
TWI231914BTaiwan Province of ChinaB
HK1072298A1Hong Kong, ChinaA1
CN1820253AChinaA
KR100613923B1Republic of KoreaB1
US7181594B2United States of AmericaB2
EP1481323B1European Patent Office (EPO)B1
AT375552TAustriaT
ATE375552T1This recordAustriaT1
DE60316774D1GermanyD1
DE60316774T2GermanyT2
CN100440151CChinaC
CA2473551CCanadaC