Low power programmable processor

Graphics processor has a programmable ALU stage to enable a scalar arithmetic operation for processing a pixel packet. Or operand in a pixel packet is formatted with the S1.8 format to improve the dynamic range, and may be in different data formats. The graphics processor may be implemented as a configurable graphics pipeline. In one embodiment, the divider is, in response to a command from the host, the coupling elements of the graphics pipeline to be reconstructed the processing flow of pixel packets through a pipeline. Configurable test point selector may be used to monitor a selected subset of tap points of the count statistics and graphics pipeline for one or more conditions associated with each of the tap points subset of tap points. Pixels may be allocated as either an even or odd pixels of pixels, a pixel packet may be assigned the odd-numbered pixels and the even pixels, then interleaved to indicate the ALU latency. In one embodiment, the data packet is the triggering element of the graphics pipeline to find an identifier.ALU (Arighmetic Logic Unit), scalar arithmetic operations