Memory device with mode-selectable prefetch and clock-to-core timing

[Subject] A storage device according to a wide data transfer range is provided without applying stress to core speed too much. [Means for Solution] In a storage device, either [which was リトリーブ (ed) from a memory array] the 1st portion of data or the 2nd smaller portion is loaded to a data buffer according to prefetch mode select, next it is outputted from a storage device via a signal interface. A value which shows the number of the minimum cycles of a clock signal which will arise while performing continuation access to any one of the memory resources can be received and memorized in a composition circuit of a storage device. When this value shows the number N of clock cycles which is less than the number of thresholds, a storage device may transmit data relevant to the 1st address between a signal interface and a data buffer between each of N cycles of a clock signal. N exceeds the number of thresholds, or it is a storage device when equal, Between each of X cycle of a clock signal, it is between a signal interface and a memory buffer, Data relevant to the 1st address may be transmitted, next data relevant to the 2nd address may be transmitted between a signal interface and a memory buffer between each of X cycle of a clock signal, and X is an integral value of less than N. [Chosen drawing] Drawing 1