Compressing test responses using a compactor

This indication describes how to use and design the enforcement form and such an enforcement form of the compactor which compresses the test result of an integrated circuit. The compactor to indicate can be used as a part of design based on arbitrary scans, for example. Furthermore -- all of the compactor to indicate set an electronic design automatic ("EDA") software tool etc. To computer execution application -- a design and a simulation -- and/or, it can inspect. The enforcement form of the method of diagnosing failure in the compactor to indicate is also described.