Apparatus and method for aligning trellis demapped data

APPARATUS AND METHOD FOR ALIGNING TRELLIS

DEMAPPED DATA

FIELD OF THE INVENTION

0004The present invention generally relates to digital signal processing in a multi¬

0005channel, multi-point distribution system, and more particularly, to an apparatus and

0006method for aligning trellis demapped data with data output from a rate 1/2 Viterbi

0007decoder.

BACKGROUND OF THE INVENTION

0009Known in the art is the use of forward-error-correction that includes convolutional

0010encoding in the transmission of encoded digital data over a noisy channel from a

0011transmitter to a receiver. The Viterbi algorithm is commonly used to decode a

0012convo rationally encoded sequence of bits transmitted over a noisy channel. In particular,

0013the Viterbi algorithm employs a series of repetitive add-compare-select operations which

0014accept as input certain metrics computed on each symbol received from a demodulator.

0015For satellite, cable and terrestrial transmission of high data rate signals, such

0016computations need to be performed at very high rates.

0017In the case of a satellite transmission channel, it is customary to transmit some

0018particular punctured quaternary phase shift keyed (QPSK) code known to the receiver's convolutional decoder. In the case of a terrestrial or cable transmission channel, it is

0019customary to transmit some particular trellis code in conjunction with a given modulation

0020scheme, such as quadrature amplitude modulation (QAM), phase amplitude modulation

0021(PAM) or phase shift keyed (PSK) code known, tef the receiver's convolutional decoder.

0022Pragmatic trellis codes are a subset of the general class of trellis codes wherein only one

0023of n bits is encoded using a convolutional code and the remaining (n-1) bits are sent

0024unencoded. Pragmatic trellis decoding involves decoding an information stream

0025corresponding to an embedded rate 1/2 encoded stream followed by a demapping

0026operation to extract the remainder of information bits. In this process, it is important that

0027the demapped data be aligned with the decoded data. The present invention has been

0028contemplated in order to ensure this result.

SUMMARY OF THE INVENTION

0030Accordingly, it is an object of the present invention to provide an apparatus and

0031method for aligning a trellis demapped data stream with a data stream output from a rate

00321/2 Viterbi decoder.

0033It is another object to provide an apparatus and method for aligning a trellis

0034demapped data stream with a data stream output from a rate 1/2 Viterbi decoder that can

0035be implemented at either the transmitter or the receiver.

0036It is still another object to provide a means for efficiently and cost effectively

0037enabling data alignment in a multi-channel, multi-point distribution system. When implemented at the transmitter, these and other objects can be achieved in

0038accordance with the principles of the present invention with an encoder for receiving and

0039convolutionally encoding a first input signal to provide output of an encoded signal. A

0040delay unit receives and delays a second input signaj/to provide output of a delayed signal.

0041A symbol mapper receives and performs a symbol mapping operation in response to the

0042encoded signal and the delayed signal, wherein the delayed signal exhibits a

0043predetermined temporal alignment with respect to the encoded signal.

0044When implemented at the receiver, these and other objects can be achieved with a

0045decoder for providing output of a decoded signal. A reencoder reencodes the decoded

0046signal to provide output of a reencoded signal. A trellis demapper demaps the reencoded

0047signal to provide output of a trellis demapped signal. A delay unit receives and delays

0048output of the decoded signal so that the delayed decoded signal exhibits a predetermined

0049temporal alignment with respect to the trellis demapped signal.

BRIEF DESCRIPTION OF THE DRAWINGS

0051A more complete appreciation of this invention, and many of the attendant

0052advantages thereof, will be readily apparent as the same becomes better understood by

0053reference to the following detailed description when considered in conjunction with the

0054accompanying drawings, wherein:

0055FIG. 1 illustrates a preferred embodiment of the present invention wherein data

0056alignment is performed at the transmitter; and FIG. 2 illustrates another preferred embodiment of the present invention wherein

0057data alignment is performed at the receiver.

DETAILED DESCRIPTION O THE INVENTION

0059In the following detailed description, many specific details regarding known

0060functions and operations, which will be readily discernible to those skilled in the art, have

0061been omitted so as not to obscure the present invention. A more detailed explanation of

0062these details is provided in U.S. Patent No. 5,497,401, which is hereby incorporated by

0063reference.

0064Turning now to the drawings and referring to FIG. 1 , a preferred embodiment of

0065the present invention wherein data alignment is performed at the transmitter is shown. In

0066FIG 1, a transmitter 100 includes a rate 1/2 encoder 101, a prealignment delay 102, a

0067symbol mapper 103 and a modulator 104. During operation, rate 1/2 encoder 101 receives

00681-bit signal inputs, performs a known rate 1/2 convolutional encoding operation and

0069provides 2-bit signal outputs. Prealignment delay 102 receives (n-1) bit signal inputs

0070(where n equals a predetermined integer selected in accordance with system design

0071considerations; n=4 and n=5, for example, have been used in exemplary systems), and

0072delays output of the (n-1) bit signals for a predetermined time period. This delay period,

0073which serves to align the (n-1) bit signals at desired, predetermined temporal locations

0074with respect to the 2-bit signals output from rate 1/2 encoder 101, compensates for

0075latency in demapping at the receiver 110. Symbol mapper 103 receives the 2-bit signal outputs from rate 1/2 encoder 101 and the (n-1) bit signal outputs from prealignment

0076delay 102, performs a known symbol mapping operation by mapping the bits to a

0077particular amplitude and or phase level depending on the type of modulation that is

0078employed, and provides output of symbol mapped data to modulator 104. Modulator 104

0079receives the symbol mapped data, performs a known type of modulation (e.g., PSK,

0080PAM, QAM), and provides output of modulated data to receiver 110 as a series of

0081convolutionally encoded symbol packets.

0082At receiver 110, a demodulator 1 11 receives the convolutionally encoded symbol

0083packets provided from transmitter 100. Demodulator 111, which is known in the art,

0084demodulates the convolutionally encoded symbol packets, and applies demodulated

0085signal outputs to a rate 1/2 Viterbi decoder 112 and delay logic 113. Rate 1/2 Viterbi

0086decoder 112 (e.g., constraint length k=7) performs the Viterbi algorithm for trellis codes,

0087and employs add-compare-select means, path metric storage means and memory for the

0088survivor paths at each level in the trellis. Rate 1/2 Viterbi decoder 112 also takes care of

0089metric renormalizations to avoid a buildup and overflow of accumulated metrics. The 1-

0090bit signal outputs from the rate 1/2 Viterbi decoder 112 are applied to a convolutional

0091reencoder 114. For trellis codes, reencoder 114 serves to regenerate the best estimates of

0092the two transmitted of the rate 1/2 embedded code. The 2-bit signal outputs from

0093reencoder 114 are applied to a trellis demapper 115, which is responsible for making

0094symbol decisions. Specifically, trellis demapper 115 uses the 2-bit signal output from

0095reencoder 114 for subset selection together with delayed I and Q received symbol data forwarded thereto through delay logic 113 to make these symbol decisions. The (n-1) bit

0096signal outputs from trellis demapper 115, and the 1-bit signal outputs from the rate 1/2

0097Viterbi decoder 112 are provided for additional receiver processing. Delay logic 113

0098accounts for the delay introduced by the rate 1/2 Vfterbi decoder 1 12 and reencoder 114,

0099and serves to synchronize the data stream at the output of reencoder 114 with the received

0100symbol stream.

0101As shown in FIG. 1, transmitter 100 provides prealignment delay 102 to account

0102for the delay that occurs in the demapping operation at receiver 110. That is,

0103prealignment delay 102 compensates for the latency in receiver 110 between the 1-bit

0104signal outputs from rate 1/2 Viterbi decoder 112 and the remaining (n-1) bit signal

0105outputs from trellis demapper 115. In other words, prealignment delay 102 ensures that

0106the (n-1) bit signals output from trellis demapper 115 are aligned at desired,

0107predetermined temporal locations with respect to the 1-bit signals output from the rate 1/2

0108Viterbi decoder 112.

0109Referring now to FIG. 2, another preferred embodiment of the present invention

0110wherein data alignment is performed at the receiver is shown. In FIG. 2, a transmitter 200

0111includes a rate 1/2 encoder 201, a symbol mapper 202 and a modulator 203. In

0112construction and operation, the transmitter 200 of FIG. 2 is essentially the same as the

0113transmitter 100 of FIG. 1, except that the transmitter 100 of FIG. 1 includes prealignment delay 102 while transmitter 200 of FIG. 2 does not. Accordingly, this embodiment

0114provides data alignment at receiver 210, rather than at transmitter 200.

0115The receiver 210 includes a demodulator 21 1, a rate 1/2 Viterbi decoder 212,

0116delay logic 213, a reencoder 214, a delay adjustment 215 and a trellis demapper 216. In

0117construction and operation, the receiver 210 of FIG. 2 is essentially the same as the

0118receiver 110 of FIG. 1, except that the receiver 210 of FIG. 2 includes delay adjustment

0119215 while the receiver 110 of FIG. 1 does not. In FIG. 2, delay adjustment 215 ensures

0120that the 1-bit signals output from the rate 1/2 Viterbi decoder 212 are aligned at desired,

0121predetermined temporal locations with respect to the (n-1) bit signals output from trellis

0122demapper 216. In this manner, efficient, synchronized system operation is achieved.

0123In accordance with the principles of the present invention, signal outputs from a

0124Viterbi decoder are properly temporally aligned with signal outputs from a trellis

0125demapper in a digital multi-channel, multi-point distribution system.

0126While there have been illustrated and described what are considered to be

0127preferred embodiments of the present invention, it will be understood by those skilled in

0128the art that various changes and modifications may be made, and equivalents may be

0129substituted for elements thereof without departing from the ✓true scope of the present

0130invention. In addition, many modifications may be made without departing from the

0131central scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the

0132invention, but that the present invention includes all embodiments falling within the

0133scope of the appended claims.